DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/27/2026 has been entered.
Response to Arguments
Claim Rejections – 35 USC 101
Applicant's arguments filed 7/27/2026 have been fully considered but they are not persuasive.
Applicant asserts the claims do not merely recite abstract mathematical formulas but specific computational steps designed to address a technical problem in a particular technical context, namely, discrete optimization problems with higher-order evaluation functions.
Examiner respectfully disagrees. Under step 2A Prong 1, the claim recites abstract ideas as indicated in the rejections below.
Applicant asserts the processing apparatus comprising “an accelerator card coupled to the host processor and the memory” which further includes “a storage circuit” and a “processor circuit” are explicitly performed by the “processor circuit” within the accelerator card, and the claimed invention provides a specific technical solution to the technical problem of efficiently solving discrete optimization problems with higher-order evaluation functions without increasing the number of independent variables which improves the ability of a data processing apparatus to handle a wider variety of discrete optimization problems more efficiently. Examiner respectfully disagrees. The improvement is a result of performing the abstract ideas and is not an improvement in technology because the recited “accelerator card”, “storage circuit”, and “processor circuit” do not provide meaningful limits for performing the optimization method. The claims do not adequately reflect a technical improvement provided by the accelerator card.
Applicant asserts the “accelerator card” with a dedicated “processor circuit” and “storage circuit” is not a mere recitation of generic computer components and represents a specialized hardware component tailored for enhanced performance in this technical field. Its existence as a separate, purpose-built component, distinct from the host processor, demonstrates a specific architectural arrangement. Thus, the argument that the claims are at a “high level of generality lacks foundation given the structural and functional specificity of the accelerator card and its constituents; and such concrete architectural arrangement, where computational burden is offloaded to a specialized accelerator, is a specific implementation that meaningfully limits the abstract idea to a practical application and far from a mere instruction to “apply it” on a generic computer.
Examiner respectfully disagrees. The “processor circuit” and “storage circuit” are recited at a high level of generality such that it is the equivalent of reciting the “processor circuit” and “storage circuit” to “apply it” with the judicial exception. The “processor circuit” and “storage circuit” do not provide meaningful limits for performing the optimization method and the claims do not reflect a technical improvement provided by the “processor circuit” and “storage circuit”. Even considering the claims as a whole, it is the equivalent of reciting an optimization method and to “apply it” with a distributed processing system.
Applicant asserts the combination of the host processor, memory and specifically the accelerator card with its storage and processor circuits constitutes an inventive concept, and the architecture is not “well-understood, routine, conventional activity” for solving higher-order discrete optimization problems; rather, it is a specific technical solution to a technical problem.
Examiner respectfully disagrees. The “accelerator card”, “storage circuit” and “processor circuit” are evaluated as the equivalent of “apply it”. Furthermore, the inventive concept is provided by the abstract ideas of performing the optimization method because the “accelerator card”, “storage circuit” and “processor circuit” do not meaningfully limit the method such that it is a specific circuit other than generic computer components.
Claim Objections
Claims 1, 8-9 are objected to because of the following informalities:
Claims 1, 8-9 line 4 of the last paragraph, change “sate” to “state”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2-4 recites the limitation "the plurality of second coefficients". There is insufficient antecedent basis for this limitation in the claim because the claims have been amended to recite “M by N second coefficients” or “relevant second coefficients” and thus it is unclear which set of second coefficients is being referred to. For examination purposes, Examiner interprets “the plurality of second coefficients” as the “relevant second coefficients”.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a data processing apparatus, which is a statutory category of invention (machine).
At Step 2A Prong 1, Examiner notes that the claims are directed towards an abstract. The claim language has been reproduced below:
A data processing apparatus of searching for, as an optimum solution of a discrete optimization problem, a ground state of an Ising type evaluation function corresponding to an Ising model converted from the discrete optimization problem, the Ising model including a plurality of state variables, the plurality of state variables comprising N state variables (N is an integer of greater than or equal to two), the Ising type evaluation function including the plurality of state variables and at least a k-th order term (k is an integer of greater than or equal to three) (mathematical relationship), the data processing apparatus comprising: a memory;
a host processor coupled to the memory;
an accelerator card coupled to the host processor and the memory, the accelerator card including: a storage circuit configured to store a first coefficient and M by N second coefficients (M is an integer of greater than or equal to two), the first coefficient being a coefficient indicating a magnitude of interaction among k state variables (mathematical relationship), the k state variables being a part of the plurality of variables and being included in the kth order term of the Ising type evaluation function, each second coefficient of the M by N second coefficients being a coefficient indicating an influence of a corresponding one of the N state variables on a corresponding one of M auxiliary variables (characterization of variables/data used in the claimed mathematical concepts);
and a processor circuit coupled to the storage circuit, the processor circuit being configured to perform processing including: the processor circuit calculating a first local field indicative of a change amount of the kth order term in a case where a value of a first state variable being one of the k state variables changes based on a value of a first variable and the first coefficient read from the storage circuit (mathematical calculation), the first variable being one of the M auxiliary variables and being obtained based on values of the k state variables and relevant second coefficients, the relevant second coefficients comprising N second coefficients retrieved from the M by N second coefficients (mathematical relationship) stored in the storage circuit;
and the processor circuit determining, based on a result of comparison, whether to allow a change in the value of the first state variable, the result of the comparison being obtained by comparing between a predetermined value (mathematical relationship) and an evaluation function change amount in a case where the value of the first sate variable changes (mathematical calculation), the evaluation change amount being derived from a product of: (i) a sum of the first local field and a second local field indicative of a change amount of quadratic and lower-order terms of the Ising type evaluation function in the case where the value of the first state variable changes (mathematical calculation), and (II) a change amount of the first state variable (mathematical relationship).
At Step 2A Prong 2, the additional elements are bolded above. The additional elements “data processing apparatus”, “memory”, “host processor”, “accelerator card”, “storage circuit”, and “processor circuit” do not integrate the abstract ideas into a practical application because the computer elements, which are recited at a high level of generality, provide conventional computer functions that do not impose any meaningful limits on practicing the abstract ideas as they are merely the equivalent of reciting “apply it” to the judicial exception. See MPEP 2106.05(f). Furthermore, the limitations of storing in a storage circuit are an insignificant extra solution activity. Even when viewed in combination, these additional elements do not integrate the recited judicial exception into a practical application and the claim is directed to the judicial exception.
At Step 2B, the additional elements do not, alone or in combination, amount to significantly more than the recited judicial exception. As set forth in step 2A prong 2 analysis, the additional elements of the “data processing apparatus”, “memory”, “host processor”, “accelerator card”, “storage circuit”, and “processor circuit” are the equivalent of merely adding the words “apply it” to the judicial exception. Furthermore, the storing in memory is understood by the courts as well understood, routine, and conventional. See MPEP 2106.05(d). Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible.
Regarding claims 2-7, the claims merely recite additional data used on the judicial exception, further mathematically limit the mathematical concepts of claim 1, or provide additional mathematical calculations performed by the processor. They do not include additional elements that would require further analysis under steps 2A prong 2 and step 2B.
Regarding claim 8, it is directed to a non-transitory computer-readable medium storing a program that could be executed by the apparatus of claim 1. All steps executed in claim 8 are executed by the apparatus in claim 1 as configured. The claim 1 analysis applies equally to claim 8.
Regarding claim 9, it is directed to a method that would be practiced by the apparatus of claim 1. All steps performed by the method of claim 9 are executed by the apparatus in claim 1 as configured. The claim 1 analysis applies equally to claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew T Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
Prosecution Insights