DETAILED ACTION
This office action is responsive to communication filed on December 22, 2025.
Response to Arguments
Applicant's arguments filed December 22, 2025 have been fully considered but they are not persuasive.
Applicant agues, with respect to claims 1 and 11, that the thickness of Ahn's circuit area (CA) is not greater than, but is less than, the thickness of Ahn's optical black sensor area OBS. Therefore, the cited references fail to disclose, teach or suggest "wherein the peripheral circuit region has a thickness greater than a thickness of the OPB region" as claimed. Thus, this feature is a distinction over the cited references.
The Examiner respectfully disagrees. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The primary reference in the rejections of claims 1 and 11, Cheung (US 2011/0032391) teaches a peripheral circuit region surrounding the pixel array region (The Examiner interprets the region outside of the pixel array region (10, 12, 14) in figure 3 to be a peripheral circuit region as this region includes an analog circuit and two digital circuits.), and where the peripheral circuit region has a thickness greater than a thickness of the OPB region (The peripheral circuit region (i.e. the region outside of the voltage application pixel region (10) in figure 3) has a thickness greater than a thickness of the OPB region (14, see figure 3).). The Ahn et al. (US 2014/0263962) secondary reference also teaches a peripheral circuit region (i.e. the circuit area (CA) and pad area (PA) in figure 1, paragraphs 0052 and 0053) surrounding the pixel array region (SA, see figure 1), and where the peripheral circuit region (CA, PA) has a thickness greater than a thickness of the OPB region (OBS, see figure 1).
Therefore, the rejection is maintained by the Examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920) and Ahn et al. (US 2014/0263962).
Consider claim 1, Cheung teaches:
A solid-state image pickup device, comprising:
a pixel array region (i.e. including pixel regions 10, 12 and 14 of figures 1 and 3, paragraphs 0013 and 0014) in which pixels (e.g. 10 or 12 of figure 2) each including a photoelectric conversion unit (photodiode, PD) are disposed two-dimensionally in rows and columns (see paragraphs 0015 and 0017, figures 1-3), wherein
the pixel array region includes a voltage application pixel (dummy pixel, 10) between an effective pixel (active pixel, 12) and an optical black (OPB) pixel (“dark reference pixel”) of the pixel array region (As shown in figures 1, the voltage application pixels (10) are found between the active pixel array (12) and the dark reference pixel array, paragraphs 0013 and 0014. For instance, the bottom side of the dummy pixel ring (10) includes voltage application pixels which are located between effective pixels of the active pixel array (12) and optical black pixels of the “dark reference pixel array”.), the voltage application pixel (10) being one of the pixels to which a fixed voltage is normally applied (For example, a reset gate (RG) is always “ON” in order to apply a fixed voltage and prevent charge from being collected in the dummy pixels (10), as detailed in paragraph 0017.), and
wherein the OPB pixel defines an OPB region (“dark reference pixel array”, figure 1) having a rectangular shape oriented horizontally (see figure 2, paragraphs 0014 and 0020),
wherein a peripheral circuit region surrounds the pixel array region (The Examiner interprets the region outside of the pixel array region (10, 12, 14) in figure 3 to be a peripheral circuit region as this region includes an analog circuit and two digital circuits.), and
where the peripheral circuit region has a thickness greater than a thickness of the OPB region (The peripheral circuit region (i.e. the region outside of the voltage application pixel region (10) in figure 3) has a thickness greater than a thickness of the OPB region (14, see figure 3).).
Cheung teaches that the invention “may be well adapted to other image sensors”, paragraph 0013. However, Cheung does not explicitly teach that the photoelectric conversion unit has one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film.
Tashiro et al. similarly teaches an image sensor (figure 14) including a pixel array (i.e. of pixels 100, paragraph 0227), wherein each pixel (100) includes a photoelectric conversion unit (photoelectric conversion unit, 101, paragraph 0227), a transfer transistor (switch, 501, paragraph 0228), a reset transistor (reset transistor, 102, paragraph 0056), an amplification transistor (amplifier transistor, 104, paragraph 0228) and a select transistor (selection transistor, 105, paragraph 0056).
However, Tashiro et al. additionally teaches that the photoelectric conversion unit (101) has one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film (The photoelectric conversion unit (101) has a photoelectric conversion layer (205), paragraph 0057, see figure 1A. As detailed in paragraph 0087, “the photoelectric conversion layer 205 includes quantum dots 10”. As detailed in paragraph 0041, the material of the quantum dots may be “InGaAs” (i.e. a chemical semiconductor). As detailed in paragraph 0043, “germanium (Ge) is used for the material of the quantum dots”.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion unit taught by Cheung comprise a photoelectric conversion layer of one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film as taught by Tashiro et al. for the benefit of reducing lattice defects and noise (Tashiro et al., paragraph 0039). Additionally, this combination only involves a simple substitution of one known element (i.e. a photoelectric conversion layer of one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film of Tashiro et al.) for another (i.e. the photodiode of Cheung) to obtain predictable results such as enabling image capture.
However, the combination of Cheung and Tashiro et al. does not explicitly teach that the OPB region borders an entire perimeter of the voltage application pixel of the pixel array region.
Ahn et al. similarly teaches a solid-state image pickup device (figure 1) having a pixel array region (image sensor area, SA) including an active pixel array (active pixel sensor area, APS) with a dummy pixel sensor area (DPS) formed at an edge portion thereof (see figure 1), and an optical black sensor area (OBS) located outside of the perimeter of the active pixel sensor area (APS, see figure 1, paragraph 0052).
However, Ahn et al. further teaches that the OPB region (OBS) has a rectangular shape that borders an entire perimeter of the voltage application pixel of the pixel array region (APS, see figure 1), and a peripheral circuit region (i.e. the circuit area (CA) and pad area (PA) in figure 1, paragraphs 0052 and 0053) surrounding the pixel array region (SA, see figure 1), wherein the peripheral circuit region (CA, PA) has a thickness greater than a thickness of the OPB region (OBS, see figure 1).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the OPB region and peripheral circuit region taught by the combination of Cheung and Tashiro et al. have a rectangular shape that borders an entire perimeter of the voltage application pixel of the pixel array region as taught by Ahn et al. for the benefit of providing an image sensor capable of reducing or preventing occurrence of problems such as distortion of an image signal or degradation of the color (Ahn et al., paragraph 0004).
Cheung teaches that the effective pixel region (12) and the voltage application pixel region (10) each have a rectangular shape oriented horizontally with a length greater than a width (see figure 1, “rectangular” in paragraph 0013). Ahn et al. teaches that the OPB region (OBS) has a rectangular shape that surrounds the entire perimeter of the effective pixel region (APS, see figure 1). Therefore, regarding claim 1, the combination of Cheung, Tashiro et al. and Ahn et al. teaches that the OPB pixel defines an OPB region having a rectangular shape oriented horizontally with a length greater than a width that borders the entire perimeter of the voltage application pixel of the pixel array region.
Consider claim 2, and as applied to claim 1 above, Cheung further teaches that in the voltage application pixel (10), a reset transistor (reset gate, RG, figure 2) of the voltage application pixel is normally controlled to an on state such that the fixed voltage is normally applied (For example, a reset gate (RG) is always “ON” in order to apply a fixed voltage and prevent charge from being collected in the dummy pixels (10), as detailed in paragraph 0017.).
Consider claim 3, and as applied to claim 1 above, Cheung does not explicitly teach that the photoelectric conversion unit includes an electrode portion for extracting charges generated in the photoelectric conversion unit.
Tashiro et al. further teaches that in the voltage application pixel (see figure 1A), an electrode portion (second electrode, 209) for extracting charge generated in the photoelectric conversion unit (101, see paragraphs 0057 and 0059) is connected to the ground (see figure 1A) without the intervention of a pixel transistor such that the fixed voltage is normally applied (As shown in the embodiment of figure 1A, the electrode portion (209) is connected to ground via node B and capacitor 103, without intervention of a pixel transistor.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion element taught by the combination of Cheung and Tashiro et al. include an electrode portion for extracting charges generated in the photoelectric conversion unit connected to the ground without the intervention of a pixel transistor such that the fixed voltage is normally applied as taught by Tashiro et al. for the benefit of reducing lattice defects and noise (Tashiro et al., paragraph 0039). Additionally, this combination only involves a simple substitution of one known element (i.e. an electrode portion connected to ground without an intervening transistor as taught by Tashiro et al.) for another (i.e. the electrode portion connected to ground via the intervening transistor taught by the combination of Cheung and Tashiro et al.) to obtain predictable results such as enabling image capture.
Consider claim 4, and as applied to claim 3 above, Cheung further teaches that the fixed voltage (V+) applied to the voltage application pixel (10) is a high voltage (see paragraph 0017) and is different than the voltage applied to the effective pixel (12) of the pixel array region (i.e. V+ versus VReset, figure 2). Cheung does not explicitly teach that V+ is higher than VReset. However, as stated in MPEP 2144.05(II), “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Determining optimal voltages for the fixed voltage and the regular pixel voltage, in order to perform the noise reduction taught by Cheung, would only require routine skill in the art. Additionally, as detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Therefore, the voltage relationships claimed in claim 4, do not differentiate the apparatus of claim 3 from the prior art.
Consider claim 6, and as applied to claim 1 above, Cheung further teaches that the voltage application pixel (10) is disposed in one row and one column on the innermost side of an OPB region (“dark reference pixel array”) of the pixel array region (see figure 1).
Consider claim 8, and as applied to claim 1 above, Cheung further teaches that the voltage application pixel (10) is disposed in one row and one column on an outermost circumference of an effective pixel region (12) of the pixel array region (see figure 1) and a plurality of rows and a plurality of columns including one row and one column on the innermost side of an OPB region (“dark reference pixel array”, see figure 1).
Claims 11-14, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920), Ota (US 2008/0211954) and Ahn et al. (US 2014/0263962).
Consider claim 11, Cheung teaches:
An electronic apparatus (figure 1), comprising:
a solid-state image pickup device, comprising:
a pixel array region (i.e. including pixel regions 10, 12 and 14 of figures 1 and 3, paragraphs 0013 and 0014) in which pixels (e.g. 10 or 12 of figure 2) each including a photoelectric conversion unit (photodiode, PD) are disposed two-dimensionally in rows and columns (see paragraphs 0015 and 0017, figures 1-3), wherein
the pixel array region includes a voltage application pixel (dummy pixel, 10) between an effective pixel (active pixel, 12) and an optical black (OPB) pixel (“dark reference pixel”) of the pixel array region (As shown in figures 1, the voltage application pixels (10) are found between the active pixel array (12) and the dark reference pixel array, paragraphs 0013 and 0014. For instance, the bottom side of the dummy pixel ring (10) includes voltage application pixels which are located between effective pixels of the active pixel array (12) and optical black pixels of the “dark reference pixel array”.), the voltage application pixel (10) being one of the pixels to which a fixed voltage is normally applied (For example, a reset gate (RG) is always “ON” in order to apply a fixed voltage and prevent charge from being collected in the dummy pixels (10), as detailed in paragraph 0017.), and
wherein the OPB pixel defines an OPB region (“dark reference pixel array”, figure 1) having a rectangular shape oriented horizontally (see figure 2, paragraphs 0014 and 0020),
wherein a peripheral circuit region surrounds the pixel array region (The Examiner interprets the region outside of the pixel array region (10, 12, 14) in figure 3 to be a peripheral circuit region as this region includes an analog circuit and two digital circuits.), and
where the peripheral circuit region has a thickness greater than a thickness of the OPB region (The peripheral circuit region (i.e. the region outside of the voltage application pixel region (10) in figure 3) has a thickness greater than a thickness of the OPB region (14, see figure 3).).
Cheung teaches that the invention “may be well adapted to other image sensors”, paragraph 0013. However, Cheung does not explicitly teach that the photoelectric conversion unit has one of a chemical semiconductor, amorphous silicon, germanium, or a quantum dot photoelectric conversion film.
Tashiro et al. similarly teaches an image sensor (figure 14) including a pixel array (i.e. of pixels 100, paragraph 0227), wherein each pixel (100) includes a photoelectric conversion unit (photoelectric conversion unit, 101, paragraph 0227), a transfer transistor (switch, 501, paragraph 0228), a reset transistor (reset transistor, 102, paragraph 0056), an amplification transistor (amplifier transistor, 104, paragraph 0228) and a select transistor (selection transistor, 105, paragraph 0056).
However, Tashiro et al. additionally teaches that the photoelectric conversion unit (101) has one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film (The photoelectric conversion unit (101) has a photoelectric conversion layer (205), paragraph 0057, see figure 1A. As detailed in paragraph 0087, “the photoelectric conversion layer 205 includes quantum dots 10”. As detailed in paragraph 0041, the material of the quantum dots may be “InGaAs” (i.e. a chemical semiconductor). As detailed in paragraph 0043, “germanium (Ge) is used for the material of the quantum dots”.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion unit taught by Cheung comprise a photoelectric conversion layer of one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film as taught by Tashiro et al. for the benefit of reducing lattice defects and noise (Tashiro et al., paragraph 0039). Additionally, this combination only involves a simple substitution of one known element (i.e. a photoelectric conversion layer of one of a chemical semiconductor, germanium, or a quantum dot photoelectric conversion film of Tashiro et al.) for another (i.e. the photodiode of Cheung) to obtain predictable results such as enabling image capture.
However, the combination of Cheung and Tashiro et al. does not explicitly teach that the electronic apparatus comprises an optical system and a digital signal processor that processes signals received from the solid-state image pickup device.
Ota similarly teaches an image sensor (5, figure 1) comprising an array of pixels (paragraph 0037), wherein each pixel (figures 2 and 3) includes a charge storage portion (53, paragraph 0043) connected to the gate of a source follower transistor (62, paragraph 0046, see figure 3) and to a reset transistor (63) which resets the charge storage portion (53, paragraph 0047).
However, Ota additionally teaches that the electronic apparatus (figure 1) comprises an optical system (e.g. comprising taking lens, 1, paragraphs 0032 and 0033) and a digital signal processor (e.g. digital signal processing section, 17) that processes signals received from the solid-state image pickup device (see paragraph 0036).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the electronic apparatus taught by the combination of Cheung and Tashiro et al. comprise an optical system and a digital signal processor as taught by Ota as this only involves combining prior art elements according to known methods to yield predictable results such as generating digital image data (Ota, paragraph 0036).
However, the combination of Cheung, Tashiro et al. and Ota does not explicitly teach that the OPB region borders an entire perimeter of the voltage application pixel of the pixel array region.
Ahn et al. similarly teaches a solid-state image pickup device (figure 1) having a pixel array region (image sensor area, SA) including an active pixel array (active pixel sensor area, APS) with a dummy pixel sensor area (DPS) formed at an edge portion thereof (see figure 1), and an optical black sensor area (OBS) located outside of the perimeter of the active pixel sensor area (APS, see figure 1, paragraph 0052).
However, Ahn et al. further teaches that the OPB region (OBS) has a rectangular shape that borders an entire perimeter of the voltage application pixel of the pixel array region (APS, see figure 1), and a peripheral circuit region (i.e. the circuit area (CA) and pad area (PA) in figure 1, paragraphs 0052 and 0053) surrounding the pixel array region (SA, see figure 1), wherein the peripheral circuit region (CA, PA) has a thickness greater than a thickness of the OPB region (OBS, see figure 1).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the OPB region and peripheral circuit region taught by the combination of Cheung, Tashiro et al. and Ota have a rectangular shape that borders an entire perimeter of the voltage application pixel of the pixel array region as taught by Ahn et al. for the benefit of providing an image sensor capable of reducing or preventing occurrence of problems such as distortion of an image signal or degradation of the color (Ahn et al., paragraph 0004).
Cheung teaches that the effective pixel region (12) and the voltage application pixel region (10) each have a rectangular shape oriented horizontally with a length greater than a width (see figure 1, “rectangular” in paragraph 0013). Ahn et al. teaches that the OPB region (OBS) has a rectangular shape that surrounds the entire perimeter of the effective pixel region (APS, see figure 1). Therefore, regarding claim 1, the combination of Cheung, Tashiro et al., Ota and Ahn et al. teaches that the OPB pixel defines an OPB region having a rectangular shape oriented horizontally with a length greater than a width that borders the entire perimeter of the voltage application pixel of the pixel array region.
Consider claim 12, and as applied to claim 11 above, Cheung further teaches that in the voltage application pixel (10), a reset transistor (reset gate, RG, figure 2) of the voltage application pixel is normally controlled to an on state such that the fixed voltage is normally applied (For example, a reset gate (RG) is always “ON” in order to apply a fixed voltage and prevent charge from being collected in the dummy pixels (10), as detailed in paragraph 0017.).
Consider claim 13, and as applied to claim 11 above, Cheung does not explicitly teach that the photoelectric conversion unit includes an electrode portion for extracting charges generated in the photoelectric conversion unit.
Tashiro et al. further teaches that in the voltage application pixel (see figure 1A), an electrode portion (second electrode, 209) for extracting charge generated in the photoelectric conversion unit (101, see paragraphs 0057 and 0059) is connected to the ground (see figure 1A) without the intervention of a pixel transistor such that the fixed voltage is normally applied (As shown in the embodiment of figure 1A, the electrode portion (209) is connected to ground via node B and capacitor 103, without intervention of a pixel transistor.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion element taught by the combination of Cheung and Tashiro et al. include an electrode portion for extracting charges generated in the photoelectric conversion unit connected to the ground without the intervention of a pixel transistor such that the fixed voltage is normally applied as taught by Tashiro et al. for the benefit of reducing lattice defects and noise (Tashiro et al., paragraph 0039). Additionally, this combination only involves a simple substitution of one known element (i.e. an electrode portion connected to ground without an intervening transistor as taught by Tashiro et al.) for another (i.e. the electrode portion connected to ground via the intervening transistor taught by the combination of Cheung and Tashiro et al.) to obtain predictable results such as enabling image capture.
Consider claim 14, and as applied to claim 13 above, Cheung further teaches that the fixed voltage (V+) applied to the voltage application pixel (10) is a high voltage (see paragraph 0017) and is different than the voltage applied to the effective pixel (12) of the pixel array region (i.e. V+ versus VReset, figure 2). Cheung does not explicitly teach that V+ is higher than VReset. However, as stated in MPEP 2144.05(II), “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Determining optimal voltages for the fixed voltage and the regular pixel voltage, in order to perform the noise reduction taught by Cheung, would only require routine skill in the art. Additionally, as detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Therefore, the voltage relationships claimed in claim 4, do not differentiate the apparatus of claim 3 from the prior art.
Consider claim 16, and as applied to claim 11 above, Cheung further teaches that the voltage application pixel (10) is disposed in one row and one column on the innermost side of an OPB region (“dark reference pixel array”) of the pixel array region (see figure 1).
Consider claim 18, and as applied to claim 11 above, Cheung further teaches that the voltage application pixel (10) is disposed in one row and one column on an outermost circumference of an effective pixel region (12) of the pixel array region (see figure 1) and a plurality of rows and a plurality of columns including one row and one column on the innermost side of an OPB region (“dark reference pixel array”, see figure 1).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920) and Ahn et al. (US 2014/0263962) as applied to claim 1, and further in view of Yamaguchi (US 2009/0236504).
Consider claim 9, and as applied to claim 1 above, the combination of Cheung, Tashiro et al. and Ahn et al. does not explicitly teach that the photoelectric conversion unit is an N-type semiconductor thin film.
Yamaguchi similarly teaches an image pickup device including a pixel (figure 1B) having a photoelectric conversion film (photoelectric conversion semiconductor thin film, 14, paragraphs 0064 and 0070).
However, Yamaguchi additionally teaches that the photoelectric conversion unit is an N-type semiconductor thin film (“The semiconductor thin film may be formed using at least two semiconductor thin film layers having different n-type impurity concentrations.” paragraph 0070).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion unit taught by the combination of Cheung, Tashiro et al. and Ahn et al. be an N-type semiconductor thin film as taught by Yamaguchi for the benefit of providing a photo-sensing device having high sensitivity to incident light (Yamaguchi, paragraph 0017).
Consider claim 10, and as applied to claim 9 above, Cheung further teaches that signal charges of the photoelectric conversion unit are pores (“a type of photodiode that collects holes” paragraph 0017).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920), Ota (US 2008/0211954) and Ahn et al. (US 2014/0263962) as applied to claim 11 above, and further in view of Yamaguchi (US 2009/0236504).
Consider claim 19, and as applied to claim 11 above, the combination of Cheung, Tashiro et al., Ota and Ahn et al. does not explicitly teach that the photoelectric conversion unit is an N-type semiconductor thin film.
Yamaguchi similarly teaches an image pickup device including a pixel (figure 1B) having a photoelectric conversion film (photoelectric conversion semiconductor thin film, 14, paragraphs 0064 and 0070).
However, Yamaguchi additionally teaches that the photoelectric conversion unit is an N-type semiconductor thin film (“The semiconductor thin film may be formed using at least two semiconductor thin film layers having different n-type impurity concentrations.” paragraph 0070).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion unit taught by the combination of the combination of Cheung, Tashiro et al., Ota and Ahn et al. be an N-type semiconductor thin film as taught by Yamaguchi for the benefit of providing a photo-sensing device having high sensitivity to incident light (Yamaguchi, paragraph 0017).
Consider claim 20, and as applied to claim 19 above, Cheung further teaches that signal charges of the photoelectric conversion unit are pores (“a type of photodiode that collects holes” paragraph 0017).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920) and Ahn et al. (US 2014/0263962) as applied to claim 1 above, and further in view of Toyoguchi et al. (US 2014/0078354).
Consider claim 5, and as applied to claim 1 above, the combination of Cheung, Tashiro et al. and Ahn et al. does not explicitly teach that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit.
Toyoguchi et al. similarly teaches a solid-state image pickup device (figure 2) having an effective pixel region (pixel array, 2, paragraph 0022) and a dummy pixel region (dummy pixel unit, 3, paragraph 0022).
However, Toyoguchi et al. additionally teaches that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit (“In the example where the photoelectric conversion element 20 is formed in the dummy pixel 12, the solid-state imaging apparatus 100 may have a shielding layer for shielding the dummy pixel unit 3 from light.” paragraph 0039).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the voltage application pixels taught by the combination of Cheung, Tashiro et al. and Ahn et al. include a light shielding film on the upper side of the photoelectric conversion unit as taught by Toyoguchi et al. for the benefit of reducing interference between an effective pixel and a dummy pixel (Toyoguchi et al., paragraph 0006).
Consider claim 7, and as applied to claim 1 above, Cheung further teaches that the voltage application pixel (10) is disposed in a plurality of rows and a plurality of columns of a region of the pixel array region (see figure 1, paragraph 0013).
However, the combination of Cheung, Tashiro et al. and Ahn et al. does not explicitly teach that the voltage application pixel region is an OPB region.
Toyoguchi et al. similarly teaches a solid-state image pickup device (figure 2) having an effective pixel region (pixel array, 2, paragraph 0022) and a dummy pixel region (dummy pixel unit, 3, paragraph 0022).
However, Toyoguchi et al. additionally teaches that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit (“In the example where the photoelectric conversion element 20 is formed in the dummy pixel 12, the solid-state imaging apparatus 100 may have a shielding layer for shielding the dummy pixel unit 3 from light.” paragraph 0039).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the voltage application pixel region taught by the combination of Cheung, Tashiro et al. and Ahn et al. be an OPB region as taught by Toyoguchi et al. for the benefit of reducing interference between an effective pixel and a dummy pixel (Toyoguchi et al., paragraph 0006).
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cheung (US 2011/0032391) in view of Tashiro et al. (US 2016/0035920), Ota (US 2008/0211954) and Ahn et al. (US 2014/0263962) as applied to claim 11 above, and further in view of Toyoguchi et al. (US 2014/0078354).
Consider claim 15, and as applied to claim 11 above, the combination of Cheung, Tashiro et al., Ota and Ahn et al. does not explicitly teach that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit.
Toyoguchi et al. similarly teaches a solid-state image pickup device (figure 2) having an effective pixel region (pixel array, 2, paragraph 0022) and a dummy pixel region (dummy pixel unit, 3, paragraph 0022).
However, Toyoguchi et al. additionally teaches that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit (“In the example where the photoelectric conversion element 20 is formed in the dummy pixel 12, the solid-state imaging apparatus 100 may have a shielding layer for shielding the dummy pixel unit 3 from light.” paragraph 0039).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the voltage application pixels taught by the combination of Cheung, Tashiro et al., Ota and Ahn et al. include a light shielding film on the upper side of the photoelectric conversion unit as taught by Toyoguchi et al. for the benefit of reducing interference between an effective pixel and a dummy pixel (Toyoguchi et al., paragraph 0006).
Consider claim 17, and as applied to claim 11 above, Cheung further teaches that the voltage application pixel (10) is disposed in a plurality of rows and a plurality of columns of a region of the pixel array region (see figure 1, paragraph 0013).
However, the combination of Cheung, Tashiro et al., Ota and Ahn et al. does not explicitly teach that the voltage application pixel region is an OPB region.
Toyoguchi et al. similarly teaches a solid-state image pickup device (figure 2) having an effective pixel region (pixel array, 2, paragraph 0022) and a dummy pixel region (dummy pixel unit, 3, paragraph 0022).
However, Toyoguchi et al. additionally teaches that the voltage application pixel has a light shielding film on the upper side of the photoelectric conversion unit (“In the example where the photoelectric conversion element 20 is formed in the dummy pixel 12, the solid-state imaging apparatus 100 may have a shielding layer for shielding the dummy pixel unit 3 from light.” paragraph 0039).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the voltage application pixel region taught by the combination of Cheung, Tashiro et al., Ota and Ahn et al. be an OPB region as taught by Toyoguchi et al. for the benefit of reducing interference between an effective pixel and a dummy pixel (Toyoguchi et al., paragraph 0006).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Inoue (US 2009/0108389) teaches a solid-state image pickup device with a peripheral circuit region thicker than an imaging element region (see figure 9).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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