DETAILED ACTION
This is in response to communication filed on 12/22/2025.
Status of Claims
Claims 1 – 20 are pending, of which claims 1, 11, and 17 are in independent form.
Specification
In light of applicant’s amendments to the abstract and specification, the examiner withdraws the previous objection to the specification.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al., U.S. Patent Application 2021/0141649 (hereinafter referred to as Xu) in view of Thibado et al., U.S. Patent Application 2020/0205299 (hereinafter referred to as Thibado).
Referring to claim 1, Xu discloses “An apparatus comprising: a circuit board; an active interposer coupled with the circuit board” (Figs. 24B-D package with substrate 2480 and [0248] each graphics engine tile 1610A-1610D and associated memory 1626A-1626D reside on separate chiplets, which are bonded to a base die or base substrate. [0322] Fig. 24B description including substrate 2480. [0325] the chiplets can be integrated into a base die or base chiplet using active interposer technology); “a” “processor die coupled with the active interposer,” “wherein the” “processor die includes” “processor resources configured to execute instructions for a multi-die system on chip (SoC) device” (Fig. 24C logic 2472, 2474 and [0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500); and “a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality of a die of the multi-die SoC device to enable validation of the” “processor die” ([0344] - [0350] FPGA based emulator, first and second processing units may be graphics processing units, validating performance metrics and determining whether an identified performance aspect is in the database).
Xu does not appear to explicitly disclose “a graphics processor die.” However, Xu does disclose dice of an SoC ([0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500). Further, Xu discloses “a graphics processor” as part of the SoC (Fig. 25) and the graphics processor including multiple cores/fragment processors (Figs. 26A-B).
As such, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to utilize graphics processor dice on Xu’s SoC and to use emulation to enable validation of a graphics processor die.
Xu does not appear to explicitly disclose “an active interposer coupled with the circuit board via a debug package” and “a graphics processor die coupled with the active interposer via the debug package.”
However, Thibado discloses another multiple die package ([0014]) wherein “an active interposer coupled with the circuit board via a debug package” and “a graphics processor die coupled with the active interposer via the debug package” ([0014] MCP multi-chip package, attaching multiple dies. [0027] companion component is a graphics processing unit or an FPGA. In another embodiment the companion component is a debug device. Figs. 1A, 1B interposer and ball grid array. Figs. 4A, 5 interposer 420 with CPU package 460 and companion chip package 480).
Xu and Thibado are analogous art because they are from the same field of endeavor, which is multiple die package development.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Xu and Thibado before him or her, to modify the teachings of Xu to include the teachings of Thibado so that the apparatus comprises an active interposer with a debug package.
The motivation for doing so would have been to provide a means for debugging/testing the multiple die package.
Therefore, it would have been obvious to combine Thibado with Xu to obtain the invention as specified in the instant claim.
As per claim 2, Xu discloses “the active interposer includes a connector to the”
“processor die that is controlled by the FPGA” ([0325] the chiplets can be integrated into a base die or base chiplet using active interposer technology. Fig. 24C logic 2472, 2474 and [0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500. [0344] - [0350] FPGA based emulator, first and second processing units may be graphics processing units, validating performance metrics and determining whether an identified performance aspect is in the database)
As above, Xu does not appear to explicitly disclose “a graphics processor die.” However, Xu does disclose dice of an SoC ([0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500). Further, Xu discloses “a graphics processor” as part of the SoC (Fig. 25) and the graphics processor including multiple cores/fragment processors (Figs. 26A-B).
As such, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to utilize graphics processor dice on Xu’s SoC and to use emulation to enable validation of a graphics processor die.
As per claim 4, Xu discloses “the active interposer includes first power rails to power the” “processor die” ([0322], [0327] interconnect structure providing power or ground associated with operation of logic 2472/2474).
As above, Xu does not appear to explicitly disclose “a graphics processor die.” However, Xu does disclose dice of an SoC ([0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500). Further, Xu discloses “a graphics processor” as part of the SoC (Fig. 25) and the graphics processor including multiple cores/fragment processors (Figs. 26A-B).
As such, it would have been obvious to one of ordinary skill in the art at the time of Applicant’s filing to utilize graphics processor dice on Xu’s SoC and to use emulation to enable validation of a graphics processor die.
As per claim 5, Xu discloses “the active interposer includes digital logic and second power rails to power the digital logic” (Figs. 24C and 24D along with [0325] base die, [0330] substrate 2480 with logic in a base die. [0322], [0327] interconnect structure providing power or ground associated with operation of logic 2472/2474).
As per claim 6, Xu discloses “the digital logic includes base die digital logic
associated with the multi-die SoC device” (Figs. 24C and 24D along with [0325] base die, [0330] substrate 2480 with logic in a base die. [0324] multiple dies. [0320] SoC integrated circuit and Fig. 25 SoC 2500).
Allowable Subject Matter
Claims 3 and 7 – 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11 – 20 are allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims in this application is the inclusion of the specific details of a field-programmable gate array (FPGA) establishing communication with a graphics compute die (GCD) associated with a chiplet for a multi-die system on chip (SoC) device, receiving signals at the FPGA via a system interconnect and, in response to the signals, driving interconnects to the GCD via general-purpose input/output (GPIO) to cause the GCD to boot into an operational state, and emulating functionality of the die of the multi-die SoC device to facilitate execution of a silicon validation test on the GCD, as are now included in independent claim 11, in combination with the other elements recited, which is not found in the prior art of record.
The primary reason for the allowance of the claims in this application is the inclusion of the specific details of a system including an active interposer coupled to a circuit board via a debug package, a graphics processor die coupled with the active interposer via the debug package, the graphics processor to execute instructions for a multi-die system on chip device, a field-programmable gate array (FPGA) including hardware to emulate system interface and power management circuitry of a system die of the SoC, the FPGA to enable validation of the graphics processor die separate from the system die, wherein the active interposer connector to the graphics processing die is controlled via GPIO connectors of the FPGA as are now included in independent claim 17, in combination with the other elements recited, which is not found in the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive.
Applicant argues, on pages 8 – 9 that
However, Xu's FPGA-based emulator is described as being used to collect performance metrics when an executable object is performed on processing units. While an FPGA-based emulator is disclosed, this emulator is used for performance monitoring/profiling of an executable object. This performance monitoring/profiling is not performed to 'emulate functionality of a die of the multi-die SoC device.' Xu's disclosure appears to be about adapting executable objects between different architectures and collecting performance data, rather than using an FPGA to emulate die functionality for silicon validation purposes. Accordingly, applicant respectfully requests the withdrawal of the rejection, at the least, as to claim 1 and its associated dependent claims.
The examiner disagrees. First, Applicant describes validation at [0210] and states “Validation is a process that is performed to determine that a hardware design works as intended.”
Xu's [0344] teaches "The processor 2710 may receive performance metrics 2702 and performance metrics 2704 as input. The performance metrics 2702 may indicate the performance of the executable object if performed on an existing ( or first) processing unit with a first architecture. The performance metrics 2704 may indicate the performance of the executable object if performed on other ( or second) processing unit with a second architecture." This 'emulates functionality of a die of the multi-die SoC device.'
Xu's [0344] goes on to describe performance metrics "Some examples of the performance metrics 2702 and 2704 may include, but not limited to, a response speed, a maximum memory space required to run software, a storage space occupied, an elapsed number of cycles, a memory traffic, statistics information of an instruction prediction unit, utilization of different execution pipelines, an amount of sampling going to memory, power metrics, cache hit/miss counts, bus or memory read/write counts, a hardware unit occupancy, hardware unit input available, and output ready counters or the like." Further, Xu's [0347] teaches "At each decision point, the performance metrics may be used to determine, for example, what proportion of time the data is available at an input of a hardware unit, what proportion of time the completed data is available at an output of the hardware unit, and whether a difference between the two proportions reaches a threshold." This is considered to be equivalent to Applicant's description at [0210] "Validation is a process that is performed to determine that a hardware design works as intended."
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN G SNYDER whose telephone number is (571)270-1971. The examiner can normally be reached on M-F 8:00am-4:30pm (flexible).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN G SNYDER/Primary Examiner, Art Unit 2184