DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is Final and is in response to the claims filed 03/12/2026. Claims 1, 3-20 are currently pending, of which claim 1 is currently rejected. Claims 3-20 are currently objected.
Response to Arguments
Applicant’s arguments filed on 03/12/2026 have been fully considered.
Specification: Objection to the title has been withdrawn necessitated by amendment to the title.
35 U.S.C. 112(f): Claim interpretation under 35 U.S.C. 112(f) has been withdrawn necessitated by amendments.
35 U.S.C. 112(b): Rejection under 35 U.S.C. 112(b) has been withdrawn necessitated by amendments.
35 U.S.C. 102: Applicant’s arguments regarding the 35 U.S.C. 102 have been considered, and are found persuasive. However, see new grounds of rejection necessitated by amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Hayata et al. (U.S. Patent No.: US 11495289 B2), hereinafter “Hayata”, in view of Zidan et al. (U.S. Patent Application Publication No.: US 20200357459 A1), hereinafter “Zidan”, further in view of Chen (U.S. Patent No.: US 7675488 B2), hereinafter “Chen”.
Regarding Claim 1, Hayata teaches:
A calculation system comprising:
a plurality of multiplying circuits arrayed to form a plurality of rows and a plurality of columns (Fig. 5, e.g., shows memory cells 21 (plurality of multiplying elements) in memory cell array 20.), and configured to multiply a plurality of first signals by respective weights to generate a plurality of calculation results (Column 2 Lines 48-50, e.g., computation circuit performs multiply-accumulate operation in each bit line using weights stored in memory cells; Column 5, Lines 40-50, e.g., computational circuit is shown in Fig. 5. Voltage is applied to word lines 22 (first signals); Fig. 5, e.g., shows line word lines 22);
a plurality of adding circuits configured to calculate a sum of calculation results in each column among the plurality of calculation results to generate a plurality of second signals individually for the plurality of columns (Column 2 Lines 48-50, e.g., computation circuit performs multiply-accumulate operation in each bit line (adding elements) using weights stored in memory cells; Fig. 5, e.g., shows bit lines 23 in each column outputting results (calculation results) to column selection circuit 25; Column 6 Lines 29-31, e.g., Current flows from bit lines 23 (second signals));
a first processing circuit configured to receive the plurality of second signals generated by the adding circuits (Fig. 5, e.g., shows Column Selection Circuit 25 (first processing circuit) receiving outputs (second signals) from bit lines 23 (adding elements)), and to extract values corresponding to certain second signals among the plurality of second signals (Column 6 Lines 16-20, e.g., Column selection circuit 25 selects (extracts) bit lines 23 (transmitting second signals) to be connected to computation circuit 26); and
a second processing circuit including a plurality of address circuits corresponding to the plurality of second signals … (Fig. 5, e.g., shows Computation circuits 26 (second processing circuit including plurality of address circuits); Column 6 Lines 16-20, e.g., Column selection circuit 25 selects (extracts) bit lines 23 (transmitting second signals) to be connected to computation circuit 26), the second processing circuit being configured to selectively enable address circuits among the plurality of address circuits, the address circuits corresponding to the certain second signals among the plurality of address circuits (Column 6 Lines 33-36, e.g., computation circuit 26 (address circuit) compares magnitude of two bit lines 23 (transmitting second signals) and outputs binary data of 0 or 1 (enable or disable))…
Hayata does not teach:
a second processing circuit including … and a shift register that includes a plurality of register circuits corresponding to the plurality of address circuits, … the shift register being configured to be reconfigurable, each of the plurality of register circuits including an input node, an output node, and a register,
the second processing circuit being further configured to reconfigure the shift register by forming a connection between the input node and the output node through the register in each of a part of register circuits among the plurality of register circuits, and by forming a connection between the input node and the output node while bypassing the register in each of remaining register circuits among the plurality of register circuits.
However, in the same field of endeavor, Zidan teaches a shift register used for post-processing accumulation of a sequence of signals representing bit values. Zidan explains “One or more sets of bit lines can be sensed in response to each sequence of applied sense voltage levels to determine partial products from each set of bit lines for each sequence of applied sense voltage levels.” (Zidan: ¶0005). Zidan further explains “Each accumulator 525 can be configured to sum each partial product to the current content of a corresponding shift register 530 and then load the sum into the corresponding shift register 530. Each shift register 530 can be configured to shift the sum in a given direction.” (Zidan: 0039)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine the accumulators and shift registers (including input and output nodes) as taught by Zidan with the Computation circuits 26 as taught by Hayata. This modification would have been obvious because implementing an accumulator and a shift register in the post-processing of the memory cell array would allow for the use of larger bit inputs to be sequentially inputted and multiplied-accumulated without the need of increasing the memory array size.
Hayata in view of Zidan do not teach:
the second processing circuit being further configured to reconfigure the shift register by forming a connection between the input node and the output node through the register in each of a part of register circuits among the plurality of register circuits, and by forming a connection between the input node and the output node while bypassing the register in each of remaining register circuits among the plurality of register circuits.
However, Chen teaches:
the [plurality of control units] being further configured to reconfigure the shift register by forming a connection between the input node and the output node through the register in each of a part of register circuits among the plurality of register circuits (Fig. 3, e.g., shows each register 304 and 310 being connected by input selector 302 output selector 306; Column 5 Lines 13-38, e.g., control units 108 and 110 control input selector and output selector, respectively), and by forming a connection between the input node and the output node while bypassing the register in each of remaining register circuits among the plurality of register circuits (Fig. 3, e.g., shows bypass selector circuit 332; Column 6 Lines 8-10, e.g., bypass selector circuit 332 bypasses shift register unit 104).
Further, Zidan does not show a specific architecture of the shift register. Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine architecture of the shift register unit including the input selector, output selector, and bypass selector 332 as taught by Chen with the shift registers as taught by Hayata in view of Zidan. One would have been motivated to combine these references because both references disclose shift registers, and Chen enhances the model of Hayata in view of Zidan because “the number of the channels may be flexibly adjusted to support different resolutions.” (Chen: Column 1 Lines 65-67)
Allowable Subject Matter
Claims 3-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner' s statement of reasons for allowance:
Hayata teaches a neural network computation circuit that includes memory cell array 20, Column selection circuit 25, and computation circuit 26. Column selection circuit 25 is configured to select among bitlines to be inputted to At least one computation circuit 26. Hayata does not specifically teach or suggest a first processing circuit generate a plurality of upper flag values to represent upper k levels, nor does it teach a first processing circuit generate a plurality of lower flag values to represent lower k levels. Instead, Hayata teaches selecting pairs of bitlines depending on the column to be used for the computation based on a column selection signal. Therefore, Hayata does not teach or suggest the combination of claims 3 and 12, including the limitations “wherein the first processing circuit is configured to generate a plurality of upper flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of upper K levels among the plurality of second signals, where K is an integer of 1 or more” and “wherein the first processing circuit is configured to generate a plurality of lower flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of lower K levels among the plurality of second signals, where K is an integer of 1 or more”.
Kulkarni et al. (U.S. Patent Application Publication No.: US 20210397930 A1), hereinafter “Kulkarni” – teaches a memory die that performs multiply-accumulate operations using an array of memory cells inside memory structure 326, and further discloses using sense blocks 350 per page of memory cells, which includes sense circuitry 870, processor 892, and data latches 894. See Figs. 5 and 8, and ¶0031-0063. Kulkarni does not specifically teach or suggest a first processing circuit generate a plurality of upper flag values to represent upper k levels, nor does it teach a first processing circuit generate a plurality of lower flag values to represent lower k levels. Instead, Kulkarni teaches sense blocks receiving bitline data to perform sensing of voltage before outputting data for storing data bits. Therefore, Kulkarni does not teach or suggest the combination of claims 3 and 12, including the limitations “wherein the first processing circuit is configured to generate a plurality of upper flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of upper K levels among the plurality of second signals, where K is an integer of 1 or more” and “wherein the first processing circuit is configured to generate a plurality of lower flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of lower K levels among the plurality of second signals, where K is an integer of 1 or more”.
Fujiwara et al. (U.S. Patent No.: US 12511102 B2), hereinafter “Fujiwara” – teaches a memory device 100A that includes memory array 112, one or more registers 115, one or more logic circuits 116, and computation circuit 117. Fujiwara does not teach or suggest a first processing circuit generate a plurality of upper flag values to represent upper k levels, nor does it teach a first processing circuit generate a plurality of lower flag values to represent lower k levels. Instead, Fujiwara teaches registers 115 to latch bitline data to be used in computations performed in logic circuit 116 and computation circuit 117. Therefore, Fujiwara does not teach or suggest the combination of claims 3 and 12, including the limitations “wherein the first processing circuit is configured to generate a plurality of upper flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of upper K levels among the plurality of second signals, where K is an integer of 1 or more” and “wherein the first processing circuit is configured to generate a plurality of lower flag values individually for the plurality of second signals, each of which indicates whether a corresponding second signal is one of second signals of lower K levels among the plurality of second signals, where K is an integer of 1 or more”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.H.D./
Carlos H. De La GarzaExaminer, Art Unit 2182
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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