DETAILED ACTION
This action is responsive to Applicant’s reply filed July 1st 2026. This action is made final.
Status of the Claims
Claim 28 is amended.
Claim 29 is canceled.
Claim 41 is added.
Claim status is currently pending and under examination for claims 19-28 and 30-41 of which independent claims are 19 and 30.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s arguments regarding the art rejections are moot in view of the new grounds of rejection necessitated by Applicant’s amendment.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following are the references relied upon in the rejections below:
Zhang (US 20200175362 A1)
Liu, He, et al. "Video-based prediction for header-height control of a combine harvester." 2019 IEEE Conference on Multimedia Information Processing and Retrieval (MIPR). IEEE, 2019.
Lin, Ji, et al. "Mcunet: Tiny deep learning on iot devices." Advances in neural information processing systems 33 (2020): 11711-11722.
Claims 19-20, 22-25, 30-31, 33-36 and 41 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang / Liu / Lin.
Regarding Claim 19, Zhang teaches:
A method implemented using one or more processors and comprising ([0008] “The program code, when executed by a processor of an electronic device, causes the electronic device to identify a new task for a ML model to perform”):
obtaining a plurality of images … ([0046] “the camera in the sensor(s) 365 may be used to capture images and/or videos of objects for tasks such as object detection and/or classification for multi-task based lifelong learning.”);
training a plurality of candidate multi-task dense prediction (MT-DP) machine learning models using neural network layers sampled from a search space of neural network layers having different parameters using a network architecture search (NAS) ([0053] “The system 500 includes a controller 505 that, upon identifying a new task to be performed, uses deeper and wider operators 510 and 515, respectively, (e.g., such as Net2Deeper and Net2Wider operators) to generate a plurality of child network architectures 520. The deeper operator 510 adds layer(s) to the existing network architecture to perform the new task, while the wider operator 515 widens existing layer(s) of the existing network architecture to perform the new task. The child network architectures 520 are expanded versions of the original/prior/existing network architecture that are generated to perform the new tasks.”
[0024] “this efficient AutoML algorithm is referred to as a Regularize, Expand and Compress (REC). In these embodiments, REC involves first searching a best new neural network architecture for the given tasks in a continuous learning mode. Tasks may include image classification, image segmentation, object detection and/or many other computer vision tasks. The best neural network architecture can solve multiple different tasks simultaneously, without catastrophic forgetting of old tasks' information, even when there is no access to old tasks' training data.”
[0078] “the system may expand the network architecture for the ML model to perform the new task using AutoML, for example, by training child network architectures using wider and deeper operators as discussed with regard to FIG. 5 above.”
[0056] “to narrow down the architecture searching space and save training time, network transformation based AutoML is utilized to accelerate the new network searching.”
Neural architecture search is used to generate and train a plurality of child network architectures. Child network architectures are expanded versions of an existing network architecture that are designed to perform old and new tasks, which includes image segmentation tasks (dense prediction), therefore each child network architecture is a candidate multi-task dense prediction machine learning model. Since a plurality of child network architectures are generated and trained from neural architecture search, it is implied that an architecture searching space is comprised of neural network layers having different parameters.),
the training of the plurality of candidate MT-DP machine learning models performed based on a satisfaction of a performance metric for the plurality of candidate MT-DP machine learning models ([0068] “After the controller 505 generates the child network architecture(s), the child network architecture(s) achieve an accuracy Aval on the validation set of task t and this will be used as the reward signal Rt to update the controller 505. The controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture.”
[0023] “Reinforcement learning framework involves observing a network's performance on a validation set as a reward signal, and giving higher probabilities to network architectures that have higher performances than network architectures that have lower performances to adapt the network model.”
See Figure 5, Reference Character “520” describing children network architectures are trained to get rewards for a controller.
Child network architectures (‘plurality of candidate MT-DP machine learning models’) are trained to achieve an accuracy (performance metric) on a validation set. Child network architectures with higher performances (accuracies) are given a higher probability (a larger expected reward). A controller maximizes an expected reward to find the optimal child network architecture (larger rewards are given to architectures with higher accuracies), therefore training of the child network architectures is performed based on a satisfaction of a performance metric (accuracy) for the child network architectures, the satisfaction being a high accuracy (an optimal architecture).);
processing the plurality of images using at least one of the plurality of candidate MT-DP machine learning models to perform a plurality of … prediction tasks including one or more … prediction tasks that generate pixel-level predictions for the plurality of images ([0024] “Tasks may include image classification, image segmentation, object detection and/or many other computer vision tasks. The best neural network architecture can solve multiple different tasks simultaneously”
[0046] “the camera in the sensor(s) 365 may be used to capture images and/or videos of objects for tasks such as object detection and/or classification for multi-task based lifelong learning”
The best child neural network architecture (‘candidate MT-DP machine learning model’) can perform image classification and segmentation tasks (‘prediction tasks’) using images captured from a camera. The best architecture can perform image segmentation, therefore the architecture can generate pixel-level predictions for a plurality of images.);
However, Zhang does not teach operating an agricultural vehicle in an agricultural plot based on pixel-level predictions, which is taught by Liu:
obtaining a plurality of images of crops growing in an agricultural plot ((P. 310, Abstract) “Crop presence detection is performed by training a classifier on texture features and the percentage of crops in the field can be estimated. Then the time to lift the header is predicted based on observing the trend of crop presence.”
(P. 314, Sec. IV-C, ¶3) “Figure 5 shows some probability maps at frame number 90, 120, 150 and 180 in one testing clip. The colored regions (both orange and blue) represent the coarsely-segmented field region, and the color shows the probability: blue indicates more likely to be crop area; orange indicates no crop.”
See Figure 5 on P. 314 depicting colored regions on frames (‘images’) of beans (‘crops’) in a field (‘agricultural plot’). Blue regions represent the presence of beans (beans are growing in the field).);
processing the plurality of images using … [a machine learning model] to perform a plurality of agricultural prediction tasks including one or more agricultural prediction tasks that generate pixel-level predictions for the plurality of images ((P. 312-313, Sec. III-D, ¶1) “We use the pre-trained classifier mentioned above to classify every divided square into either crops or empty field. Then the results of this classification process are merged to generate one probability map of crops using a voting method: the probability of each field pixel that contains crop presence is voted by the number of squares which include that pixel position.”
(P. 312, Sec. III-A, Last Paragraph) “A pre-trained classifier is used to separate the crop region from the empty field.”
(P. 311, Sec. I, ¶3) “a crop presence classifier is designed to estimate the crop percentage in each frame.”
A pre-trained classifier is used to separate crop regions and estimate crop percentage for each frame (‘image’), therefore the classifier performs a plurality of agricultural prediction tasks. For each pixel in a frame, the classifier generates a probability that a pixel contains a crop (crop presence), therefore the classifier performs an agricultural prediction task that generates pixel-level predictions for a plurality of frames.);
and operating one or more agricultural vehicles in the agricultural plot based on the pixel- level predictions for the plurality of images ((P. 311, Sec. III.A, First Paragraph) “the goal of this framework is to analyze the field region in front of the combine harvester and predict when the header should be raised. As mentioned in Section I, we assume that the combine harvester is in its normal harvesting state, which means the front reel is rotating and harvesting crops. The output of the system is the predicted future time that indicates when the reel should be lifted. Furthermore, we assume the operator is making correct adjustments while operating the combine; therefore, the video contains the ground truth for the correct time to raise the header. Then the predicted time can be validated”
(P. 315, Sec. V, ¶1) “a video-based header-height prediction framework for a combine harvester. The time to lift the header is predicted based on the crop estimation using a crop presence classifier”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the method of Zhang with the technique disclosed by Liu to use a machine learning model to detect the presence of crops. By using a machine learning model to detect the presence of crops, agricultural vehicles can be operated autonomously to avoid or target crops in a field, thereby automating harvesting activities.
Furthermore, the combined method of Zhang / Liu does not teach neural architecture search corresponding to hardware-based constraints of a target edge computing system to be operated in association with an agricultural plot, which is taught by Lin:
the NAS to correspond to hardware-based constraints of a target edge computing system to be operated in association with the agricultural plot ((P. 1, Sec. 1, ¶1) “The number of IoT devices based on always-on microcontrollers is increasing rapidly at a historical rate, reaching 250B [2], enabling numerous applications including … precision agriculture, automated retail, etc. These low-cost, low-energy microcontrollers give rise to a brand new opportunity of tiny machine learning (TinyML). By running deep learning models on these tiny devices, we can directly perform data analytics near the sensor, thus dramatically expand the scope of AI applications”
(P. 3, Sec. 3.1, ¶1-2) “TinyNAS is a two-stage neural architecture search method that first optimizes the search space to fit the tiny and diverse resource constraints, and then performs neural architecture search within the optimized space. With an optimized space, it significantly improves the accuracy of the final model. … To fit the tiny and diverse resource constraints of different microcontrollers, we scale the input resolution and the width multiplier of the mobile search space [44]. … Our goal is to find the best search space configuration S∗ that contains the model with the highest accuracy while satisfying the resource constraints”
Neural architecture search is modified to only include architectures that meet resource constraints of a microcontroller that is used in precision agriculture (therefore a microcontroller is a target edge computing system to be operated in association with an agricultural plot).).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu with the neural architecture search disclosed by Lin to modify neural architecture search to only include architectures that meet resource constraints of a target hardware. By modifying neural architecture search to only include architectures that meet resource constraints of a target hardware, machine learning models that satisfy resource constraints can be configured and embedded in microcontrollers with limited resources, thereby allowing machine learning models to perform accurate sensor-based data analytics for precision agriculture.
Regarding Claims 20 and 31, the combined method of Zhang / Liu / Lin teaches:
the method of claim 19, further comprising jointly training the NAS and one or more of the plurality of candidate MT-DP machine learning models ([0053] “includes a controller 505 that, upon identifying a new task to be performed, uses deeper and wider operators 510 and 515, respectively, (e.g., such as Net2Deeper and Net2Wider operators) to generate a plurality of child network architectures 520.”
[0068] “After the controller 505 generates the child network architecture(s), the child network architecture(s) achieve an accuracy Aval on the validation set of task t and this will be used as the reward signal Rt to update the controller 505. The controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture.”
See [0078] describing child network architectures (‘plurality of candidate MT-DP machine learning models’) are trained.
A controller generates child network architectures and child network architectures are generated from an architecture searching space (see [0056]), therefore the controller performs neural architecture search. The accuracies of the child network architectures are used as rewards to update (‘train’) the controller. Generated child network architectures are trained to achieve an accuracy, therefore when an updated controller generates child network architectures, both the controller and architectures are trained, thereby jointly training the neural architecture search (performed by the controller) and the child network architectures.).
Regarding Claims 22 and 33, the combined method of Zhang / Liu / Lin teaches:
the method of claim 19, wherein the satisfaction of the performance metric is determined based on an accuracy of a corresponding candidate MT-DP machine learning model ([0068] “After the controller 505 generates the child network architecture(s), the child network architecture(s) achieve an accuracy Aval on the validation set of task t and this will be used as the reward signal Rt to update the controller 505. The controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture.”
See Figure 5, Reference Character “520” describing children network architectures are trained to get rewards for a controller.
Child network architectures (‘candidate MT-DP machine learning models’) are trained to achieve an accuracy (‘performance metric’) on a validation set. Child network architectures with higher performances (accuracies) are given a higher probability (a larger expected reward), see [0023]. A controller maximizes an expected reward to find the optimal child network architecture, therefore finding the optimal architecture is determining a satisfaction of accuracy for a child network architecture.).
Regarding Claims 23 and 34, the combined method of Zhang / Liu / Lin teaches:
the method of claim 19, wherein the at least one of the plurality of candidate MT-DP machine learning models is selected based on at least one of an accuracy metric or latency metric ([0068] “he controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture. For example, the empirical approximation of this AutoML reinforcement can be expressed as follows”
[0079] “use AutoML as discussed above to expand the network architecture to achieve the desired performance accuracy or standards. Thereafter, the system may compress the network architecture to maintain model size.”).
Regarding Claims 24 and 35, the combined method of Zhang / Liu / Lin teaches:
the method of claim 23, further including training the selected candidate MT-DP machine learning model to convergence ([0069] “The final child network architecture … is trained to convergence with hard and soft labels by the following loss function”).
Regarding Claims 25 and 36, the combined method of Zhang / Liu / Lin teaches:
The method of claim 24, further including deploying the selected candidate MT-DP machine learning model ([0078] “the system may remove and shrink layers from the selected best child network architecture to compress the child network architecture”
[0063] “network architecture 600 has been expanded and compressed as discussed above to perform multiple tasks (i.e., old or existing task(t−1) 605 and new task(t) 610).”).
Regarding Claim 30, the rejection of claim 19 is incorporated. The difference in scope being:
At least one non-transitory computer readable medium comprising instructions that cause at least one processor to at least ([0008] “a non-transitory, computer-readable medium comprising program code for lifelong learning is provided. The program code, when executed by a processor of an electronic device,”).
Regarding Claim 41, the combined method of Zhang / Liu / Lin teaches:
the method of claim 19, wherein the training the plurality of candidate MT-DP machine learning models further includes jointly training the NAS and the plurality of candidate MT-DP machine learning models (([0053] “includes a controller 505 that, upon identifying a new task to be performed, uses deeper and wider operators 510 and 515, respectively, (e.g., such as Net2Deeper and Net2Wider operators) to generate a plurality of child network architectures 520.”
[0068] “After the controller 505 generates the child network architecture(s), the child network architecture(s) achieve an accuracy Aval on the validation set of task t and this will be used as the reward signal Rt to update the controller 505. The controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture.”
See [0078] describing child network architectures (‘plurality of candidate MT-DP machine learning models’) are trained.
A controller generates child network architectures and child network architectures are generated from an architecture searching space (see [0056]), therefore the controller performs neural architecture search. The accuracies of the child network architectures are used as rewards to update (‘train’) the controller. Generated child network architectures are trained to achieve an accuracy, therefore when an updated controller generates child network architectures, both the controller and architectures are trained, thereby jointly training the neural architecture search (performed by the controller) and the child network architectures.),
wherein the training of the NAS is based on performance metrics corresponding to each of the plurality of candidate MT-DP machine learning models (A controller is updated by using rewards generated from the accuracies achieved by child network architectures on a validation set. Therefore, neural architecture search (performed by the controller) is based on performance metrics (accuracies) corresponding to each of the child network architectures.).
The following are the references relied upon in the rejections below:
Li (US 20220230048 A1)
Claims 21 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang / Liu / Lin / Li.
Regarding Claims 21 and 32, the combined method of Zhang / Liu / Lin teaches:
the method of claim 19, wherein the satisfaction of the performance metric is determined … [for] a corresponding candidate MT-DP machine learning model ([0068] “After the controller 505 generates the child network architecture(s), the child network architecture(s) achieve an accuracy Aval on the validation set of task t and this will be used as the reward signal Rt to update the controller 505. The controller 505 maximizes (or increases) the expected reward to find the optimal, desired, or best child network architecture.”
See Figure 5, Reference Character “520” describing children network architectures are trained to get rewards for a controller.
Child network architectures (‘candidate MT-DP machine learning models’) are trained to achieve an accuracy (‘performance metric’) on a validation set. Child network architectures with higher performances (accuracies) are given a higher probability (a larger expected reward), see [0023]. A controller maximizes an expected reward to find the optimal child network architecture, therefore finding the optimal architecture is determining a satisfaction of accuracy for a child network architecture.).
However, the combination does not teach determining satisfaction of a performance metric based on a latency of a corresponding candidate machine learning model, which is taught by Li:
wherein the satisfaction of the performance metric is determined based on a latency of a corresponding candidate … machine learning model ([0060-0061] “the system can be configured to train the candidate neural network until stopping criteria are met, such as a number of iterations for training, a maximum period of time, convergence, or when a minimum accuracy threshold is met. The system can generate performance metrics for the accuracy and latency of the candidate neural network architecture on the target computing resources, in addition to other performance metrics”
[0057] “the stopping criteria can specify threshold ranges predetermined to be “optimal.” For example, a threshold range for optimal latency can be a threshold range from a theoretical or measured minimum latency achieved by the target computing resources. The theoretical or measured minimum latency can be based on physical characteristics of the computing resources, such as the minimum amount of time necessary for components of the computing resources to be able to physically read and process incoming data”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu / Lin with the stopping criteria disclosed by Li to stop candidate model training based on latency. By stopping candidate model training based on latency, computer resources and time can be saved by not letting models train beyond reaching a desired latency.
The following are the references relied upon in the rejections below:
Gupta, Suyog, and Berkin Akin. "Accelerator-aware neural network design using automl." arXiv preprint arXiv:2003.02838 (2020).
Claims 26-27 and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang / Liu / Lin / Gupta.
Regarding Claims 26 and 37, the combined method of Zhang / Liu / Lin teaches the method of claim 19, however the combination does not teach a layer type selected from inverted bottleneck and fused inverted bottleneck, which is taught by Gupta:
wherein the different parameters include a layer type selected from inverted bottleneck (IBN) and fused-IBN ((P. 3, Sec. 2.2, ¶1-2) “As a result, crafting the search space to include building blocks that are known to improve hardware utilization … our search space includes the inverted bottleneck convolution block with a depthwise convolution layer that is used in MobileNetV2 (Sandler et al., 2018). In addition to this baseline block, we introduce a fused inverted bottleneck convolution block that fuses the initial expansion convolution with the depthwise convolution into a single full convolution (Figure 3). Originally this block expands the depth of the input tensor and performs a “cheaper” depthwise convolution with a larger depth dimension. Although, the fused alternative performs a more “expensive” full convolution at a larger depth dimension, it can utilize the hardware resources better and provide more trainable parameters which can be a good latency-accuracy trade-off. In Figure 3, on the top, we observe that the fused inverted bottleneck block has a better runtime as well as more trainable parameters compared to the baseline inverted bottleneck. However, on the bottom, fused version has more than 2x worse runtime compared to the baseline version”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu / Lin with the search space disclosed by Gupta to create a search space comprised of IBN and fused IBN convolution blocks. By creating a search space comprised of IBN and fused IBN convolution blocks, machine learning engineers can design a model based on hardware constraints, thereby allowing engineers to balance the trade-off between hardware resource utilization and runtime.
Regarding Claims 27 and 38, the combined method of Zhang / Liu / Lin teaches the method of claim 19, however the combination does not teach wherein the different parameters include a kernel size, which is taught by Gupta:
wherein the different parameters include a kernel size ((P. 3, Sec. 2.2, ¶1-2) “As a result, crafting the search space to include building blocks that are known to improve hardware utilization … our search space includes several potentially useful blocks with varying kernel and tensor sizes,”
(P. 3, Sec. 2.2, ¶3) “Figure 4 demonstrates another case where the same choice from the search space is not always favorable. In Figure 4, on the top, 5x5 kernel size choice leads to 2.78x increase in the number of MACs and parameters compared to 3x3 kernel size which leads to 2.71x increase in the runtime (1122us vs. 414us). However, on the bottom we observe that the same increase in the kernel size, number of MACs and parameters lead to only a 35% increase in the runtime (27us vs 20us). For this case, it turns out that the combination of a shallow input tensor depth with a larger output tensor depth has a lower utilization where the increase in the kernel size has minor impact on the runtime due to improved utilization. This can be good trade-off to gain more trainable parameters to improve model quality at a marginal latency cost”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu / Lin with the search space disclosed by Gupta to create a search space comprised of convolution blocks with varying kernel sizes. By creating a search space comprised of convolution blocks with varying kernel sizes, machine learning engineers can design a model based on hardware constraints, thereby allowing engineers to balance the trade-off between hardware resource utilization and runtime.
The following are the references relied upon in the rejections below:
Das (US 20210350203 A1)
Claims 28 and 39-40 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang / Liu / Lin / Das.
Regarding Claims 28 and 39, the combined method of Zhang / Liu / Lin teaches the method of claim 19, however the combination does not teach wherein the different parameters include at least one of an output channel multiplier, stride, or expansion ratio, which is taught by Das:
wherein the different parameters include at least one of an output channel multiplier, stride, or expansion ratio (Das discloses “FIGS. 1A-1B illustrate a conceptual idea of searching for neural components at every layer (11A, 111B, 11C) of the DNN model (12). The neural components vary with “hyperparameters”, such as a number of filter (12A, 12F), a filter size (12B, 12C, 12G), a stride (12D, 12E), an expansion ratio and so on. Determining a correct balance of the hyperparameters is equal to determining a correct choice of a neural block in any layer (11A, 111B, 11C) of the DNN model (12). … The search space 10A includes of all possible choices of the neural blocks” [0052]. See Figure 1B depicting stride height and stride width are possible neural block choices.).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu / Lin with the search space disclosed by Das to create a search space comprised of neural blocks with varying strides and expansion ratios. By creating a search space comprised of neural blocks with varying strides and expansion ratios, the most optimal configuration of strides and expansion ratios can be chosen for a model, thereby increasing overall model performance.
Regarding Claim 40, the combined method of Zhang / Liu / Lin teaches the method of claim 19, however the combination does not teach wherein the different parameters include an expansion ratio, which is taught by Das:
wherein the different parameters include an expansion ratio (Das discloses “FIGS. 1A-1B illustrate a conceptual idea of searching for neural components at every layer (11A, 111B, 11C) of the DNN model (12). The neural components vary with “hyperparameters”, such as a number of filter (12A, 12F), a filter size (12B, 12C, 12G), a stride (12D, 12E), an expansion ratio and so on. Determining a correct balance of the hyperparameters is equal to determining a correct choice of a neural block in any layer (11A, 111B, 11C) of the DNN model (12). … The search space 10A includes of all possible choices of the neural blocks” [0052].).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the combined method of Zhang / Liu / Lin with the search space disclosed by Das to create a search space comprised of neural blocks with varying expansion ratios. By creating a search space comprised of neural blocks with varying expansion ratios, the optimal expansion ratio can be chosen based on hardware or performance constraints, thus allowing an optimal model to be developed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (US 20230267307 A1) teaches generating a machine-learned multitask model by generating candidate nodes (obtained from neural architecture search) for each task to be performed by the multitask model.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEDRO J MORALES whose telephone number is (571)272-6106. The examiner can normally be reached 8:30 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MIRANDA M HUANG can be reached at (571)270-7092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEDRO J MORALES/Examiner, Art Unit 2124
/MIRANDA M HUANG/Supervisory Patent Examiner, Art Unit 2124
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