DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-5, drawn to a subcombination of an integrated circuit, classified in G06F30/39.
II. Claims 6-14, drawn to a combination of a computing system for manufacturing a standard cell, performing a high level design step, and performing a layout design step, classified in G06F30/392.
III. Claims 15-20, drawn to a combination or a subcombination of a method of designing a layout for manufacturing a first standard cell, classified in G06F30/3953.
During a telephone conversation with Min Choi on 2/10/2026 a provisional election was made without traverse to prosecute the invention of group I, claims 1-5. This supersedes the Response to Restriction Requirement filed 1/7/2026. Affirmation of this election must be made by applicant in replying to this Office action. Claims 6-20 withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the standard cell" in each of lines 14 and 15 and twice in line 16. There is insufficient antecedent basis for these limitations in the claim, as the claim previously recites both “a first standard cell” and “a second standard cell,” and therefore it is not clear as to which is being referred to by the claim limitation.
Claim 2 recites the limitation " the standard cell " in line 9. There is insufficient antecedent basis for this limitation in the claim, as the claim previously recites “a third standard cell” and Claim 1 on which claim 2 depends recites both “a first standard cell” and “a second standard cell,” and therefore it is not clear as to which is being referred to by the claim limitation.
Claims 3-5 are rejected based on their dependency to Claim 1 for the reasons stated above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al., hereinafter Yang, US Publication No. 2019/0163863.
Regarding Claim 1, Yang teaches an integrated circuit, comprising:
a first standard cell including a first-a output pin and a second-a output pin (Yang Fig. 4 and paragraphs [0042] and [0045]-[0046], wherein a standard cell library includes a plurality of standard cells having output pin cells with different pin configurations, for example pin cell 404 comprising two output pins 4042 and 4044), a first routing wire configured to electrically connect the first-a output pin to the second-a output pin (Yang paragraphs [0045]-[0046], wherein the output pins are connected to each other by a metal line), a first-a via configured to electrically connect the first-a output pin to the first routing wire, and a second-a via configured to electrically connect the second-a output pin to the first routing wire (Yang paragraphs [0046] and [0069], wherein the output pins and the metal line are on different metal layers, with their connections to each other including vias to connect the different metal layers at their overlap), wherein each of the first-a output pin and the second-a output pin are configured to output a first signal (Yang paragraphs [0041] and [0045], wherein the output pins of a cell output a signal); and
a second standard cell including a first-b output pin and a second-b output pin (Yang Fig. 4 and paragraphs [0042] and [0045]-[0046], wherein a standard cell library includes a plurality of standard cells having output pin cells with different pin configurations, for example pin cell 406 comprising three output pins 4062, 4064 and 4066), a second routing wire configured to electrically connect the first-b output pin to the second-b output pin (Yang paragraphs [0045]-[0046], wherein the output pins are connected to each other by a metal line), a first-b via configured to electrically connect the first-b output pin to the second routing wire, and a second-b via configured to electrically connect the second-b output pin to the second routing wire (Yang paragraphs [0046] and [0069], wherein the output pins and the metal line are on different metal layers, with their connections to each other including vias to connect the different metal layers at their overlap), wherein each of the first-b output pin and the second-b output pin are configured to output a second signal (Yang paragraphs [0041] and [0045], wherein the output pins of a cell output a signal),
wherein the first-a via is placed at a first-a position in the standard cell, the second-a via is placed at a second-a position in the standard cell, the first-b via is placed at a first-b position in the standard cell, the second-b via is placed at a second-b position in the standard cell, and the first-a position, the second-a position, the first-b position, and the second-b position are different from one another (Yang Fig. 4, wherein the output pins of the pin cells 404 and 406 are in different locations, which indicates that wires connecting them and their vias are in different locations).
Regarding Claim 2, Yang further teaches a third standard cell including a first-c output pin and a second-c output pin (Yang Fig. 5 and paragraph [0050], wherein the standard cell library includes a plurality of standard cells having output pins with different configurations, for example pin cell 504 having output pins 5042 and 5044), a third routing wire configured to electrically connect the first-c output pin to the second-c output pin (Yang paragraphs [0045]-[0046] and [0050], wherein the output pins are connected to each other by a metal line), a first-c via configured to electrically connect the first-c output pin to the third routing wire, and a second-c via configured to electrically connect the second-c output pin to the third routing wire (Yang paragraphs [0046], [0050], and [0069], wherein the output pins and the metal line are on different metal layers, with their connections to each other including vias to connect the different metal layers at their overlap), wherein each of the first-c output pin and the second-c output pin are configured to output a third signal (Yang paragraphs [0041] and [0045], wherein the output pins of a cell output a signal),
wherein the first-c via is placed at a first-c position in the standard cell, the second-c via is placed at a second-c position in the standard cell, and the first-c position and the second-c position are different from each other (Yang Fig. 5, wherein the output pins of the standard cell 504 are in different locations, with the connections to the metal line, i.e. vias, therefore being in different locations).
Regarding Claim 3, Yang further teaches wherein the first-a position and the second-a position are determined based on electro-migration (EM) of first load cells to be connected to the first routing wire (Yang paragraph [0047], wherein the different pin cells are designed based on meeting EM requirements for load cells).
Regarding Claim 4, Yang further teaches wherein the first-b position and the second-b position is determined based on EM of second load cells to be connected to the second routing wire (Yang paragraph [0047], wherein the different pin cells are designed based on meeting EM requirements for load cells).
Regarding Claim 5, Yang further teaches wherein the first routing wire is placed by setting must-join pins of a placement and routing (P&R) tool to be the first-a output pin and the second-a output pin and the second routing wire is placed by setting must-join pins of the placement and routing tool to be the first-b output pin and the second-b output pin (Yang paragraph [0046], wherein the output pins of the pin cells 404 and 406 are must-joint pins).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC D LEE whose telephone number is (571)270-7098. The examiner can normally be reached Monday-Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC D LEE/Primary Examiner, Art Unit 2851