DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Response to Amendment
This office action is responsive to amendment filed on 04/13/2026. Claims 2-16 are pending.
Response to Arguments
In response to applicant’s assertion regarding non-statutory double patenting on page 6, “Applicant is filing a terminal disclaimer in compliance with 37 C.F.R. § 1.321(c) with this reply. Applicant notes, that as stated in the MPEP and judicial doctrine, the filing of a terminal disclaimer to obviate a rejection based on non-statutory double patenting is not an admission of the propriety of the rejection. Withdrawal of the obviousness-type double-patenting rejection is respectfully requested.”
Examiner respectfully disagrees because MPEP 804(I)(B)(1) recites “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers).” However, as of the date of this OA, no terminal disclaimer has been filed, but based on the amendment, most of the non-statutory double patenting rejections corresponding with Patent (10719575; 9880976; 11366877; 9898441) have been withdrawn because the amended claim recites additional limitations, such as identify, based on the request, a processor from among the plurality of processors included in the sparse element access unit and access multiple sparse elements based on the respective control signals and using the identified processor. However, there is an outstanding non-statutory double patenting rejection corresponding to patent US 10417303.
In response to applicant’s argument regarding 112(f) interpretation on page 6, “Applicant submits that the claims as amended do not invoke a § 112(f) interpretation. Specifically, the amended claims do not recite "a concatenation unit," or "the compress/decompress unit." Further, the specification, e.g., in relation to Figures 2A-2D provide sufficient structure for the "sparse-dense transform unit." Furthermore, the claims recite that the "plurality of sparse element access units are arranged in a network topology," providing sufficient structure.”
While examiner agrees that the amended claim 6 would avoid 112(f) interpretation. However, the limitation “each sparse element access unit” would still be invoked 112(f) interpretation because the generic placeholder unit is not modified by sufficient structure, material, or act for performing the claimed function. merely reciting the sparse element access units arranged in a network topology does not provide sufficient structure to perform the claimed functions, such as identify a processor and generate an output matrix.
In response to applicant’s argument regarding rejection under 35 U.S.C. 101 on page 7 that the amended claims integrate the abstract idea into a practical application.
Examiner agrees that the amended would integrate the judicial exception into a practical application by identifying a processor from among the plurality of processors to access multiple sparse elements of data based on control signal, which increases computation bandwidth of the CPU by fetching sparse data using the identified processor. Thus, having a plurality of sparse element access units to access portions of sparse data using the identified processor would increase computation bandwidth and decreases the processing cost of the system.
In response to applicant’s argument regarding rejection under 35 U.S.C. 103 on page 8-9, “In rejecting claim 1, the office action concedes that Strauss does not teach or suggest "data element access units," therefore Strauss cannot possibly teach or suggest the "sparse element access unit configured to identify, based on [a] request, a processor from among the plurality of processors" and "access using the identified processor, multiple sparse elements of a plurality of sparse elements corresponding to the sparse element access unit." Usui also does not teach or suggest this feature of claim 1. Usui has been relied on to allegedly teach or suggest "a plurality of CPUs [in Figure 2] having a plurality of cores perform in parallel [i.e., a plurality of data element access units]" (Office Action, page 20. To the extent that the Office Action is equating the CPUs 110 to the "sparse element access unit," the Usui does not discuss the CPUs 110 being configured to "identify a processor from among the plurality of processors included" in the CPUs 110, and "access using the identified processor, multiple sparse elements," as recited in claim 1. Usui does discuss the CPUs 110 including a number of cores 111-114, but Usui fails to teach or suggest that any of the cores are "identified" and "using the identified processor" to access "multiple sparse elements."
Examiner respectfully disagrees because it is not clear how applicant concludes that Strauss fails to teach data element access units would result in Strauss not be possible to teach or suggest the step of identify a processor from among the plurality of processors and access data using such processor. In fact, Strauss teaches such limitation as Strauss figure 1 teaches an on chip computing unit 112 that operates on sparse matrices [i.e., a sparse element access unit] includes a plurality of parallel processing units [i.e., a plurality of processors] and [0025-0026] describes that data elements from storage device 106 may be streamed in multiple data streams, such that each data stream may be sent to a different parallel processing unit of a plurality of parallel processing units. Thus, at least one parallel processing unit is identified based on a computation request, and the identified parallel processing unit would access the sparse elements to perform computation.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-3, 6-10, and 13-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 6-9, 13, 15-18, and 20 of U.S. Patent No. 10417303 in view of Usui - US 9418048.
Regarding claim 2, the reference US 10417303 teaches a system for transforming sparse elements into a dense matrix, the system comprising: a sparse-dense transform unit configured to output a target dense matrix, the sparse-dense transform unit comprising multiple sparse element access units comprising a plurality of processors, each sparse element access unit being configured to: receive a request for sparse elements; identify a processor from among a plurality of processors included in the sparse element access unit, the identified processor being configured to process the request for the sparse elements; fetch, using the identified processor, sparse elements for generating a dense matrix, wherein the fetched sparse elements are stored in one or more data shards of the system; and generate an output dense matrix using the fetched sparse elements, the output dense matrix being used by the sparse-dense transform unit to generate the target dense matrix output by the sparse-dense transform unit, but reference US 10417303 does not teach multiple sparse element access units arranged in a network topology, and each element access unit configured to receive respective control signals. However, Usui teaches multiple sparse element access units arranged in a network topology, and each element access unit configured to receive respective control signals (Usui teaches figure 2 illustrates a plurality of CPUs, each comprises 4 cores, wherein each CPU configured to receives respective control signals to perform operations, and the CPUs are connected to share memory 120, thus each CPU would be able to access data from memory based on the respective control signals. Thus, Usui teaches the multiple sparse element access units arranged in a network topology.)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the multiple sparse element access units of the reference patent US 10417303 to arrange in network and having each CPU to receive control signal to operate independently. This modification would have been obvious because both references disclose plurality of data accessing units to process data, and having a plurality of processors in each unit allows each unit to process data faster in parallel as they operate independently.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) :
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) , because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“each data element access unit” in claim 1. Figure 3A illustrates a data element access unit comprising a data fetch unit 304 having a plurality of processors 322a-322k to access data elements, wherein [0038] the processors may be implemented as vector processing units (VPUs), a concatenation unit 308 and a compress/decompress unit 310 to generate output matrix based on the accessed data elements. However, specification fails to provide sufficient structure for the concatenation unit and the compress/decompress unit because these units are illustrated as “black boxes” without sufficient structures to perform the claimed function. [0040-0041] merely describe what each unit does, but not what it is.
“a sparse-dense transform unit” in claim 3. Figure 1 illustrates a sparse dense transform unit 104 includes a plurality of element access units as illustrated in figure 2, wherein the data element access unit having a node network 320 [0036] configured to receive instructions corresponding to the respective control signals.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) , it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) , applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) .
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites “each data element access unit”, which invokes 112(f) interpretation. Figure 3A illustrates a data element access unit comprising a data fetch unit 304 having a plurality of processors 322a-322k to access data elements, wherein [0038] the processors may be implemented as vector processing units (VPUs), a concatenation unit 308 and a compress/decompress unit 310 to generate output matrix based on the accessed data elements. However, specification fails to provide sufficient structure, material, or acts for the concatenation unit and the compress/decompress unit because these units are illustrated as “black boxes” without sufficient structures to perform the claimed function. [0040-0041] merely describe what each unit does, but not what it is. In other words, the specification describes the plurality of processors 322a-322k implemented as vector processing units (VPUs) to perform the accessing limitation, but does not provide sufficient structure to perform the step of generating an output matrix since the unit 308 and 310 are illustrated as black boxes. Accordingly, the specification fails to provide sufficient structure for “each data element access unit” to perform the entire claimed function.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 line 8; claim 9 line 6; claim 16 line 6 recite "the request". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "a request".
Claim 2 recites “each data element access unit”, which invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function as explained in the 112(a) above. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-16 are rejected under 35 U.S.C. 103 as being unpatentable over Strauss – US 20150067009 in view of Usui – US 9418048. (IDS filed on 06/16/2022)
Regarding claim 2, Strauss teaches a system for transforming sparse elements into a matrix (Strauss [0016] figure 1 computing system 100 [i.e., a system] for performing sparse matrix multiplication. Thus, the system transforms sparse matrix input data [i.e., sparse elements] into a result matrix [i.e., a matrix]), the system comprising: a sparse element access unit comprising a corresponding plurality of processors (Strauss figure 1 illustrates on chip computing unit 112 [i.e., a sparse element access unit] comprising a plurality of parallel processing units 116 [i.e., a corresponding parallel of processors] that operate on sparse matrix), and the sparse element access unit being configured to: receive a control signal (Strauss [0021] the computing system 100 may include a specialized computation device 110 configured to perform specific computations in a very fast and efficient manner. The computation device 110 may be implemented in dedicated hardware as a logic circuit distinct from the processor 102, and linked to the processor 102 by the communications interface 108. For example, the processor 102 may execute an instruction that invokes the computation device 110 to perform computations specified by the instruction. Thus, the computing unit 112 receives control signal from processor to perform computation operation); identify, based on the request, a processor from among the plurality of processors included in the sparse element access unit (Strauss, figure 1 illustrates on chip computing unit 112 includes the plurality of parallel processing units [i.e., the plurality of processor], [0025-0026] describes sparse matrix vector multiplication computation, where each row of the sparse matrix is sent as a different data stream and each stream may be sent to a different parallel processing unit 116. Thus, based on a computation request [i.e., the request], a parallel processing unit [i.e., a processor] is identified from among the plurality of parallel processing units 116 to perform computation); access, based on the control signal and using the identified processor, multiple sparse elements of a plurality of sparse elements corresponding to the sparse element access unit (Strauss [0021, 0025-0026] the parallel processing unit 116 accesses the data stream as a row of the sparse matrix [i.e., multiple sparse elements of the plurality of sparse elements] to carry out computation); generate an output matrix based on the multiple sparse elements obtained from the plurality of sparse elements corresponding to the sparse element access unit; and output the output matrix to another component of the system (Strauss [0021] describes the computing unit 112 retrieve data element from storage device 106, process the computations, and return results of the computation to the off chip storage device 106. [0015-0028] describes matrix multiplication computation performed by the parallel processing units 116 to generate a result matrix [i.e., an output matrix] based on the sparse elements [i.e., the multiple sparse elements] obtained and output the result matrix to off chip storage device [i.e., another component of the system]).
Strauss does not teach a plurality of sparse element access units arranged in a network topology. However, Usui teaches a plurality of sparse element access units arranged in a network topology (Usui figure 2 illustrates a plurality of CPUs having a plurality of cores perform in parallel [i.e., a plurality of data element access units] that are connected to cache memory 115 and shared memory 120. Thus, such cores within the CPUs arranged in a network topology. Usui also describes computation of sparse matrix.)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the computing system of Strauss to include a plurality of on chip computing units as illustrated in figure 2 of Usio to further perform matrix multiplication in parallel to increase the computation speed. This modification would have been obvious because both references disclose concept of processing sparse matrix utilizing parallelism, wherein Strauss discloses an on chip processing unit having a plurality of parallel processing unit to perform matrix multiplication in parallel, thus modifying the system to have a plurality of on chip processing units would further increase the speed computation by allowing more data to be processed in parallel.
As modified, the combined system of Strauss in view of Usui teaches the system having a plurality of data element access units, each comprising a plurality of processors and configured to receive respective control signals, access multiple data elements and generate an output matrix based on multiple data elements (as modified, figure 1 of Strauss includes a plurality of computing units 112 to perform matrix multiplication, such as matrix-matrix multiplication, based on the matrix input to generate a matrix output)
Regarding claim 3, the combined system of Strauss in view of Usui teaches the system of claim 2, further comprising: a sparse-dense transform unit configured to receive instructions corresponding to the respective control signals; and wherein the plurality of sparse element access units are located in the sparse-dense transform unit (as modified, Strauss the plurality of computing units 112 [i.e., the plurality of data element access units] are located in the computing device 110, wherein computing device 110 [i.e., a sparse-dense transform unit] [0022] performs a computation on sparse matrix may be stored in a dense format, which configured receive instructions [i.e., instructions corresponding to the respective control signals] from processor 102 by the communication interface 108 [0026] that includes an on chip communication interface to enable communication between separate units).
Regarding claim 4, the combined system of Strauss in view of Usui teaches the system of claim 3, wherein the sparse-dense transform unit is a multi-dimensional sparse-dense transform unit comprising a row dimension and a column dimension (as modified, computing device 110 includes the plurality of computing units 112, such as a 2x2 units as illustrated in Usui figure 2. Thus, the computing device 110 is a multi-dimensional unit comprising a row and column dimensions).
Regarding claim 5, the combined system of Strauss in view of Usui teaches the system of claim 4, wherein the plurality of sparse element access units are arranged along respective dimensions of the multi-dimensional sparse-dense transform unit (as modified, the plurality of computing units 112 are arranged along the dimensions of the computing device 110, such as 2x2 array core in Usui figure 2).
Regarding claim 6, the combined system of Strauss in view of Usui teaches the system of claim 3, wherein each sparse element access unit includes one or more programmable computers configured to apply a transformation to the multiple sparse elements to generate the output matrix (as modified, Strauss, figure 1 illustrates a computing unit 112 [i.e., each data element access unit] includes a plurality of parallel processing units to perform matrix multiplication on multiple data element retrieved to generate the output matrix [i.e., one or more programmable computers to apply a transformation to generate the output matrix]).
Regarding claim 7, the combined system of Strauss in view of Usui teaches the system of claim 6, wherein: the transformation is based on a concatenation operation (Strauss [0026] describes that each row of the sparse matrix may be sent to a parallel processing unit 116 to perform partial computation. Thus, in order to generate a result matrix, the plurality of results generated by the plurality of parallel processing unit 116 are concatenated to form a final result. Accordingly, the transformation is based on a concatenation operation of the plurality of processing units, which corresponds to a concatenation unit).
Regarding claim 8, the combined system of Strauss in view of Usui teaches the system of claim 6, wherein: the transformation is based on an operation to compress the multiple sparse elements (Strauss figure 1 illustrates computing unit 112 includes a plurality of parallel processing units 116 to perform matrix matrix multiplication [0015]. Thus, data elements of two matrices are compressed to generate a result matrix. Accordingly, the parallel processing unit is a compress unit and the multiplication [i.e., transformation] is based on an operation to compress the multiple data elements).
Claims 9-15 recite method claims that would be practiced by the apparatus claims 2-8. Thus, they are rejected for the same reasons.
Claim 16 recites a product claims having limitations that are similar to the method claims. Thus, it is rejected for the same reasons. Furthermore, the claim recites a non-transitory machine-readable storage device comprising instructions that, when executed by a data processing apparatus, cause the data processing apparatus to perform operations (Strauss figure 1 illustrates [0019] a mass storage device 104 [i.e., a non-transitory machine readable storage device] comprises instructions executed by processor 102 and computation device 110 [i.e., a data processing apparatus]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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