DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112 below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 10/719,575. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are merely a broaden version of the patent claims. To demonstrate, Claim 2 of the examined application is compared with claim 1 of the reference patent in the following table:
Instant application 17/842,420
Reference Patent 10/719,575
2. A system for transforming data elements into a matrix, the system comprising:
1. A system for transforming sparse elements into a dense matrix, the system comprising:
a plurality of data element access units, each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors, and each data element access unit being configured to:
multiple sparse element access units … a sparse element access unit includes: a respective data fetch unit comprising a respective plurality of processors
receive respective control signals; access, based on the respective control signals, multiple data elements of a plurality of data elements corresponding to the data element access unit; generate an output matrix based on the multiple data element obtained from the plurality of data elements corresponding to the data element access unit; and output the output matrix to another component of the system.
…receive, from an external source, one or more control signals …fetch, based on the indication, one or more sparse elements of the subset of the particular sparse elements; …generate an output dense matrix based on a transformation that is applied to at least the one or more sparse elements…compress the output dense matrix to generate a compressed output dense matrix; and
provide the compressed output dense matrix to a node network.
Claims 2-3, 6-10, and 13-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 6-9, 13, 15-18, and 20 of U.S. Patent No. 10417303. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are merely a broaden version of the patent claims.
Claims 2-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 9880976. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are merely a broaden version of the patent claims.
Claims 2-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 11366877 in view of Usui - US 9418048. To demonstrate, Claim 2 of the examined application is compared with claim 1 of the reference patent in the following table:
Instant application 17842420
Reference Patent US 11366877
2. A system for transforming data elements into a matrix, the system comprising:
1. A system for transforming sparse elements into a dense matrix, the system comprising:
a plurality of data element access units, each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors, and each data element access unit being configured to:
a plurality of sparse element access units, each sparse element access unit of the plurality of sparse element access units being configured to:
receive respective control signals; access, based on the respective control signals, multiple data elements of a plurality of data elements corresponding to the data element access unit; generate an output matrix based on the multiple data element obtained from the plurality of data elements corresponding to the data element access unit; and output the output matrix to another component of the system.
receive respective control signals; access, based on the respective control signals, sparse elements stored in a data shard corresponding to the sparse element access unit; generate an output dense matrix based on a transformation applied to the sparse elements obtained from the data shard; and provide the output dense matrix to a node network of the system.
Regarding claim 2, reference patent US 11366877 teaches a plurality of sparse element access units, but does not teach each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors. However, Usui teaches a plurality of data element access units, wherein each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors (Usui figure 2 illustrates a plurality of CPUs, each comprises 4 processors [i.e., each data element access unit comprising a corresponding plurality of processors] as illustrated in figure 2).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify each sparse element access unit of the reference patent US 11366877 to include a plurality of processors as illustrated in figure 2 of Usui. This modification would have been obvious because both references disclose plurality of data accessing units to process data, and having a plurality of processors in each unit allows each unit to process data faster in parallel.
Claims 2-3, 6-10, and 13-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 5-7, 9-10, 12, 15-17 of U.S. Patent No. 9898441 in view of Usui. The analysis for claim 2 is demonstrated below.
Regarding claim 2, reference patent US 9898441 teaches a system for transforming data elements into a matrix, the system comprising: a data element access unit configured to receive respective control signals; access, based on the respective control signals, multiple data elements of a plurality of data elements corresponding to the data element access unit; generate an output matrix based on the multiple data element obtained from the plurality of data elements corresponding to the data element access unit; and output the output matrix to another component of the system (see claim 1 of US 9898441), but does not teach a plurality of data element access units, each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors. However, Usui teaches a plurality of data element access units, each data element access unit of the plurality of data element access units comprising a corresponding plurality of processors (Usui figure 2 illustrates a plurality of CPUs, each comprises 4 processors [i.e., each data element access unit comprising a corresponding plurality of processors] as illustrated in figure 2).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the system of the reference patent US 11366877 to include a plurality of data element access units, each comprises a plurality of processors as illustrated in figure 2 of Usui. This modification would have been obvious because both references disclose data accessing unit to process data. Furthermore, having a plurality of data element access units, each includes a plurality of processors allows the system to process data in parallel.
Claim Objections
Claims 2-8 are objected to because of the following informalities:
Claim 2 line 8 “the multiple data element” should be “the multiple data elements” as antecedently recited.
Dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) :
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) . The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) , is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) , except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) , because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“each data element access unit” in claim 1. Figure 3A illustrates a data element access unit comprising a data fetch unit 304 having a plurality of processors 322a-322k to access data elements, wherein [0038] the processors may be implemented as vector processing units (VPUs), a concatenation unit 308 and a compress/decompress unit 310 to generate output matrix based on the accessed data elements. However, specification fails to provide sufficient structure for the concatenation unit and the compress/decompress unit because these units are illustrated as “black boxes” without sufficient structures to perform the claimed function. [0040-0041] merely describe what each unit does, but not what it is.
“a sparse-dense transform unit” in claims 3. Figure 1 illustrates a sparse dense transform unit 104 includes a plurality of element access units as illustrated in figure 2, wherein the data element access unit having a node network 320 [0036] configured to receive instructions corresponding to the respective control signals.
“a respective first unit” in claim 6. Figure 3A illustrates concatenation unit and compress/decompress unit to apply a transformation to the multiple data elements to generate output matrix. However, the concatenation unit and compress/decompress unit are illustrated as black boxes without sufficient structure to perform the claimed function.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) , it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) , applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) .
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 2-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 2 and 6 recites “each data element access unit” and “a respective first unit” which invoke 112(f) interpretation. Figure 3A illustrates a data element access unit comprising a data fetch unit 304 having a plurality of processors 322a-322k to access data elements, wherein [0038] the processors may be implemented as vector processing units (VPUs), a concatenation unit 308 and a compress/decompress unit 310 to generate output matrix based on the accessed data elements. However, specification fails to provide sufficient structure, material, or acts for the concatenation unit and the compress/decompress unit because these units are illustrated as “black boxes” without sufficient structures to perform the claimed function. [0040-0041] merely describe what each unit does, but not what it is. In other words, the specification describes the plurality of processors 322a-322k implemented as vector processing units (VPUs) to perform the accessing limitation, but does not provide sufficient structure to perform the step of generating an output matrix since the unit 308 and 310 are illustrated as black boxes. Accordingly, the specification fails to provide sufficient structure for “each data element access unit” and “a respective first unit” to perform the entire claimed function.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 6 recite “each data element access unit” and “a respective first unit”” invokes 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Figure 3A illustrates a data element access unit comprising a data fetch unit 304 having a plurality of processors 322a-322k to access data elements, wherein [0038] the processors may be implemented as vector processing units (VPUs), a concatenation unit 308 and a compress/decompress unit 310 to generate output matrix based on the accessed data elements. However, specification fails to provide sufficient structure, material, or acts for the concatenation unit and the compress/decompress unit because these units are illustrated as “black boxes” without sufficient structures to perform the claimed function. [0040-0041] merely describe what each unit does, but not what it is. In other words, the specification describes the plurality of processors 322a-322k implemented as vector processing units (VPUs) to perform the accessing limitation, but does not provide sufficient structure to perform the step of generating an output matrix since the unit 308 and 310 are illustrated as black boxes. Accordingly, the specification fails to provide sufficient structure for “each data element access unit” and “a respective first unit” to perform the entire claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 2-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 2 recites an apparatus
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites step of transforming data elements into a matrix and generate an output matrix based on multiple data element obtained from the plurality of data elements. Such limitations cover mathematical calculations, relationship, and/or formula (see at least [0039] describes step of reducing data dimensionality, [0040] describes rearrange data elements and concatenate data, [0041] describes compressing step to remove zero values. Thus, [0039-0041] describes the step of transforming data into a matrix by performing dimensional data, rearrange data, and removing zero values from the data set, which are mathematical operations to pre-process data. Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a system comprising a plurality of data element access units, each data element access unit comprising a plurality of processors. However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data. The claim further recites step of receiving control signals, access, based on the control signals, multiple data elements corresponding to the data element access unit, and output the output matrix to another component of the system. Such limitations of receiving control signals, accessing data and outputting the output matrix to another component are at most considered as insignificant extra/post solution activities because such limitations are mere data gathering and well known activities. Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using computer components. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on computer elements cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of receiving control signals, accessing data and outputting the output matrix to another component considered to be insignificant extra/post solution activity in step 2A, and are determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network and (iv) Storing and retrieving information in memory, are well-understood, routing, conventional function when they are claimed in a merely generic manner. Also see Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest Ebook Central, page 532 figure 6.2 illustrates a multi-processors architecture having a plurality of data accessing units each comprises a plurality of processors, and configured to receives control signal via interconnection network to perform operation. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 3-5 further comprising: a sparse-dense transform unit configured to receive instructions corresponding to the respective control signals; and wherein the plurality of data element access units are located in the sparse-dense transform unit; wherein the sparse-dense transform unit is a multi-dimensional sparse-dense transform unit comprising a row dimension and a column dimension; wherein the plurality of data element access units are arranged along respective dimensions of the multi-dimensional sparse-dense transform unit. Such additional elements are recited at a high level of generality, e.g., having computer components performing computer functions of processing data, and the concept of having multiple accessing units located in a multi-dimensional unit comprising a row and column dimensions, where the plurality of units are arranged along the respective dimensions are considered as insignificant extra solution activity under step 2A prong two and determined to be well-understood, routine and conventional under step 2B. see at least Hennessy, John L., et al. Computer Architecture : A Quantitative Approach, Elsevier Science & Technology, 2014. ProQuest Ebook Central, page 532 figure 6.2 illustrates a multi-processors architecture having a plurality of processors configured to receive instructions, wherein the processors are located in a multi-processor unit having a row and a column dimension, wherein the processors are arranged along respective dimensions. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites wherein each data element access unit includes a respective first unit configured to apply a transformation to the multiple data elements to generate the output matrix. The step of applying a transformation to the multiple data elements to generate the output matrix covers mathematical calculations, relationship, and/or formula (e.g., mathematical concepts, see at least [0039-0041] describes the transformation includes reducing dimensionality, rearrange data, and compressing by removing zeros values of the data set). The additional element of a respective first unit is recited at a high level of generality, e.g., computer component performing computer function. Thus, such limitation amount to no more than mere instructions to apply the exception using computer component. Therefore, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claim 7 further recites each first unit is a concatenation unit; and the transformation is based on a concatenation operation. As explained above, the step of transformation is based on concatenation operation covers mathematical calculations, relationship, and/or formula (see at least [0039-0041] describes the step of concatenating and rearrange data). The concatenation unit is recited at a high level generality, e.g., computer component performing computer function. Thus, such limitation amount to no more than mere instructions to apply the exception using computer component. Therefore, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claim 8 further recites the system of claim 6, wherein: each first unit is a compress/decompress unit; and the transformation is based on an operation to compress the multiple data elements. As explained above, the step of transformation is based on an operation to compress the multiple data elements covers mathematical calculations, relationship, and/or formula (see at least [0039-0041] describes the step of compressing data by removing zero value from the data set). The compress/decompress unit is recited at a high level generality, e.g., computer component performing computer function. Thus, such limitation amount to no more than mere instructions to apply the exception using computer component. Therefore, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claims 9-15 recite method claims having similar limitations as apparatus claims 2-8. Thus, they are rejected for the same reasons.
Claim 16 recites a product claim having similar limitations as apparatus claim 2. Thus, it is rejected for the same reasons. claim 16 further recites a non-transitory machine-readable storage device comprising instructions that, when executed by a data processing apparatus, cause the data processing apparatus to perform operations. Such additional elements are recited at a high level of generality, e.g., generic computer components performing generic functions of storing and executing instructions to perform operation. Thus, such limitation amount to no more than mere instructions to apply the exception using computer components. Therefore, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-16 are rejected under 35 U.S.C. 103 as being unpatentable over Strauss – US 20150067009 in view of Usui. (IDS filed on 06/16/2022)
Regarding claim 2, Strauss teaches a system for transforming data elements into a matrix (Strauss figure 1 computing system 100 [i.e., a system] for performing matrix multiplication. Thus, the system transforms matrix input data [i.e., data elements] into a result matrix [i.e., a matrix]), the system comprising: a data element access unit comprising a corresponding plurality of processors (Strauss figure 1 illustrates on chip computing unit 112 [i.e., a data element access unit] comprising a plurality of parallel processing units 116 [i.e., a corresponding parallel of processors]), and the data element access unit being configured to: receive a control signal (Strauss [0021] the computing system 100 may include a specialized computation device 110 configured to perform specific computations in a very fast and efficient manner. The computation device 110 may be implemented in dedicated hardware as a logic circuit distinct from the processor 102, and linked to the processor 102 by the communications interface 108. For example, the processor 102 may execute an instruction that invokes the computation device 110 to perform computations specified by the instruction. Thus, the computing unit 112 receives control signal from processor to perform computation operation); access, based on the control signal, multiple data elements of a plurality of data elements corresponding to the data element access unit (Strauss [0021] the computation device 110 may be configured to retrieve data elements [i.e., multiple data elements of a plurality of data elements] from the off-chip storage device 106 to carry out the computations); generate an output matrix based on the multiple data element obtained from the plurality of data elements corresponding to the data element access unit; and output the output matrix to another component of the system (Strauss [0021] describes the computing unit 112 retrieve data element from storage device 106, process the computations, and return results of the computation to the off chip storage device 106. [0015-0028] describes matrix multiplication computation performed by the parallel processing units 116 to generate a result matrix [i.e., an output matrix] based on the data elements [i.e., the multiple data elements] obtained and output the result matrix to off chip storage device [i.e., another component of the system]).
Strauss does not teach a plurality of data element access units. However, Bell teaches a plurality of data element access units (Usui figure 2 illustrates a plurality of CPUs having a plurality of cores perform in parallel [i.e., a plurality of data element access units)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the computing system of Strauss to include a plurality of on chip computing units as illustrated in figure 2 of Usio to further perform matrix multiplication in parallel to increase the computation speed. This modification would have been obvious because both references disclose concept of processing sparse matrix utilizing parallelism, wherein Strauss discloses an on chip processing unit having a plurality of parallel processing unit to perform matrix multiplication in parallel, thus modifying the system to have a plurality of on chip processing units would further increase the speed computation by allowing more data to be processed in parallel.
As modified, the combined system of Strauss in view of Usui teaches the system having a plurality of data element access units, each comprising a plurality of processors and configured to receive respective control signals, access multiple data elements and generate an output matrix based on multiple data elements (as modified, figure 1 of Strauss includes a plurality of computing units 112 to perform matrix multiplication, such as matrix-matrix multiplication, based on the matrix input to generate a matrix output)
Regarding claim 3, the combined system of Strauss in view of Usui teaches the system of claim 2, further comprising: a sparse-dense transform unit configured to receive instructions corresponding to the respective control signals; and wherein the plurality of data element access units are located in the sparse-dense transform unit (as modified, Strauss the plurality of computing units 112 [i.e., the plurality of data element access units] are located in the computing device 110, wherein computing device 110 [i.e., a sparse-dense transform unit] [0022] performs a computation on sparse matrix may be stored in a dense format, which configured receive instructions [i.e., instructions corresponding to the respective control signals] from processor 102 by the communication interface 108 [0026] that includes an on chip communication interface to enable communication between separate units).
Regarding claim 4, the combined system of Strauss in view of Usui teaches the system of claim 3, wherein the sparse-dense transform unit is a multi-dimensional sparse-dense transform unit comprising a row dimension and a column dimension (as modified, computing device 110 includes the plurality of computing units 112, such as a 2x2 units as illustrated in Usui figure 2. Thus, the computing device 110 is a multi-dimensional unit comprising a row and column dimensions).
Regarding claim 5, the combined system of Strauss in view of Usui teaches the system of claim 4, wherein the plurality of data element access units are arranged along respective dimensions of the multi-dimensional sparse-dense transform unit (as modified, the plurality of computing units 112 are arranged along the dimensions of the computing device 110, such as 2x2 array core in Usui figure 2).
Regarding claim 6, the combined system of Strauss in view of Usui teaches the system of claim 3, wherein each data element access unit includes a respective first unit configured to apply a transformation to the multiple data elements to generate the output matrix (as modified, Strauss, figure 1 illustrates a computing unit 112 [i.e., each data element access unit] includes a plurality of parallel processing units to perform matrix multiplication on multiple data element retrieved to generate the output matrix [i.e., a first unit to apply a transformation to generate the output matrix]).
Regarding claim 7, the combined system of Strauss in view of Usui teaches the system of claim 6, wherein: each first unit is a concatenation unit; and the transformation is based on a concatenation operation (Strauss [0026] describes that each row of the sparse matrix may be sent to a parallel processing unit 116 to perform partial computation. Thus, in order to generate a result matrix, the plurality of results generated by the plurality of parallel processing unit 116 are concatenated to form a final result. Accordingly, the transformation is based on a concatenation operation of the plurality of processing units, which corresponds to a concatenation unit).
Regarding claim 8, the combined system of Strauss in view of Usui teaches the system of claim 6, wherein: each first unit is a compress/decompress unit; and the transformation is based on an operation to compress the multiple data elements (Strauss figure 1 illustrates computing unit 112 includes a plurality of parallel processing units 116 to perform matrix matrix multiplication [0015]. Thus, data elements of two matrices are compressed to generate a result matrix. Accordingly, the parallel processing unit is a compress unit and the multiplication [i.e., transformation] is based on an operation to compress the multiple data elements).
Claims 9-15 recite method claims that would be practiced by the apparatus claims 2-8. Thus, they are rejected for the same reasons.
Claim 16 recites a product claims having limitations that are similar to the method claims. Thus, it is rejected for the same reasons. Furthermore, the claim recites a non-transitory machine-readable storage device comprising instructions that, when executed by a data processing apparatus, cause the data processing apparatus to perform operations (Strauss figure 1 illustrates [0019] a mass storage device 104 [i.e., a non-transitory machine readable storage device] comprises instructions executed by processor 102 and computation device 110 [i.e., a data processing apparatus]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Blomgren – US 20020198911 discloses a matrix processor 16 comprises 16 identical processing elements arranged in a 4x4 array or matrix to efficiently perform matrix computations on 4x4 sub-matrices
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182