DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claims 1 and 16 under 35 USC 112(a) and 35 USC 112(b), Applicant’s arguments filed 11/25/2025 have been fully considered and they are persuasive. Examiner withdraws said rejections.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7, 8, 12-16, 21, 25-44, 45-48 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2014/0254232 A1) in view of Yu (US 2018/0151501 A1) and Muir (US 2016/0149580 A).
Regarding claim 1, Wu teaches a multi-chip package comprising:
a non-volatile memory (NVM) integrated-circuit (IC) chip (Fig. 16, 1608) wherein the non-volatile memory (NVM) integrated-circuit (IC) chip comprises a first memory cell for storing therein a first datum for configuration (Fig. 16, Configuration Bitstream to 1608, [0048]); and
a semiconductor integrated-circuit (IC) chip (Fig. 16, 1610, [0048] 1610, such as the integrated circuit described below in Fig. 17) wherein the semiconductor integrated-circuit (IC) chip comprises a plurality of static-random-access-memory (SRAM) cells ([0054] SRAM blocks) for storing therein third data for a look-up table (LUT) ([0057] LUTs), wherein a third datum of the third data stored in the plurality of static-random-access-memory (SRAM) cells is associated with the first datum and a selection circuit comprising a first set of input points for a selecting data set and a second set of input points for an input data set having a datum associated with the third datum wherein the selection circuit is configured to select, in accordance with the selecting data set an input datum from the input data set as an output datum at an output point of the selection circuit (Fig. 18, [0057] AMUX-DMUX, data input terminals, the select inputs are controlled by configuration memory cells).
However, Wu does not explicitly teach the package comprising:
an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers; and
the non-volatile memory (NVM) integrated-circuit (IC) chip and the semiconductor integrated-circuit (IC) chip located over and coupling to the interconnection scheme; and
wherein the second datum stored in the second memory cell of the non-volatile memory (NVM) integrated-circuit (IC) chip is associated with a forth datum related to computation of the semiconductor integrated-circuit (IC) chip.
Yu teaches a multi-chip package comprising:
an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers (Fig. 11, 105, 106, [0037]); and
a non-volatile memory (NVM) integrated-circuit (IC) chip ([0030] flash memories) and the semiconductor integrated-circuit (IC) chip ([0030] ASIC or the like) located over and coupling to the interconnection scheme (Fig. 11, 103 over 105).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the multi-chip package construction of Yu to the teachings of Wu in order for high yield and low manufacturing cost (Yu, [0003]).
However, Wu in view of Yu does not teach a multi-chip package wherein the second datum stored in the second memory cell of the non-volatile memory (NVM) integrated-circuit (IC) chip is associated with a forth datum related to computation of the semiconductor integrated-circuit (IC) chip.
Muir teaches a multi-chip package wherein a datum stored in a memory cell of a non-volatile memory (NVM) integrated-circuit (IC) chip is associated with a datum related to computation of a semiconductor integrated-circuit (IC) chip (Fig. 2, [0030] Once initialized, the APS 110 communicates with a non-volatile memory 133 and a system or volatile memory 131, as well as the various specialized processors and controllers within the SoC 120 or coupled to the SoC 120. The non-volatile memory 133 is available for storing and retrieving system configuration information, application programs as well as storing files and any other information that can be controllably retrieved and or executed by the APS 110 or other subsystems in the PCD 100e.).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Muir to the teachings of Wu in view of Yu in order to improve mechanisms for managing pipelines in reconfigurable processors (Muir [0007], [0039])
Regarding claim 7, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the non-volatile memory (NVM) integrated-circuit (IC) chip is a flash chip ([0040] flash memory).
Regarding claim 8, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip ([0060] FPGA chip 1910).
Regarding claim 12, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Yu further teaches the package, further comprising a central-processing-unit (CPU) chip over and coupling to the component, wherein the central-processing-unit (CPU) chip couples to the semiconductor integrated-circuit (IC) chip through the interconnection scheme ([0025]).
Regarding claim 13, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, further comprising a graphic-processing-unit (GPU) chip over and coupling to the interconnection scheme, wherein the graphic-processing-unit (GPU) chip couples to the semiconductor integrated-circuit (IC) chip through the interconnection scheme ([0050] DSP, dedicated processor block).
Regarding claim 14, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, further comprising an input/output (I/O) chip over and coupling to the interconnection scheme, wherein the input/output (I/O) chip couples to the semiconductor integrated-circuit (IC) chip through the interconnection scheme ([0050] I/O block).
Regarding claim 15, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, further comprising a dynamic-random-access-memory (DRAM) chip over and coupling to the interconnection scheme, wherein the dynamic-random-access-memory (DRAM) chip couples to the semiconductor integrated-circuit (IC) chip through the interconnection scheme (Fig. 19, 1912).
Regarding claim 16, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 16 is rejected under the same rationale as claim 1 above.
Regarding claim 21, all the limitations of claim 16 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the semiconductor integrated-circuit (IC) chip is a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip ([0060] FPGA chip 1910).
Regarding claim 25, this claim has substantially the same subject matter as that in claim 12. Therefore, claim 25 is rejected under the same rationale as claim 12 above.
Regarding claim 26, this claim has substantially the same subject matter as that in claim 14. Therefore, claim 26 is rejected under the same rationale as claim 14 above.
Regarding claim 27, all the limitations of claim 16 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the second set of input points of the selection circuit have an input point coupling to an output point of the static-random-access-memory (SRAM) cell (Fig. 18, 1811, 1812).
Regarding claim 28, all the limitations of claim 16 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the selection circuit comprises a multiplexer (Fig. 18, 1811, 1812).
Regarding claim 29, all the limitations of claim 16 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the semiconductor integrated- circuit (IC) chip further comprises a plurality of first interconnects each coupling to one of the first set of input points of the selection circuit and a second interconnect coupling to the output point of the selection circuit (Fig. 18, 1811, 1812).
Regarding claim 30, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein each of the second set of input points of the selection circuit couples to an output point of one of the plurality of static-random- access-memory (SRAM) cells (Fig. 18, 1811, 1812 coupled to 1801A-D).
Regarding claim 31, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, wherein the selection circuit comprises a multiplexer (Fig. 18, 1811, 1812).
Regarding claim 32, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Muir further teaches the package, wherein the second datum is associated with a computed datum output from the computation of the semiconductor integrated-circuit (IC) chip ([0030]).
Regarding claim 33, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu further teaches the package, further comprising a dynamic-random-access-memory (DRAM) integrated-circuit (IC) chip comprising a third memory cell for storing therein a fifth datum associated with the fourth datum related to the computation of the semiconductor integrated-circuit (IC) chip ([0030]).
Regarding claim 34, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Muir further teaches the package, wherein the fifth datum is associated with the second datum stored in the second memory cell of the non-volatile memory (NVM) integrated-circuit (IC) chip ([0030]).
Regarding claim 35, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Yu further teaches the package, further comprising an underfill having a first portion between the semiconductor integrated-circuit (IC) chip and interconnection scheme ([0035]).
Regarding claim 36, all the limitations of claim 35 are taught by Wu in view of Yu and Muir.
Yu further teaches the package, wherein the underfill has a second portion between the non-volatile memory (NVM) integrated-circuit (IC) chip and interconnection scheme, wherein the semiconductor integrated-circuit (IC) chip and non-volatile memory (NVM) integrated-circuit (IC) chip are arranged at a same horizontal level ([0035], Fig. 11).
Regarding claim 37, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Yu further teaches the package further comprising a polymer layer over the interconnection scheme and at a same horizontal level as the semiconductor integrated-circuit (IC) chip, wherein the polymer layer comprises resin ([0028], Fig. 11).
Regarding claim 38, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Yu further teaches the package further comprising a polymer layer over the interconnection scheme and at a same horizontal level as the semiconductor integrated-circuit (IC) chip and a through polymer via (TPV) vertically in the polymer layer, at the same horizontal level as the semiconductor integrated-circuit (IC) chip and polymer layer and coupling to the interconnection scheme, wherein the polymer layer comprises resin ([0041]).
Regarding claim 39, all the limitations of claim 38 are taught by Wu in view of Yu and Muir.
Yu further teaches the package herein the through polymer via (TPV) comprises a copper layer ([0041]).
Regarding claim 40, this claim has substantially the same subject matter as that in claim 13. Therefore, claim 40 is rejected under the same rationale as claim 13 above.
Regarding claim 41, this claim has substantially the same subject matter as that in claim 15. Therefore, claim 41 is rejected under the same rationale as claim 15 above.
Regarding claim 42, this claim has substantially the same subject matter as that in claim 33. Therefore, claim 42 is rejected under the same rationale as claim 33 above.
Regarding claim 43, this claim has substantially the same subject matter as that in claim 34. Therefore, claim 43 is rejected under the same rationale as claim 34 above.
Regarding claim 44, this claim has substantially the same subject matter as that in claim 32. Therefore, claim 44 is rejected under the same rationale as claim 32 above.
Regarding claim 45, this claim has substantially the same subject matter as that in claim 35. Therefore, claim 45 is rejected under the same rationale as claim 35 above.
Regarding claim 46, this claim has substantially the same subject matter as that in claim 37. Therefore, claim 46 is rejected under the same rationale as claim 37 above.
Regarding claim 47, this claim has substantially the same subject matter as that in claim 38. Therefore, claim 47 is rejected under the same rationale as claim 38 above.
Regarding claim 48, this claim has substantially the same subject matter as that in claim 39. Therefore, claim 48 is rejected under the same rationale as claim 39 above.
Claims 4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2014/0254232 A1) in view of Yu (US 2018/0151501 A1) and Muir (US 2016/0149580 A) as applied to claim 1 above, and further in view of Lin (US 2012/0193785 A1).
Regarding claim 4, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu in view of Yu does not explicitly teach the package comprising a plurality of tin-containing bumps under the interconnection scheme and at a bottom of the multi-chip package.
Lin teaches a package comprising a plurality of tin-containing bumps under a component and at a bottom of the multi-chip package ([0063] solder bump may include one or more of tin-silver).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Lin to the teachings of Wu in view of Yu and Muir since the tin-containing bumps are well-known in the art as Lin disclosed is a part of suitable process (Lin, [0063]) and one skilled in the art could have combined the bumps as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 18, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 18 is rejected under the same rationale as claim 4 above.
Claims 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2014/0254232 A1) in view of Yu (US 2018/0151501 A1) and Muir (US 2016/0149580 A) as applied to claim 1 above, and further in view of Lesea (US 10,038,647 B1).
Regarding claim 5, all the limitations of claim 1 are taught by Wu in view of Yu and Muir.
Wu in view of Yu does not explicitly teach the package wherein the semiconductor integrated-circuit (IC) chip further comprises a metal bump at the bottom of the semiconductor integrated-circuit (IC) chip and bonded to the interconnection scheme.
Lesea teaches a package further comprising a metal bump under a semiconductor integrated-circuit (IC) chip and bonded to an interconnection scheme (Fig. 3, 310, col. 4, lines 30~32).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Lesea to the teachings of Wu in view of Yu and Muir since the solder balls are well-known form of making electrical connections in the art as Lesea disclosed is a part of suitable process (Lesea, col. 4, lines 30~32, bumps or other connective elements) and one skilled in the art could have combined the bumps as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 19, this claim has substantially the same subject matter as that in claim 5. Therefore, claim 19 is rejected under the same rationale as claim 5 above.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2014/0254232 A1) in view of Yu (US 2018/0151501 A1), Muir (US 2016/0149580 A) and Lesea (US 10,038,647 B1) as applied to claim 5 above and further in view of Lin (US 2012/0193785 A1).
Regarding claim 6, all the limitations of claim 5 are taught by Wu in view of Yu, Muir and Lesea.
Wu in view of Yu, Muir and Lesea does not explicitly teach the package wherein the metal bump comprises tin.
Lin teaches a package wherein a metal bump comprises tin ([0063] solder bump may include one or more of tin-silver).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the teachings of Lin to the teachings of Wu in view of Yu, Muir and Lesea since the tin-containing bumps are well-known in the art as Lin disclosed is a part of suitable process (Lin, [0063]) and one skilled in the art could have combined the bumps as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 6. Therefore, claim 20 is rejected under the same rationale as claim 6 above.
Conclusion
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844