DETAILED ACTION
Status of Application
Claims 1-9, 11-18, and 20-28 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 26 have been considered but are moot because of the new ground of rejection. Any arguments presented by the applicant which are still relevant to any references being applied are addressed below.
Applicant's arguments filed 01/21/2026 have been fully considered but they are not persuasive. The reasons set forth below.
Applicant argues: (1) Chambers does not disclose a descriptor that describes the data reformat operation to perform [remarks, p. 10].
The examiner respectfully disagrees with this argument.
The examiner notes that Chambers states in col. 6, lines 35-41, “The ENDIAN_ ALIGN[1:0] field 368 of the present invention consists of two bits that are used to define the endian domain format of the input and the output data packets and define whether or not endian domain conversion is required by circuits 200 and 200a and also the required conversion manner. Specifically, bit 0 defines the input data packet endian orientation, where a data value of 0 represents little endian format and a data value of 1 represents big endian format. Bit 1 defines the output data packet endian orientation where a data value of 0 represents little endian format and a data value of 1 represents big endian format”]. The bolded portions of Chambers show that the descriptor of Chambers describes the data reformat operation to perform (e.g., the reformatting from the input format to the output format, which is either little endian format or big endian format). Claim 1 does not further elaborate on “describing” a data reformat operation, and the therefore the examiner is not convinced by applicant’s argument.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 25 of U.S. Patent No. 11,934,332 B2, in view of Schnarch et al (hereinafter Schnarch), US 20170060448 A1.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 11,934,332 B2
Claim 1. A data transfer device, comprising:
a device interface enabling communications with a data source; and
a data reformat unit, comprising:
circuitry that collects data received from the data source, references a descriptor that describes a data reformat operation to perform on the data received from the data source, reformats the data received from the data source according to the data reformat operation, and provides the reformatted data to the data source via the device interface.
Claim 1. A network device, comprising:
a device interface that receives data from at least one data source; and
a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target, wherein the descriptor comprises at least one of a work queue element (WQE) posted to a queue pair, a memory region description, a description of a Remote Direct Memory Access (RDMA) request, and a description of an application-level request.
‘332 does not explicitly disclose providing the reformatted data to the data source via the device interface.
However, Schnarch discloses providing the reformatted data to the data source via the device interface [paragraph 39, valid data pages of a target block from the SSD 510 to the host 550…The host 550 may analyze and reformat valid data within the valid data pages and return a new data structure comprising the valid data to the SSD 510].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Schnarch in ‘332, to implement providing the reformatted data to the data source via the device interface, in order to promote more efficient data storage that is capable of addressing invalid data [Schnarch, paragraph 14].
Claims 1 and 26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 20, respectively, of U.S. Patent No. 12,229,072 B2, in view of Schnarch et al (hereinafter Schnarch), US 20170060448 A1.
Please note that in the interest of time, the examiner is selecting only one of the independent claims from the instant application and U.S. Patent for the table below.
Instant Application
U.S. Patent No. 12,229,072 B2
Claim 1. A data transfer device, comprising:
a device interface enabling communications with a data source; and
a data reformat unit, comprising:
circuitry that collects data received from the data source, references a descriptor that describes a data reformat operation to perform on the data received from the data source, reformats the data received from the data source according to the data reformat operation, and provides the reformatted data to the data source via the device interface.
1. A system, comprising:
a device interface to receive data from at least one data source; and
circuitry to collect the data received from the at least one data source, receive a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, perform the data shuffle operation on the data to produce shuffled data, and then provide the shuffled data to at least one data target, wherein the descriptor comprises at least one of a processor instruction description, a work queue element (WQE) posted to a queue pair, a memory region description, a description of a Remote Direct Memory Access (RDMA) request, and a description of an application-level request.
‘072 does not explicitly disclose providing the reformatted data to the data source via the device interface.
However, Schnarch discloses providing the reformatted data to the data source via the device interface [paragraph 39, valid data pages of a target block from the SSD 510 to the host 550…The host 550 may analyze and reformat valid data within the valid data pages and return a new data structure comprising the valid data to the SSD 510].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Schnarch in ‘072, to implement providing the reformatted data to the data source via the device interface, in order to promote more efficient data storage that is capable of addressing invalid data [Schnarch, paragraph 14].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 9, 11, 16-18, 22-24, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers et al (hereinafter Chambers), US 5961640, in view of Schnarch et al (hereinafter Schnarch), US 20170060448 A1.
Referring to claim 1, Chambers discloses a data transfer device, comprising:
a device interface [fig. 3B, element 210] enabling communications with a data source [fig. 3B, Domain 1; see figs. 1B, 2, and 3 showing the data source (Domain 1) and target (Domain 2)]; and
a data reformat unit [fig. 3B, element 200a], comprising:
circuitry that collects [fig. 3B, in register 212] data received from the data source [Domain 1], references a descriptor [col. 2, lines 59-62, “Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet”; also see fig. 4A showing field 368 of the descriptor] that describes a data reformat operation to perform on the data received from the data source [fig. 5, data reformat operation equivalent to big endian to little endian OR little endian to big endian; steps 525 and 530 where ENDIAN_ALIGN[1:0] of the descriptor is read; col. 6, lines 35-41, “The ENDIAN_ ALIGN[1:0] field 368 of the present invention consists of two bits that are used to define the endian domain format of the input and the output data packets and define whether or not endian domain conversion is required by circuits 200 and 200a and also the required conversion manner. Specifically, bit 0 defines the input data packet endian orientation, where a data value of 0 represents little endian format and a data value of 1 represents big endian format. Bit 1 defines the output data packet endian orientation where a data value of 0 represents little endian format and a data value of 1 represents big endian format”], reformats the data received from the data source according to the data reformat operation [fig. 5, col. 10, lines 27-38, “At step 525, control circuit 270 reads bit 0 of ENDIAN_ALIGN [1:0] field 368 to determine if it is of value zero (little endian format). If so, then step 530 is entered as the input is in little endian format”…”At step 530, control circuit 270 reads bit 1 of ENDIAN_ ALIGN [1:0] field 368 to determine if it is of value zero (little endian format)”…”If not, then ‘B’ (FIG. 7B) is entered as the input is in little endian format but the output is in big endian format and endian conversion is required”].
Chambers does not explicitly disclose provide the reformatted data to the data source via the device interface.
However, Schnarch discloses provide the reformatted data to the data source via the device interface [paragraph 39, valid data pages of a target block from the SSD 510 to the host 550…The host 550 may analyze and reformat valid data within the valid data pages and return a new data structure comprising the valid data to the SSD 510].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Schnarch in the device of Chambers, to implement provide the reformatted data to the data source via the device interface, in order to promote more efficient data storage that is capable of addressing invalid data [Schnarch, paragraph 14].
Referring to claim 3, the modified Chambers discloses the data transfer device of claim 1, wherein the descriptor is provided by the data source [Chambers, col. 6, lines 19-23].
Referring to claim 4, the modified Chambers discloses the data transfer device of claim 1, wherein the descriptor is referenced for a plurality of data reformat operations [Chambers, fig. 5, steps 530, 540, 550].
Referring to claim 9, the modified Chambers discloses the data transfer device of claim 1, wherein the data source is accessed via a single device interface [Chambers, fig. 3B, element 210].
Referring to claim 11, the modified Chambers discloses the data transfer device of claim 1, wherein the data source uses a memory area [Schnarch, paragraph 39, valid data pages of a target block from the SSD 510].
Referring to claim 16, the modified Chambers discloses the data transfer device of claim 1, wherein the data reformat operation comprises at least one of a matrix transpose, a non-homogenous transpose, a data type conversion, a tensor layout conversion, color channel separation, and a change in endianity [Chambers, fig. 5, change in endianity].
Referring to claim 17, the modified Chambers discloses the data transfer device of claim 1, wherein the device is a network interface adapter or a DPU (data processing unit) [Chambers, fig. 3B showing a data processing unit].
Referring to claim 18, the modified Chambers discloses the data transfer device of claim 1, wherein an initiator of the data reformat operation is the data source [Chambers, col. 6, lines 19-23, descriptor originating from domain 1 (data source), the descriptor initiating data reformat operation].
Referring to claim 22, the modified Chambers discloses the data transfer device of claim 1, wherein the descriptor defines a requirement for endianness [Chambers, fig. 5, steps 525 and 530 where ENDIAN_ALIGN[1:0] of the descriptor is read; col. 6, lines 35-41, “The ENDIAN_ ALIGN[1:0] field 368 of the present invention consists of two bits that are used to define the endian domain format of the input and the output data packets and define whether or not endian domain conversion is required by circuits 200 and 200a and also the required conversion manner].
Referring to claim 23, the modified Chambers discloses the data transfer device of claim 1, wherein the data source comprises a peripheral device [Schnarch, paragraph 39, SSD 510].
Referring to claim 24, the modified Chambers discloses the data transfer device of claim 1, wherein the descriptor is stored in memory that is coupled with the circuitry [Chambers, Abstract, “Data descriptors located in a data packet header”; “the data packets obtained from the first bus 210 are supplied to a 32-bit incoming data register 212”] or in a remote memory.
Referring to claim 26, Chambers discloses a system, comprising:
circuitry [fig. 3B]; and
memory [fig. 3B, register 212] coupled with the circuitry [fig. 3B], wherein the circuitry is configured to collect data received from a data source [fig. 3B, Domain 1; see figs. 1B, 2, and 3 showing the data source (Domain 1) and target (Domain 2)] in the memory [col. 4, lines 47-48, “the data packets obtained from the first bus 210 are supplied to a 32-bit incoming data register 212”], reference a descriptor [col. 2, lines 59-62, “Data descriptors located in a data packet header define the endian input domain format, the expected endian output domain format, the data packet size and the start address in system memory of the input data packet”; also see fig. 4A showing field 368 of the descriptor] that describes a data reformat operation to perform on the data received from the data source [fig. 5, data reformat operation equivalent to big endian to little endian OR little endian to big endian; steps 525 and 530 where ENDIAN_ALIGN[1:0] of the descriptor is read; col. 6, lines 35-41, “The ENDIAN_ ALIGN[1:0] field 368 of the present invention consists of two bits that are used to define the endian domain format of the input and the output data packets and define whether or not endian domain conversion is required by circuits 200 and 200a and also the required conversion manner. Specifically, bit 0 defines the input data packet endian orientation, where a data value of 0 represents little endian format and a data value of 1 represents big endian format. Bit 1 defines the output data packet endian orientation where a data value of 0 represents little endian format and a data value of 1 represents big endian format”], reformat the data received from the data source according to the data reformat operation [fig. 5, col. 10, lines 27-38, “At step 525, control circuit 270 reads bit 0 of ENDIAN_ALIGN [1:0] field 368 to determine if it is of value zero (little endian format). If so, then step 530 is entered as the input is in little endian format”…”At step 530, control circuit 270 reads bit 1 of ENDIAN_ ALIGN [1:0] field 368 to determine if it is of value zero (little endian format)”…”If not, then ‘B’ (FIG. 7B) is entered as the input is in little endian format but the output is in big endian format and endian conversion is required”].
Chambers does not explicitly disclose provide the reformatted data to the data source.
However, Schnarch discloses provide the reformatted data to the data source [paragraph 39, valid data pages of a target block from the SSD 510 to the host 550…The host 550 may analyze and reformat valid data within the valid data pages and return a new data structure comprising the valid data to the SSD 510].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Schnarch in the system of Chambers, to implement provide the reformatted data to the data source, in order to promote more efficient data storage that is capable of addressing invalid data [Schnarch, paragraph 14].
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Williams, US 6775283 B1.
Referring to claim 2, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the descriptor is stored in a local memory or a remote memory and described by a match criteria on the data.
However, Williams discloses wherein the descriptor is stored in a local memory or a remote memory and described by a match criteria on the data [claim 7, “a descriptor in a network interface controller of a network interface card of a switch” (see fig. 1 where the switches can be local or remote); the descriptor containing…a virtual local area network (VLAN) tag control command, and a field for VLAN tag control information].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Williams in the device of the modified Chambers to implement, wherein the descriptor is stored in a local memory or a remote memory and described by a match criteria on the data, in order to reduces the processing burden placed on the switch [Williams, col. 2, lines 61-63].
Claim(s) 5-8, 20, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Spicer, US 20180232427 A1.
Referring to claim 5, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the device interface comprises a communication port connected with a communication network.
However, Spicer discloses wherein the device interface comprises a communication port connected with a communication network [paragraphs 6, 15, figs. 1-2, see endian conversion system 110 with first device interface 220 connected to network/bus 210 and network 120].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Spicer in the device of the modified Chambers to implement, wherein the device interface comprises a communication port connected with a communication network, in order to address the problem of data being incorrectly processed due to misinterpretation of the data [Spicer, paragraph 3].
Referring to claim 6, the modified Chambers discloses the data transfer device of claim 5, further comprising an additional device interface that comprises an additional communication port connected with the communication network [Spicer, fig. 2, second device interface 290 connected with network 120].
Referring to claim 7, the modified Chambers discloses the data transfer device of claim 5, further comprising an additional device interface that connects to the communication network [Spicer, fig. 2, second device interface 290 connected with network 120].
Referring to claim 8, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the device interface connects to a communication network.
However, Spicer discloses wherein the device interface connects to a communication network [figs. 1-2, first device interface 220 connecting to network 120].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Spicer in the device of the modified Chambers to implement, wherein the device interface connects to a communication network, in order to address the problem of data being incorrectly processed due to misinterpretation of the data [Spicer, paragraph 3].
Referring to claim 20, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein an initiator of the data reformat operation is an infrastructure layer.
However, Spicer discloses wherein an initiator of the data reformat operation is an infrastructure layer [paragraph 15, “The data source 130 may include any provider or generator of data. For example, the data source 130 may include providers or generators of video data, audio data, still image data textual data, numerical data, measurement data, calculated data, stored data, etc. The data source 130 may include hardware components, e.g., sensors, that may measure and report measured data such as temperature, humidity, pressure, velocity, or any of a variety of environmental, performance, or other measurable parameters. The data source 130 may include a data storage device that stores data in a non-volatile memory or a computing processor that generates data through computations. The data source 130 may have an endian type that is incompatible with an intended recipient of the data provided by the data source 130. Rather than send the data directly to an intended recipient that is of an endian type that is incompatible with the endian type of the data, the data source 130 may send the data to the data structure endian conversion system 110 over the computing network 120 to be converted from the data's endian type to the endian type of the intended recipient”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Spicer in the device of the modified Chambers to implement, wherein an initiator of the data reformat operation is an infrastructure layer, in order to address the problem of data being incorrectly processed due to misinterpretation of the data [Spicer, paragraph 3].
Referring to claim 25, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the descriptor is received from a control device that is different from the data source.
However, Spicer discloses wherein the descriptor is received from a control device that is different from the data source [paragraph 38, 29, The endian conversion element 280 may…endian-convert each of the data words in the first data message 310 according to the characteristics of the respective data words specified in the data format specification 320; In an embodiment, the data format specification 320 may include a JSON file; In some embodiments, a file defining the data format specification for each of one or more predefined data types may be stored in the memory circuits 250; hence Spicer discloses a control device that stores the JSON file, the control device is not a data source].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Spicer in the device of the modified Chambers to implement, wherein the descriptor is received from a control device that is different from the data source, in order to address the problem of data being incorrectly processed due to misinterpretation of the data [Spicer, paragraph 3].
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Kovvuri et al (hereinafter Kovvuri), US 20190286973 A1.
Referring to claim 13, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the data received from the data source comprises a neural network.
However, Kovvuri discloses wherein the data received from the data source comprises a neural network [paragraph 80, fig. 4, The compiler 420 analyzes the source code and data (e.g., the weights and biases learned from training the model) provided for a neural network model and transforms the model into a format that can be accelerated on the neural network server 410 and/or the neural network accelerator 450”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kovvuri in the device of the modified Chambers to implement, wherein the data received from the data source comprises a neural network, in order to provide higher performance, and/or more efficient structures [Kovvuri, paragraph 106].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Bloomfield et al (hereinafter Bloomfield), US 20130051701 A1.
Referring to claim 14, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the data received from the data source comprises image data.
However, Bloomfield discloses wherein the data received from the data source comprises image data [paragraph 19, When image data is provided to an application or GPU for transformation].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Bloomfield in the device of the modified Chambers to implement, wherein the data received from the data source comprises image data, in order to allow the primary processing unit(s) to focus on other activities, while the GPU can handle the specialized activities related to rendering images [Bloomfield, paragraph 1].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Boudris et al (hereinafter Boudris), US 6886018 B1.
Referring to claim 15, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the data received from the data source is formatted for use by a first version of an application and wherein the reformatted data is formatted for use by a second version of the application.
However, Boudris discloses wherein the data received from the data source is formatted for use by a first version of an application and wherein the reformatted data is formatted for use by a second version of the application [col. 6, lines 49-53, “The Version Validation and Reformat Routines 104 provide transitioning of previous record versions to current record versions to bring a previous file version up to the current file version for processing by the application system 24”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Boudris in the device of the modified Chambers to implement, wherein the data received from the data source is formatted for use by a first version of an application and wherein the reformatted data is formatted for use by a second version of the application, in order to implement changes when convenient so that the changes can be implemented with minimum affect on the users [Boudris, col. 1, lines 66-67].
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chambers, in view of Schnarch, as applied to claim 1 above, and further in view of Ogawa et al (hereinafter Ogawa), WO 2019210075 A1.
Referring to claim 21, the modified Chambers does not explicitly disclose the data transfer device of claim 1, wherein the circuitry of the data reformat unit is further configured to perform the data reformat operation on the data received from the data source and produce first reformatted data for the data source as well as second reformatted data from an additional data source, wherein the first reformatted data is formatted differently from the second reformatted data.
However, Ogawa discloses wherein the circuitry of the data reformat unit is further configured to perform the data reformat operation on the data received from the data source and produce first reformatted data for the data source as well as second reformatted data from an additional data source, wherein the first reformatted data is formatted differently from the second reformatted data [paragraph 277, fig. 17, The collected data is transmitted via a message bus 1703 to a distributed streaming analytics engine 1704, which applies various data transforms and machine learning algorithms… It can be appreciated that different data sources require different reformatting protocols].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Ogawa in the device of the modified Chambers to implement, wherein the circuitry of the data reformat unit is further configured to perform the data reformat operation on the data received from the data source and produce first reformatted data for the data source as well as second reformatted data from an additional data source, wherein the first reformatted data is formatted differently from the second reformatted data, in order to eliminate research time for users [Ogawa, Abstract].
Allowable Subject Matter
Claims 12 and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein no data target address is provided, and the device writes the reformatted data to a source address, in combination with other recited limitations in claim 12.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein no data target address is provided, and the reformatted data is written to a source address, in combination with other recited limitations in claim 27.
Claim 28 is objected to by virtue of its dependency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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