DETAILED ACTION
The action is responsive to the following: the request for continued examination, amendments to claims, and arguments made in an amendment filed on February 23, 2026.
Claims 1-9 are pending. Claim 1 is independent. Claims 1-9 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 23, 2026 has been entered.
Response to Amendment
The amendment filed on February 23, 2026 has been entered. Claims 1-9 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20210193661) in view of Morishita et al (US 20080251860).
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Regarding Independent Claim 1, Lee teaches a memory device (see Fig. 37) that uses a semiconductor element in which a page is made up of a plurality of memory cells arranged in a row direction of a substrate, wherein each of the plurality of memory cells contained in each of the pages comprising:
A memory device (see Fig. 37) that including a plurality of pages arranged in a column direction, each page including a plurality of memory cells arranged in a row direction of a substrate, and a plurality of the pages is arranged in a column direction, wherein each of the memory cells contained in each of the pages includes:
a semiconductor base material formed on the substrate in a first direction vertical to the substrate or formed to extend on the substrate in a second direction orthogonal to the first (Fig 37: 134),
a first impurity layer and a second impurity layer formed at opposite ends of the semiconductor base material (Fig 37: 102, 136), respectively,
a first gate insulating layer formed, in contact with, or close to, the first impurity layer, to at least partially surround a side surface of the semiconductor base material between the first impurity layer and the second impurity layer, or close to, the second impurity layer, surrounding the lateral surface of the semiconductor base material (Fig 37: 132),
a first gate conductor layer formed to cover part or all of the first gate insulating layer (Fig 37: 114),
a second gate conductor layer formed to cover at least part of the second gate insulating layer (Fig 37: 108), wherein the first impurity layer (Fig. 37: 136) is connected with a source line (Fig. 37: 102), the second impurity layer is connected with a bit line (Fig. 37: 150), one of the first gate conductor layer (Fig. 108a) and the second gate conductor layer (Fig. 37: 114) is connected with a word line, and the other of the first gate conductor layer and the second gate conductor layer is connected with a plate line, and
a channel semiconductor layer in which the semiconductor base material is covered with the first gate insulating layer and the second gate insulating layer (Fig 37: 134);
a page write operation (Fig 9: write1) and a page erase operation (Fig 9: write 0) on respective memory cells arranged in the selected one of the plurality of pages, wherein the page write operation is performed to apply a first write voltage (Table 1: Second voltage) to the word line of the respective memory cells to form positive holes by operation of an impact ionization phenomenon in the channel semiconductor layer of the respective memory cells, and wherein the page erase operation is performed to move a majority of the formed positive holes through the semiconductor body to erase the majority of the formed positive holes
wherein voltages are applied to the source line, the bit line, the word line and the plate line of at least some of the respective memory cells to perform a refresh operation (Fig 9: hold) for refreshing positive holes formed by the page write operation in the at least some of the respective memory cells, wherein the refresh operation is performed to apply a second write voltage (Table 1: turn-on voltage), lower than the first write voltage, to word lines of the at least some of the respective memory cells to regenerate positive holes groups by operation of the impact ionization phenomenon in the channel semiconductor layer of the at least some of the respective memory cells
Lee further teaches that the second impurity region “may be doped with impurities having a second conductivity type different from the first conductivity type. For example, the second conductivity type may be a P type.“ (para 59) and that “a substrate 100 of a cell region may be doped with impurities having the first conductivity type to form a common source region” (para 91). Though Lee does not teach that the two impurity regions are identical Lee, allows for the possibility that they are identical and it would be obvious to one of ordinary skill in the art to use identical impurity layers that are the same conductivity type for source and drain as is common in the art.
For instance, Morishita teaches a planar floating body transistor with a storage transistor (Fig. 3: STr) and access transistor (Fig. 3: ATr), wherein the drain (Fig. 3: 20) connected to the bit line (Fig. 3: BL) and the source (Fig. 3: 24) is connected to the source line (Fig. 3: SL) are the same conductivity type (para 54 and 56).
Lee also fails to teach a decoder circuit which selects one of a plurality of pages and fails to teach that a non-negative voltage is applied to both of the gates during a write operation.
Morishita however teaches a decoder circuit (Fig. 1: 2) and applying a non-negative voltage to the bit line, source line, and both word lines during write and refresh operations (Fig. 5: GL, WL, BL; para 88).
Morishita also teaches refresh operations (Fig. 5: 0 Ref, 1 Ref) and erase operations (Fig. 5: 0W).
Though Lee does not explicitly the teach a decoder circuit the use of such circuits to select one or more cells within the address space of the array in order to selectively program or read cells. Without decoder circuits memory arrays would be largely inoperable. Thus, the addition of such a decoder circuit would have been obvious to persons having ordinary skill in the memory art. Further the use of non-negative voltage is also common in the art as applying negative voltages to a gate typically requires the use of specialized circuitry such as charge pumps, which can be area and power intensive. Thus, using positive voltages and ground is standard practice when designing a memory device and would allow for lower power and more compact memory devices on chips.
It would have been obvious to one of ordinary skill in the art to apply the teachings of Morishita to the teaching of Lee to produce a columnar vertical floating body transistor as described in claim 1 with impurity layers that are identical conductivity types wherein the individual pages of the array are selected using a decoder circuit. And wherein the bit line, source line, and word lines are all set to non-negative voltages during operations applied to the cells of the memory array.
Regarding Claim 7, Lee and Morishita teach the limitations of Claim 1.
Lee further teaches a memory device, wherein a first gate capacitance between the first gate conductor layer and the channel semiconductor layer is higher than a second gate capacitance between the second gate conductor layer and the channel semiconductor layer (Fig. 44: Vmerge, Vselect, 24, 22, 20).
Regarding Claim 8, Lee and Morishita teach the limitations of Claim 1.
Lee further teaches a memory device, wherein the first gate conductor layer is separated into at least two conductor layers by surrounding the first gate insulating layer arranged along the semiconductor base material (Fig. 41: Vmerge, 24, 22).
Regarding Claim 9, Lee and Morishita teach the limitations of Claim 1.
Lee further teaches a memory device, wherein the page write operation, is performed to set a first retention voltage to the channel semiconductor layer to retain the positive holes generated by the impact ionization phenomenon in the channel semiconductor layer, and wherein the first data retention voltage is higher than a voltage applied to at least one of the first impurity layer and the second impurity layer (Paragraph [0080]); and
the page erase operation, is operated to apply voltages to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer, to move the positive holes out from one or both of the first impurity layer and the second impurity layer, and wherein the page erase operation is performed to set the channel semiconductor layer is set to a second data retention voltage lower than the first data retention voltage (Paragraph [0081-0085]).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Lee (US 20210193661) & Morishita (US 20080251860) & Kim (US 20130176788 A1).
Regarding Claim 2, Lee teaches the limitations of Claim 1.
Lee and Morishita however does not teach and address latch circuit for selecting at least one of the word lines.
Kim teaches an address latch circuit of a row decoder circuit for selecting WL in a flash memory (Fig 1: 40).
It would have been prima facie obvious to one of ordinary skill in the art to apply the teachings of Kim to the teaching of Lee to produce an array of memory device described in claim 1 with word lines selected by a latched row decoder.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210193661), Morishita (US 20080251860), Kim (US 20130176788 A1), & Hama (US 20120230117 A1).
Lee, Morishita and Kim teach the limitations of Claim 2.
Lee and Kim however do not teach an operation for selecting all word lines.
Hama teaches an operation where the row decoder circuit selects all the word lines in a flash memory cell block (Fig 5: S104, S105).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee, Kim, and Hama to provide a memory device outlined in claim 2, where all the rows can be selected simultaneously.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210193661), Morishita (US 20080251860) & Lu (US 20190259462 A1).
Lee and Morishita teach the limitations of Claim 1.
Lee and Morishita however fail to teach a refresh operation that is performed periodically.
Lu teaches a memory device that uses a semiconductor element, wherein the refresh operation is performed periodically (Paragraph [0146]).
It would have been prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee, Morishita, and Lu to produce the memory device recited in claim 1 with a refresh operation performed periodically.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210193661), Morishita (US 20080251860) & Prakash (US 20220284971 A1).
Lee teach the limitations of Claim 1.
Lee and Morishita however fail to teach a refresh operation performed periodically that is controlled by a temperature sensor circuit and timer circuit.
Prakash teaches a flash memory device that uses a semiconductor element, wherein the refresh operation is performed periodically using a temperature sensor circuit (Fig 1A: 115) and a timer circuit (Fig. 1A: 113a).
It would have been prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee, Morishita, and Prakash to produce the memory device of claim 1, wherein the refresh operation is performed periodically by a temperature sensor circuit and a timer circuit.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20210193661), Morishita (US 20080251860) & Pascucci (US 10825525 B2).
Lee and Morishita teach the limitations of Claim 1.
Lee and Morishita however fail to teach a drive control line that in the column direction is disposed in common to adjacent ones of the memory cells
Pascucci teaches cells where that share common control line across multiple rows and multiple columns (Fig. 6: Row_0).
It would have been prima facie obvious of one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee, Morishita, and Pascucci to produce the memory device of claim 1, wherein the drive control line of the memory cells arranged in the row direction and in the column direction is disposed in common to adjacent ones of the memory cells.
Response to Arguments
Applicant's arguments filed February 23, 2026 have been fully considered but they are not persuasive.
Applicant’s argument primarily has to do with differences between the method of operating the decoder circuit, which performs operations on a plurality of memory cells. As applicant’s claim is an apparatus claim dealing primarily with the specific physical structure of the memory cell, the method of operating the cells is not differentiate the claimed invention from the prior art. MPEP 2114(II) states ‘"[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim.’
Applicant has not pointed to any structural differences in the decoder circuit claimed that would lead one of ordinary skill in the art to understand that it is different from the decoder circuit recited by Morishita. The only differences are in how it is operated. Further, applicant makes no argument that the memory cells which make up the bulk of the structural claims are different in any way from prior art or that the memory cells of the prior art would function differently than the cells claimed. Thus, the rejections are maintained.
In response to applicant's arguments against the references of Morishita and Lee individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Yang (US 20230282576) Figure 2 and paragraphs 82 and 91-93, which shows a “dynamic flash memory” (DFM) that utilizes refresh and erase operations “similar to flash memory functionality” and performs read, program and erase operations by applying voltages to the word line to induce an electric field within the DFM cell’s cylindrical body. Yang also includes a definition of “impact ionization” or “collision ionization” in paragraph 57.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825