Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Osawa (US 2011/0074244 A1), Microchip (2016, Ultrasound), Savord (US 2019/0212424 A1), Tkzczyk (US 2012/0133001 A1), and Ante (DE 102015216471 A1).
Regarding claim 1, Osawa teaches an ultrasound device, comprising:
a plurality of [ultrasonic transducers] [[abstract] [fig. 5] ultrasonic probe has transmitting ultrasonic transducers #27a and receiving ultrasonic transducers #27b];
a [circuit] comprising [ultrasonic probe #11]:
a pulser configured to provide a signal to a [transducer] of the plurality of [ultrasonic transducers] [[fig. 5] #50 pulser connects to transmitting ultrasonic transducer #27a; [0054] +/- 20V and +/- 100V];
integrated analog processing receive circuitry [receiver #54] configured to process a signal produced by [a transducer] in response to receiving an acoustic signal [[0004] receive echoes from the body. By electrically processing the echoes received by the ultrasonic transducers, the ultrasonic image is obtained; [0052] both of the two ultrasonic transducers composing the single channel carry out transmission and reception.; [0064] single transmitting and receiving channel is constituted of the single transmitting ultrasonic transducer and the single receiving ultrasonic transducer]; and
an analog-to-digital converter (ADC) [A/D #55] configured to digitize a signal provided by the analog processing receive circuitry [[0039] the receiver 54 receives the detection signal amplified by the amplifier 53. The A/D 55 digitizes the detection signal from the receiver 54.], and
serial-deserialized (SERDES) transmit circuitry [parallel to serial converter P/S #56];
a second [circuit] comprising [portable ultrasonic observing device #10]:
SERDES receive circuitry [serial to parallel converter S/P #60] and integrated digital processing circuitry configured to digitally process a signal provided by the SERDES receive circuitry [beamformer #61],
a conductive communication link coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC [[0041] serial data is inputted to a serial-to-parallel converter (S/P) 60 of the portable ultrasonic observing device 10 through the cable 20, the connector 19, and the probe connection portion 17.].
Osawa does not explicitly teach and yet Microchip teaches wherein the first ASIC is configured to operate at a first operating voltage [[fig. 1-1] shows U1 HV7321 with output pulser voltages at 0 to +80V], wherein the integrated digital processing circuitry is configured to operate at a second operating voltage in a range of approximately 0.45-0.9 Volts [U2 MD1730 waveform transmitter with beamformer is powered by U3 MCP1727 low voltage regulator which shows +2.5V output voltage for interface between U2 and U1 in fig. 1-1; however, table B-2 indicates that U3 voltage regulator has an adjustable output voltage at 0.9V], and wherein the first operating voltage is at least twenty-five times greater than the second operating voltage [note: ratio between +80V to 0.9V is about 88 V/V which is understood to be greater than twenty five times].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to implement the two different voltages for the multiple chips as taught by Osawa, with the 0.9V for digital interface and 80V pulser voltage as taught by Microchip because digital communication only requires data to be exchanged electrically (i.e., at low voltage), whereas the pulser must produce enough acoustic power for imaging with the ultrasonic transducer (i.e., using high voltage).
Osawa does not explicitly teach and yet Savord teaches micromachined ultrasonic transducers [[0037] MUT devices … capacitive micromachined ultrasonic transducers … PVDF … PZT] wherein each MUT of the plurality of MUTs are configured to transmit and receive ultrasonic signals [[fig. 3] shows transmit pulse generator #302/#304 connected to transducer element #101n, as well as receiver amplifier #68, and the selection of a connection pathway to either transmit generator or receive amplifier being made with transit/receive switch #306; [0020] analog ASIC may further comprise a plurality of transmit/receive switches, each coupled to a respective one of the plurality of transmitters and a respective one of the plurality of amplifiers; [0037] microbeamformer applies timed transmit pulses to elements of each group of elements (patch) of the array; [0039] each adapted to controlling the reading of delayed digital echo signals for a different digital multiline echo signal]; wherein the first ASIC is implemented in a first technology node [[abstract] microbeamformer comprises one or more analog ASICs containing transmitters and amplifiers coupled to transducer elements, and one or more digital ASICs containing analog to digital converters and digital beamforming circuitry. The analog ASICs and the digital ASICs are manufactured by different integrated circuit processes; [0019] Preferably, the first feature size is equal to or larger than 0.18um; note: this is equivalent to 180 nanometers]; and wherein the second ASIC is implemented in a second technology node smaller than the first technology node [[0022] digital integrated circuit further comprises a digital ASIC. Preferably, the second integrated circuit process is suitable for high density digital integrated circuitry. Also preferably, the second feature size is equal to or smaller than 65nm.].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to modify the receivers and pulsers taught by Osawa, with the transmit pulser, receive amplifier, and transmit and receive switch as taught by Savord so that a single transducer element may serve as either a transmitter or receiver depending on the switch position. Finally, it would have been obvious to implement the circuit boards as taught by Osawa, with different feature sizes of different ASICs as taught by Savord because power consumption is reduced by using a different integrated circuit fabrication process for the digital ADC and beamforming integrated circuits than that used for the analog transmit/receive integrated circuits (Savord) [[0005] when the number of transducer elements exceeds the number of beamformer channels, multiplexing is generally employed and only a subset of the total number of elements of the transducer can be connected to the beamformer at any point in time. [0011]]; additional transmit/receive switch element may be included so that each element may be controlled to serve as a transmitter or a receiver in sequence [[0043]] (Savord).
Osawa does not explicitly teach and yet Tkaczyk teaches a plurality of micromachined ultrasonic transducers (MUT) arranged on a first device [[0029] the sensors may also include micro-electromechanical systems (MEMs) devices, such as, but not limited to, capacitive micro-machined ultrasonic transducers (cMUTs).];
a first application-specific integrated circuit (ASIC) arranged on a second device bonded to the first device comprising [[abstract] coupling the sensor stack to a substrate to form the detector module, and tiling a plurality of detector modules on a second substrate to form the tileable detector array]:
a second ASIC arranged on a third device mounted adjacent to the second device comprising [[0056] storing configuration data for the respective sensor stacks, timing and control of programming and operation of the ASICs in the respective sensor stacks, amplification, variable gain control and analog to digital converters to process the received signals from the sensor stacks]:
a conductive communication link coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC [[0070] coupling the sensor array interposer stack 256 to other electronics advantageously circumvents exposure of sensitive electronics such as ASICs to the severe vibrations and dust generated during the dicing process. Also, the use of the interposer 232 allows segregation of the sensor array forming process from the cleaner microelectronics attach process used to attach the sensor array interposer stack 256 to the ASIC];
wherein the conductive communication link comprises a through-silicon via (TSV) extending from the second ASIC of the third device to the first ASIC of the second device [[0090] stacking of the sensor directly on top of the ASIC having the TSVs disposed therethrough allows the formation of a tileable element that can be handled similar to a flip chip die]; and
wherein the first device, second device, and third device are stacked together within a probe housing [[0077] transducer assembly 306 may be disposed in an image acquisition device, such as an ultrasound probe; [0072] sensor stack 260 may then be attached to a first side of an interconnect layer that may include one or more ASICs].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to combine the high speed data bus as taught by Osawa, with the stacked sensor with ASICs as taught by Tkaczyk because coupling the sensor array interposer stack to other electronics advantageously circumvents exposure of sensitive electronics such as ASICs to the severe vibrations and dust generated during the dicing process (Tkaczyk) [[0070]].
Osawa does not explicitly teach and yet Ante teaches a first ASIC having integrated analog circuitry and a second ASIC having integrated digital circuitry [[abstract] two ASIC wafers can each have a different node size. In this way, digital and analog circuit functions can be distributed to the respectively more appropriate ASIC wafer of the two ASIC wafers in a space-saving and cost-saving manner. For example, by means of the first capping structure 18 realized first ASIC wafer originate from a high-voltage process. Thus, a node size of the first ASIC wafer is comparatively large and it makes sense to integrate an analog part (mixed signal part) on the first ASIC wafer. By means of the high-voltage option of the first ASIC wafer imperfections, such as a quadrature (eg on the sensor structure 16) Getting corrected. The by means of the second capping structure 20 On the other hand, the realized second ASIC can have a smaller node size. The digital part is preferably integrated in this case on the second ASIC wafer. In addition, the second ASIC wafer may include additional components such as a microcontroller, a pressure sensor, a humidity sensor, a memory and / or an EEPROM.].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to combine the high speed data bus as taught by Osawa, with first asic and second asic having respective integrated analog and digital circuitry as taught by Ante so that the two circuit functions can be distributed to the most appropriate ASIC wafer of the two ASIC wafers in a space saving and cost saving manner (Ante) [[abstract]].
Regarding claim 3, Osawa as modified by Savord teaches the ultrasound device of claim 1, wherein the first technology node is 65 nm, 80 nm, 90 nm, 110 nm, 130 nm, 150 nm, 180 nm, 220 nm, 240 nm, 250 nm, 280 nm, 350 nm, or 500 nm [[abstract]; [0019] first feature size is equal to or larger than 0.18um; [0022]].
Regarding claim 4, Osawa as modified by Savord teaches the ultrasound device of claim 1, wherein the second technology node is 90 nm, 80 nm, 65 nm, 55 nm, 45 nm, 40 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, or 3 nm [[abstract]; [0019]; [0022] second feature size is equal to or smaller than 65nm].
Regarding claim 7, Osawa teaches the ultrasound device of claim 1, wherein: the analog-to-digital converter (ADC) is one of multiple ADCs [[fig. 5] shows that A/D converters #55 are between receivers #54 and parallel to serial converter #56]; and the SERDES transmit circuitry is configured to transmit, to the second ASIC, data generated by the multiple ADCs in a multiplexed fashion [[0041] P/S 56 converts parallel data of the detection signals outputted from the A/Ds 55 into serial data.; [0063] multiplexer].
Regarding claim 8, Osawa teaches the ultrasound device of claim 1, wherein the ADC of the first ASIC is disposed electrically between the integrated analog processing receive circuitry and the SERDES transmit circuitry of the first ASIC [[fig. 5] shows that A/D converters #55 are between receivers #54 and parallel to serial converter #56].
Regarding claim 9, Osawa teaches the ultrasound device of claim 1. further comprising a printed circuit board (PCB), wherein: the conductive communication link comprises a trace of the PCB, and the SERDES receive circuitry of the second ASIC is disposed between the trace of the PCB and the integrated digital processing circuitry of the second ASIC [[0036] first and second conductor patterns 31a and 31b downward extends on the backing material 26. The first conductor patterns 31a are connected to transmission circuit boards 32a attached to the single side face of the mount support 25, with bonding wires 33, and the second conductor patterns 31b are connected to reception circuit boards 32b in a like manner. The transmission circuit boards 32a and the reception circuit boards 32b are flexible printed circuit boards made of a polyimide or the like.].
Regarding claim 10, Osawa does not explicitly teach and yet Microchip teaches the ultrasound device of claim 1, further comprising a printed circuit board (PCB), wherein the first and second ASICs are both coupled to the PCB [fig. 2-1 depicts a green circuit board with all integrated circuits mounted on board with reference designators U1, U2, and U3 shown in white silkscreen].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to mount the analog and digital integrated circuits as taught by Osawa, on a circuit board in the form of integrated circuits as taught by Microchip so that the circuits may interconnect electrically though they are formed from different semiconductor processes.
Regarding claim 11, Osawa teaches the ultrasound device of claim 1, wherein the first ASIC is disposed electrically between the plurality of MUTs and the second ASIC [ultrasonic probe #11 is between plurality of ultrasonic transmitters and receivers #27a #27b and ultrasonic observing device #10; [0037] bonding between the transmitting ultrasonic transducers. 27a and the transmission circuit boards 32a and between the receiving ultrasonic transducers 27b and the reception circuit boards 32b, and the like are carried out to complete the ultrasonic transducer array 21.].
Regarding claim 12, Osawa as modified by Savord teaches the ultrasound device of claim 1, wherein the second ASIC is bonded to the first ASIC via thermocompression bonding, eutectic bonding, silicide bonding or solder bonding [[0042] ASICs … other interconnect techniques such as stacked silicon dies, ceramic circuits or multi-chip modules may also be employed; note: "stacked silicon dies soldered" refers to a manufacturing technique where multiple silicon semiconductor dies (the active part of a chip) are placed directly on top of each other and connected using solder bumps].
Regarding claim 13, Osawa teaches the ultrasound device of claim 1, wherein the integrated analog processing receive circuitry comprises an analog amplifier [[0039] receiver is connected through an amplifier … analog to digital converter … amplifier amplifies a detection signal outputted as a voltage], an analog filter, analog beamforming circuitry, analog dechirp circuitry, analog quadrature demodulation (AQDM) circuitry, analog time delay circuitry, analog phase shifter circuitry, analog summing circuitry, analog time gain compensation circuitry, and/or analog averaging circuitry.
Regarding claim 14, Osawa teaches the ultrasound device of claim 1, wherein the integrated digital processing circuitry comprises one or more digital filters, digital beamforming circuitry, digital quadrature demodulation (DQDM) circuitry, averaging circuitry, digital dechirp circuitry, digital time delay circuitry, digital phase shifter circuitry, digital summing circuitry, digital multiplying circuitry, requantization circuitry, waveform removal circuitry, formation circuitry, backend processing circuitry [[0047] digital detection signals from the A/Ds 55 are converted into the serial data by the P/S 56, and the serial data is sent to the portable ultrasonic observing device 10.] and/or one or more output buffers [[0049] television signal produced by the DSC 63 is displayed on the monitor 15 as the ultrasonic image after the digital-to-analog conversion].
Regarding claim 15, Osawa as modified by Microchip teaches the ultrasound device of claim 1, wherein the pulser comprises a multi-level pulser [pg. 11 HV7321 is a 4-Channel, 5-Level, ±80V, 2.5A ultrasound transmit pulser with integrated transmit/receive switches. It is designed for medical ultrasound imaging].
Regarding claim 16, Osawa as modified by Savord teaches the ultrasound device of claim 1, the ADC comprises a delta-sigma ADC [[0046] an analog patch signal is converted to a sequence of digital echo samples by a low power ADC 603, preferably one which consumes 10 milliwatts or less, such as a successive approximation type ADC or a delta-sigma ADC.].
Regarding claim 17, Osawa as modified by Savord teaches the ultrasound device of claim 16, wherein the delta-sigma ADC lacks current integrators [[0010] use of delta-sigma modulation to implement resource-efficient ADCs in FPGA devices is described in "Integrated ADC for Altera CycloneIV Devices" Technical Brief 20110419 from Missing Link Electronics Inc., 1 Jan. 2011 (XP055361582); [0046] discusses delta-sigma ADC and does not mention current integrators].
Regarding claim 18, Osawa as modified by Savord teaches the ultrasound device of claim 1, wherein the plurality of MUTs comprise capacitive MUTs (CMUTs) [[0037] MUT devices … capacitive micromachined ultrasonic transducers … PVDF … PZT; [abstract] microbeamformer comprises one or more analog ASICs containing transmitters and amplifiers coupled to transducer elements, and one or more digital ASICs containing analog to digital converters and digital beamforming circuitry].
Regarding claim 19, Osawa as modified by Savord teaches the ultrasound device of claim 1, wherein the plurality of CMUTs are formed on a substrate bonded to the first ASIC [[0042] acoustic elements of the matrix array transducer 101 are connected directly to element pads of the analog AS I Cs 102 in a flip chip type interconnect. Control and group output signals are connected between the analog ASICs and the other components of the microbeamformer through a flexible interconnect (e.g., flex circuit) to a printed circuit board containing the other probe circuitry. Other interconnect techniques such as stacked silicon dies, ceramic circuits or multi-chip modules may also be employed.].
Regarding claim 20, Osawa as modified by Microchip teaches the ultrasound device of claim 1, wherein the first operating voltage is in a range of approximately 5-30 Volts or in a range of approximately 30-80 Volts [[[fig. 1-1] shows U1 HV7321 with output pulser voltages at 0 to +80V; U2 MD1730 waveform transmitter with beamformer is powered by U3 MCP1727 low voltage regulator which shows +2.5V output voltage for interface between U2 and U1 in fig. 1-1; however, table B-2 indicates that U3 voltage regulator has an adjustable output voltage at 0.9V].
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Osawa (US 2011/0074244 A1), Microchip (2016, Ultrasound), Savord (US 2019/0212424 A1), Tkzczyk (US 2012/0133001 A1), and Ante (DE 102015216471 A1) as applied to claim 1 above, and further in view of Rothberg (US 2015/0080724 A1).
Regarding claim 5, Osawas does not explicitly teach and yet Rothberg teaches the ultrasound device of claim 1. wherein: the conductive communication link supports a data rate of approximately 2-5 gigabits/second [[abstract] repeatable ultrasound transducer probe … optionally be connected to various types of external devices to provide additional processing and image rendering; [0120] CMUTs; [0124] ultrasound transducer probe having multiple types of interfaces for electrically connecting the transducer probe to external devices via corresponding wired or wireless links. For example, higher speed and lower speed interfaces; [0128] high speed interfaces…SerDES … 10 GB, 40 GB, 100 GB Ethernet].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to implement the serial communication link as taught by Osawa, with the high speed interfaces as taught by Rothberg so the amount of ultrasound data provided by the ultrasound transducer probe to an external device may be maximized (Rothberg) [0132].
Regarding claim 6, Osawa does not explicitly teach and yet Rothberg teaches the ultrasound device of claim 1, wherein the conductive communication link is a first conductive communication link, and wherein the ultrasound device comprises multiple conductive communication links operating in parallel and coupling the SERDES transmit circuitry of the first ASIC and the SERDES receive circuitry of the second ASIC [[0128] high speed interfaces … SerDES; [0133] multiple interfaces of a single type are included on a transducer probe of the types described herein, not all such interfaces need be used … all four such interfaces may be utilized for example when it is desired to maximize data output from the ultrasound transducer probe].
It would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the invention to implement the serial communication link as taught by Osawa, with the high speed interfaces as taught by Rothberg so the amount of ultrasound data provided by the ultrasound transducer probe to an external device may be maximized (Rothberg) [0132].
Response to Arguments
Applicant’s arguments, see pgs. 6-8, filed 3/24/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ante (DE 102015216471 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JONATHAN D ARMSTRONG/Examiner, Art Unit 3645
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