DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-12, 15, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shan (US 20170219649 A1).
Regarding Claim 1, Shan teaches:
A method for analog simulation of a circuit model, the circuit model comprising a digital circuit model, the digital circuit model comprising an oscillator, the oscillator comprising logic devices, and the method comprising: (¶9 generates an oscillation waveform by using the time delay of the inverters and inverse functions thereof ... the effect of temperature fluctuations on the ring oscillator cannot be eliminated. It can be found by HSPICE simulation; examiner notes that HSPICE simulations inherently models of what they are simulating; ¶13 the self-timing oscillation ring is constituted by 9 two-input Miller units and inverters, and a two-input AND gate ... the self-timing oscillation ring has 9 stages)
obtaining a plurality of different environment variable values of the circuit model; (¶34 The process corner detection module is simulated with different process corners and at different temperatures)
obtaining delay time of a relevant logic device in the oscillator under the plurality of different environment variable values according to the plurality of environment variable values, (¶9 generates an oscillation waveform by using the time delay of the inverters and inverse functions thereof ... the effect of temperature fluctuations on the ring oscillator cannot be eliminated. It can be found by HSPICE simulation; ¶33 After finishing the design of the process corner detection circuit based on the self-timing oscillation ring, the HSPISE tool is used to perform simulation. The HSPICE simulation result of the process corner detection module is shown in FIG. 5.; ¶34 The process corner detection module is simulated with different process corners and at different temperatures)
the relevant logic device being a logic device whose delay time is affected by the plurality of environment variable values; (¶13 the self-timing oscillation ring is constituted by 9 two-input Miller units and inverters, and a two-input AND gate ... the self-timing oscillation ring has 9 stages; ¶16 In the self-timing oscillation ring, when increase of the temperature causes the time delay of the Miller unit in a certain stage to increase; examiner notes that both the inverters and Miller units are affected by temperature change, with the idea of the reference that all together the "stages may compensate each other so that the time delay of the whole oscillation ring may maintain stability relatively." (¶16))
inputting the delay time of each of the logic devices in the oscillator under the plurality of different environment variable values into the digital circuit model to perform a simulation test; (¶9 generates an oscillation waveform by using the time delay of the inverters and inverse functions thereof ... the effect of temperature fluctuations on the ring oscillator cannot be eliminated. It can be found by HSPICE simulation; ¶33 After finishing the design of the process corner detection circuit based on the self-timing oscillation ring, the HSPISE tool is used to perform simulation. The HSPICE simulation result of the process corner detection module is shown in FIG. 5.; ¶34 The process corner detection module is simulated with different process corners and at different temperatures; examiner notes that the HSPICE simulations determine the delay and use it in their timing simulations with results shown on Fig.5, which falls within the scope of the claim language (the claim language including scenarios where the simulation is used to obtain the delay that is then used for further simulation).)
obtaining frequencies of an output signal from the oscillator under the plurality of different environment variable values; and (¶9 The change of the process corner of the ring oscillator based on an inverter chain may change its oscillation frequency, but changes of the voltage and temperature may also affect the oscillation frequency.)
obtaining a relationship between the plurality of environment variable values and the frequencies of the output signal from the oscillator according to the frequencies of the output signal from the oscillator under the plurality of different environment variable values, to digitize the plurality of environment variable values. (¶35 Therefore, when the process corner is determined according to the counting result of the oscillation ring, it is possible to take into account only the counting result within a normal variation range of environment temperature, i.e., situations between −25° C. and 50° C. Specific determination values are as shown in Table 2.; examiner notes that the counting result is equivalent to frequency, as it is the number of cycles in a given time period.)
Regarding Claim 2, Shan teaches:
obtaining a simulation relationship netlist of the relevant logic devices in the oscillator, the simulation relationship netlist comprising a plurality of environment variable values and a plurality of corresponding delay times. (¶33 After finishing the design of the process corner detection circuit based on the self-timing oscillation ring, the HSPISE tool is used to perform simulation. The HSPICE simulation result of the process corner detection module is shown in FIG. 5.; ¶34 The process corner detection module is simulated with different process corners and at different temperatures; examiner notes that one of ordinary skill in the art would understand HSPICE simulations as used by the reference inherently operate based on netlists and that therefore an HSPICE simulation involves netlists, thereby falling within the scope of the claim language.)
Regarding Claim 3, Shan teaches:
obtaining number of oscillations of the oscillator within a preset time period under the plurality of different environment variable values; and (¶35 Therefore, when the process corner is determined according to the counting result of the oscillation ring, it is possible to take into account only the counting result within a normal variation range of environment temperature, i.e., situations between −25° C. and 50° C. Specific determination values are as shown in Table 2.)
calculating the frequencies of the output signal from the oscillator under the plurality of different environment variable values according to the number of oscillations of the oscillator within the preset time period. (¶35 Therefore, when the process corner is determined according to the counting result of the oscillation ring, it is possible to take into account only the counting result within a normal variation range of environment temperature, i.e., situations between −25° C. and 50° C. Specific determination values are as shown in Table 2.; examiner notes that the counting result is equivalent to frequency, as it is the number of cycles in a given time period.)
Regarding Claim 4, Shan teaches:
wherein the plurality of environment variable values comprise an environment temperature, (¶34 The process corner detection module is simulated with different process corners and at different temperatures; ¶35 the temperature of the chip may be regarded to be the same as the environment temperature)
establishing a digital simulation model according to the relationship between the environment temperature values and the frequencies of the oscillator. (¶33 After finishing the design of the process corner detection circuit based on the self-timing oscillation ring, the HSPISE tool is used to perform simulation. The HSPICE simulation result of the process corner detection module is shown in FIG. 5.; ¶34 The process corner detection module is simulated with different process corners and at different temperatures)
Regarding Claim 7, Shan teaches:
wherein the logic device comprises at least one of an inverter, a NAND gate or a NOR gate. (¶13 the self-timing oscillation ring is constituted by 9 two-input Miller units and inverters, and a two-input AND gate ... the self-timing oscillation ring has 9 stages)
Regarding Claim 8, Shan teaches:
wherein the plurality of environment variables comprise a control voltage of the logic device. (¶6 The local variation is increasing as a CMOS process size is scaling. Scaling of a transistor size may cause a standard deviation σVT of a threshold voltage and a current factor σk/k(k=μCOXW/L) to increase because they are proportional to the square root of the reciprocal of the area of an active region.; examiner notes that the simulations of Shan are by process corner as well as by temperature, and process corner variations result in varied control voltages as set forth by the above citation)
Regarding Claims 9-14:
Claims 9-14 are substantially similar to claims 1-6 respectively, and are rejected under the same grounds as those set forth above for claims 1-6.
Regarding Claim 15, Shan teaches:
A computer device comprising a memory and a processor, the memory storing a computer program executable by the processor to implement the method according to claim 1. (the grounds of rejection presented above for claim 1 are equally applicable to claim 15, see ¶33, “HSPICE simulation”, and note that performing an HSPICE simulation inherently requires a computer with a processor, memory, and program instructions)
Regarding Claim 16, Shan teaches:
A non-transitory computer-readable storage medium storing a computer program thereon, the computer program is executable by a processor to implement the method according to claim 1. (the grounds of rejection presented above for claim 1 are equally applicable to claim 15, see ¶33, “HSPICE simulation”, and note that performing an HSPICE simulation inherently requires a computer with a processor, memory, and program instructions)
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 6, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shan (US 20170219649 A1) in view of Hanzhou University (CN 109632117 A, cited by applicant on the IDS dated 11/29/2022 as Foreign Patent Document 1).
Regarding Claim 5:
Shan does not teach in particular, but Hanzhou University teaches:
wherein the circuit model further comprises a simulation circuit model, the simulation circuit model comprising a temperature sensor; (Abstract, an on-chip temperature detection method based on an RC oscillator)
obtaining a temperature value of the temperature sensor; and (Abstract, The CPU obtains the temperature value corresponding to the frequency of the current clock signal through a table look-up method)
inputting the temperature value of the temperature sensor into the digital simulation model, such that the digital simulation model outputs a corresponding digital signal value (Abstract, The CPU obtains the temperature value corresponding to the frequency of the current clock signal through a table look-up method; see also Shan as cited for Claim 4, note that in the combination the look-up table would be generated by Shan's simulation.)
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the on-chip temperature detector to the circuit being simulated in HSPICE by Shan, and to use the HSPICE simulation results of Shan to populate the look-up table of Hangzhou University, in order to greatly reduce the chip area occupied by the temperature sensor, and meet the application requirements of various clock control at the same time (Hangzhou University), while enabling simulation (and thereby population of the look-up table) before the chip tape-out (Shan, abstract).
Regarding Claim 6:
The combination of Shan and Hanzhou University as set forth above teaches:
adjusting the temperature of the circuit model according to the corresponding digital signal value outputted by the digital simulation model. (examiner notes that as defined by the claim language, the digital simulation model is having a temperature value input into (claim 5) in order to output a corresponding digital signal value, and the digital simulation model is defined as being established according to the relationship between the environment temperature values and the frequencies of the oscillator (claim 4). This implies that inputting a temperature (as claimed) would result in a frequency output, but this claim appears to expect a further temperature output, without specifying in any way how this is generated. It is unclear how a temperature input into a model that relates temperature to frequency could generate another temperature (the expectation being that a frequency would be output). The simulations of Shan, however, do simulate at multiple temperatures, and this is loosely based on the previous temperatures simulated (to avoid duplicate simulations), so absent any further clarification of how an input temperature results in an output temperature, the claims are being interpreted to include the scenario where the adjusted temperature is the next temperature to be simulated based on the previous temperature having been simulated and related to a frequency (i.e. what the combination of the references provides))
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to apply the on-chip temperature detector to the circuit being simulated in HSPICE by Shan, and to use the HSPICE simulation results of Shan to populate the look-up table of Hangzhou University, in order to greatly reduce the chip area occupied by the temperature sensor, and meet the application requirements of various clock control at the same time (Hangzhou University), while enabling simulation (and thereby population of the look-up table) before the chip tape-out (Shan, abstract).
Regarding Claims 13 and 14:
Claims 13 and 14 are substantially similar to claims 5 and 6 respectively, and are rejected under the same grounds as those set forth above for claims 5 and 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kerber (A. Kerber, T. Nigam, P. Paliwoda and F. Guarin, "Reliability Characterization of Ring Oscillator Circuits for Advanced CMOS Technologies," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 230-241, June 2020) discloses simulation of complex factors for ring oscillator circuits that accounts for temperature based variability and effects, and characterizes them for the oscillator.
Nunez (J. Nuñez et al., "Experimental Characterization of Time-Dependent Variability in Ring Oscillators," 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lausanne, Switzerland, 2019, pp. 229-232) discusses fabrication and simulation of a ring oscillator in regards to its temperature dependence.
Biabanifard (Biabanifard, S., Largani, S. M. H., & Asadi, S. (2015). Delay time analysis of combined CMOS ring oscillator. International Journal of Electronics and Electrical Engineering, 4(2), 53-64.) explicitly discloses the consideration of individual inverters and other gates and their associated delays when calculating the performance of an oscillator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIJAN MAPAR whose telephone number is (571)270-3674. The examiner can normally be reached Monday - Thursday, 11:00-8:30.
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/BIJAN MAPAR/ Primary Examiner, Art Unit 2189