DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-17, and 19-20 are objected to because of the following informalities:
Claim 1 line 3; claim 12 line 8 recites "the channelizer output". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "the reconfigurable channelizer's output".
Claim 1 line 4; claim 9 line 2; claim 12 line 9; claim 16 line 2 "the polyphase filter" should be "the polyphase filter circuit" as antecedently recited.
Claims 2-11 line 1 "The channelizer" should be "The reconfigurable channelizer" as antecedently recited.
Claim 3 line 9; claim 13 line 9 "the second channel" should be “the second channel circuit" as antecedently recited.
Claim 4 line 2; claim 14 line 2 "the processing stages" should be "the five serially cascaded processing stages" to clearly identify such processing stages referring to the five serially cascaded processing stages as antecedently recited.
Claims 5-6, 8, 11 line 1; claim 12 line 6; claim 15 line 1; claim 17 line 1 "the channelizer" should be "the reconfigurable channelizer" as antecedently recited.
Claim 10 line 1; claim 16 line 3-4 "the channelizer output frequency domain data" should be "the reconfigurable channelizer's output frequency domain data" to clearly refer to output of the reconfigurable channelizer.
Claim 9 line 1; claim 10 line 2; claim 16 line 1 and line 4-5; claim 19 line 1; claim 20 line 2 "the number of frequency bins" should be "the number of the frequency bins" as antecedently recited.
Claim 12 line 5-6 "channelizer output" should be "the reconfigurable channelizer's output" to clearly refer to output of the reconfigurable channelizer.
Claims 9, 16 19 line 3 "the range" should be "a range" because there is lack of antecedent basis for such limitations antecedently recited.
Claim 20 recites "the channelizer output frequency domain data". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets such limitation as "the output frequency domain data".
Dependent claims are also objected for inheriting the same deficiencies in which claims they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2, 9-12, and 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract idea without significantly more.
Claim 1 recites an apparatus
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites steps to filter time domain input data, wherein filter coefficients and a number of folds of the polyphase filter are dynamically reconfigurable; and to transform the filtered time domain input data to output frequency domain data distributed into the frequency bins, wherein a number of the frequency bins is dynamically reconfigurable. Such limitations cover mathematical calculations, relationship, and/or formula (see at least figure 4 illustrates the multiply and accumulate operations for the filtering to generate filtered data p0-p64 and [0033] describes the mathematical operations to filter data, and FFT transformation is also a mathematical operation to transform data from one domain to another domain using butterfly operations, see figure 12 illustrates butterfly operation includes multiply and add operations. Thus, the claim recites limitations that perform mathematical operations on reconfigurable parameters (e.g., filter coefficients, number of folds, and number of channels or bins), which are merely variables). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a reconfigurable channelizer comprising: a polyphase filter circuit and a fast Fourier transform circuit and also recites the parameters (e.g., filter coefficients, number of folds, and number of frequency bins are dynamically programmable). However, the additional elements are recited at a high level of generality, i.e., as computer components performing computer functions of processing data based on the programmable variables. The claim further recites to control spectral shaping of frequency bins of the channelizer output, but such limitation is merely a result of performing the mathematical operations of filtering and also at most considered as mere generally linking the use of the judicial exception into a particular technological environment or field of use, such as digital signal processing. Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer components. Thus, the claim is directed to an abstract idea.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously with respect to the step 2A prong two, the additional elements in the claim amount to no more mere instructions to apply the exception. Thus, the claim does not provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception, and fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C 101.
Claim 2 further recites wherein the FFT circuit is employed to implement an inverse fast Fourier transform. The limitation of implementing an inverse fast Fourier transform cover mathematical calculations, relationship, and/or formula (e.g., performing IFFT operation), and the FFT circuit is recited at a high level of generality as explained above and amount to no more than mere instructions to apply the judicial exception using computer components. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 further recites wherein the number of frequency bins is dynamically programmable to one of 64, 128, 256, 512, or 1024, and the number of folds of the polyphase filter is dynamically programmable in the range of one to seven. Such limitation of dynamically reconfiguring the number of frequency bins to one of 64, 128, 256, 512, or 1024 and the number of folds of the polyphase filter is in the range of one to seven cover mathematical calculations, relationship, and/or formula (such as mere description of the selected parameters being performed on the mathematical operations, see at least figure 4 illustrates 64 bins operates with 448 taps, wherein the number of folds is 7 as describe in [0033] to generate p0. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 10 further recites the channelizer output frequency domain data is organized into frames, the frames of length proportional to the number of frequency bins. Such limitations cover mathematical calculations, relationship, and/or formula (merely describes organization of output data into frames and the length is proportional to the number of output channels or bins generated using the filtering and FFT transformation see at least figure 3A). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101
Claim 11 further recites the channelizer is implemented in an application specific integrated circuit. Such limitation is recited at a high level of generality and amount to no more than mere instructions to apply the exception using computer component. Thus, The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 12 and 16-17 recite apparatus claims having similar limitations as the apparatus claims 1 and 9-11. Thus, they are rejected for the same reasons. claim 12 further recites a receiver comprising an analog to digital converter (ADC) configured to convert a received analog signal to a time domain digital signal, such limitation is recited at a high level of generality and the step of converting analog signal to digital signal using ADC is at most considered as insignificant extra solution activity under step 2A prong two because such step is well known to convert received analog to digital domain for subsequent processing in digital domain and such step is determined to be well-understood, routine, and conventional under step 2B (see at least Analog, Devices Inc. Engineer, Analog Devices Inc., and Devices Inc. Engineer, Analog Devices Inc. Analog. Data Conversion Handbook, Elsevier Science &
Technology, 2004 page 621 figure 8.96 illustrates a receiver having ADC to convert analog data to digital data. The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 18-20 recite method claims that would be practiced by the apparatus claims 1 and 9-11. Thus, they are rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 9-10, 12, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Scott – US 20200036398 in view of Brede – US 20020098795.
Regarding claim 1, Scott teaches a reconfigurable channelizer (Scott figure 2 [0027] illustrates a dynamically reconfigurable channelizer 102) comprising:
a polyphase filter circuit configured to filter time domain input data to control spectral shaping of frequency bins of the channelizer output (Scott figure 2 [0029] illustrates an adaptive filter 120, wherein the adaptive filter 120 is an adaptive polyphase FIR filter [i.e., a polyphase filter circuit] configured to filter RF input signal 106 [i.e., time domain data]. [0038] also described the coefficients parameters [i.e., coefficient filters] that adjust the bandwidth of the output channel 121. Thus, the coefficient filter is used to control spectral shaping of frequency bins of the channelizer 102, wherein frequency domain is generated after the FFT transformation by the FFT circuit), wherein filter coefficients and a number of folds of the polyphase filter are dynamically programmable (Scott [0040] figure 4 describes a plurality of filter branches, wherein the filter branches can dynamically tapped to actively reconfigure the adaptive filter, [0043] describes the adaptive filter 120 provides a very flexible filter capable of implementing an arbitrary filter shape, which is controlled by the number of filter taps. [0055] also describes that the system 102 allow for dynamic reconfiguration of filtering coefficients. Thus, the number of taps per branch [i.e., a number of folds] and filter coefficients are dynamically programmable); and
a fast Fourier transform (FFT) circuit configured to transform the filtered time domain input data to output frequency domain data distributed into the frequency bins (Scott figure 2 illustrates FFT circuit 122 [i.e., a FFT circuit], and [0031] transform the output channels 121 [i.e., the filtered time domain input data] from the adaptive filter to generate frequency domain data distributed into the output channels 123 [i.e., the frequency bins] )
Scott does not teach a number of the frequency bins is dynamically programmable. However, Brede teaches an FFT circuit having a number of the frequency bins is dynamically programmable (Brede figure 70 [0453-0454] describes an FFT system 2100 [i.e., an FFT circuit] having a size select 2116 to select between various transform sizes, providing select ability for a 1024-point transform, a 512-point transform, a 256-point transform, a 128-point transform, a 64-point transform, or a 32-point transform, and the number of point corresponds to the number of frequency bins, such as 64 point corresponds to 64 frequency bins. Accordingly, the size or number of frequency bins is dynamically programmable).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the FFT circuit of the reconfigurable channelizer of Scott to be a reconfigurable size FFT circuit as described in Brede. This modification would have been obvious because both references discloses FFT circuit configured to transform time domain to frequency domain, and Scott discloses a channelizer that can be dynamically reconfigurable, but is silenced regarding changing the size of the FFT circuit. Thus, having an a various transform sizes FFT circuit as in Brede allow the system to be more flexible.
Regarding claim 2, the combined system of Scott in view of Brede teaches the channelizer of claim 1, but does not teach wherein the FFT circuit is employed to implement an inverse fast Fourier transform. However, another embodiment of Brede teaches the FFT circuit is employed to implement an inverse fast Fourier transform (Brede [0459-0460] describes the FFT system 2100 is implemented on a single IC that perform both FFT and inverse fast Fourier transform, wherein the system 2100 includes a signal 2119 that selects between the two type of transforms)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the FFT circuit of the combined system of Scott in view of Brede to have FFT circuit to implement FFT and IFFT. This modification would have been obvious because as recognized by Brede [0460], that IFFT uses the identical calculation sequence as the forward transform (i.e., FFT), but the complex values of twiddle factors and coefficients are conjugated. Furthermore, having an FFT circuit to implement both FFT and IFFT further increases the flexibility of the overall circuit.
Regarding claim 7, the combined system of Scott in view of Brede teaches the channelizer of claim 1, wherein the polyphase filter circuit comprises a crossbar circuit configured to align the time domain input data with the filter coefficients and a multiply circuit configured to multiply the aligned time domain input data with the filter coefficients (Scott figure 4 illustrates implementation of adaptive filter 120 [i.e., the polyphase filter circuit] comprises a plurality of sample and hold circuit 304 [i.e., a crossbar circuit], wherein [0040] the S/H output signals are routed to a plurality of FIR filter branches 306 to perform operations with coefficient parameter 118 set via coefficient input module 108 [0043]. Thus, the time domain input data is aligned with filter coefficients and branches 306 illustrates multiply circuit configured to multiply the aligned time domain input with filter coefficients).
Regarding claim 9, the combined system of Scott in view of Brede teaches the channelizer of claim 1, wherein the number of frequency bins is dynamically programmable to one of 64, 128, 256, 512, or 1024 (Brede [0453-0454] figure 70 describes the selectable sizes of FFT includes 1024-point transform, a 512-point transform, a 256-point transform, a 128-point transform, or a 64-point transform) and also teaches that the number of folds of the polyphase filter is dynamically programmable (Scott [0040] figure 4 describes a plurality of filter branches, wherein the filter branches can dynamically tapped to actively reconfigure the adaptive filter, [0043] describes the adaptive filter 120 provides a very flexible filter capable of implementing an arbitrary filter shape, which is controlled by the number of filter taps), but the combined system of Scott in view of Brede does not teach the number of folds of the polyphase filter is dynamically programmable in the range of one to seven. However, another embodiment of Brede discloses a number of folds of a polyphase filter is in the range of one to seven (Brede figure 31 [0327] illustrates a polyphase filter 122 [i.e., a polyphase filter] that comprises a plurality of branches that each branch includes 5 taps [i.e., a number of folds in the range of one to seven] as illustrated in figure 32, and [0329] describes that one skilled in the art will recognize that the number of tap can vary).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the branches of the polyphase filter described in the combined system of Scott in view of Brede to include 5 taps in each branch as described in Brede figure 32. This modification would have been obvious because both references disclose polyphase filter, where Scott describes an adaptive polyphase filter that the number of taps can be controlled dynamically and Brede describes the number of tap for each branch to be 5. Furthermore, figure 4 of Scott illustrates the number of taps per branch is greater than 5, thus reducing the number of tap of each branch to 5 also reduces the number of multipliers and adders that needed to carry out operation. Therefore, such modification allows the system to decrease the number of computation needed to be performed.
Regarding claim 10, the combined system of Scott in view of Brede teaches the channelizer of claim 1, wherein the channelizer output frequency domain data is organized into frames, the frames of length proportional to the number of frequency bins (Scott, figure 4 illustrates at least 8 output 123a-123h [i.e., the channelizer output frequency domain data], wherein [0041] describes a first real output channel 123a is output on a first clock cycle, a second real output channel 123b is output on a second clock cycle, etc. thus the output channels data of the channelizer is organized into frames, and length of the frames [i.e., the frames of length] corresponds [i.e., proportional] to the number of output channels 123 [i.e., the frequency bins]).
Claim 12 recites apparatus claim having similar limitations as claim 1. Thus, it is rejected for the same reasons. Claim 12 further recites a receiver comprising an analog to digital converter (ADC) configured to convert a received analog signal to a time domain digital signal. Scott teaches a receiver comprising a reconfigurable channelizer (Scott figure 2 [0010] describes a digital receiver including a dynamically reconfigurable channelizer), but Scott does not explicitly teach a receiver comprising an analog to digital converter (ADC) configured to convert a received analog signal to a time domain digital signal. However, another embodiment of Brede teaches a receiver comprising an analog to digital converter (ADC) configured to convert a received analog signal to a time domain digital signal (Brede figure 31 [0104] illustrates a receiver comprising A/D convertor [i.e., ADC] configured to convert analog to time domain digital signal and feed to the polyphase filter and FFT circuit)
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the receiver as illustrated in Scott to include an ADC as illustrated in Brede figure 31 to convert analog to digital signal. This modification would have been obvious because both references discloses digital receiver, and Scott discloses a receiver for receiving RF input signal and operate in digital domain for polyphase filter and FFT, but Scott does not explicitly recite an ADC within the receiver. Thus, all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention, which is a receiver having ADC to convert analog RF input signal to digital domain. See MPEP 2141(III) (A) Combining prior art elements according to known methods to yield predictable results.
Claim 16 recites apparatus claim having similar limitations as apparatus claims 9-10. Thus, it is rejected for the same reasons.
Claims 18-20 recite method claims that would be practiced by the apparatus claims 1, and 9-10. Thus, they are rejected for the same reasons.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Scott in view of Brede as applied to claim 1 above, and further in view of Harris - US 8958510.
Regarding claim 8, the combined system of Scott in view of Brede teaches the channelizer of claim 1, but does not teach the channelizer is configured to generate the frequency bins for output at a rate equal to two times a frequency spacing between the frequency bins. However, Harris teaches a channelizer is configured to generate frequency bins for output at a rate equal to two times a frequency spacing between the frequency bins (Harris figure 1 illustrates a channelizer 100 that generate M channels [i.e., frequency bins] for output, wherein figure 2D column 3 line 55-56 describes channel spacing [i.e., a frequency spacing] equal to Fs/M, where Fs is the input sample rate, and figures 3A-B column 4 line 13-22 describes the fourth option (e.g., fig. 2D) where the output sample rate is twice the channel spacing or the out sample rate is 2Fs/M [i.e., output at a rate equal to two times a frequency spacing between the frequence bins]. Note that this is similar to the description of [0030] of specification).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the channelizer of the combined system of Scott in view of Brede to generate the channels or frequency bins at a rate that is twice the channel spacing between the channels as described in Harris. This modification would have been obvious because the references discloses a channelizer for channelizing input signal, and as recognized by Harris at column 4 line 16-20, having output sample rate twice the channel spacing satisfies the Nyquist sampling criteria and avoids the spectral folding at the band edge as illustrated in 301 302 in figure 3.
Claims 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Scott in view of Brede as applied to claims 1 and 12 above, and further in view of Velazquez - US 20130016798.
Regarding claim 11, the combined system of Scott in view of Brede teaches the channelizer of claim 1, but not does not teach the channelizer is implemented in an application specific integrated circuit. However, Velazquez teaches the channelizer is implemented in an application specific integrated circuit (Velazquez figure 8 illustrates a channelizer 220 is implemented in an ASIC, [0091] describes the present invention (including ADC) can be implemented in an ASIC to significantly reduce size, power consumption).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the channelizer 102 of the combined system of Scott in view of Brede to implement the channelizer in an ASIC as described in Velazquez. This modification would have been obvious because the references discloses channelizer and as recognized by Velazquez [0091], implementing the channelizer in an ASIC significantly reduces size and power consumption.
Claim 17 recites apparatus claim having similar limitations as apparatus claim 11. Thus, it is rejected for the same reasons.
Allowable Subject Matter
Claims 3-6 and 13-15 would be allowable if rewritten to overcome the claim objections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claims 3 and 13, , including the FFT circuit comprises: two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage; a first channel circuit configured to transform a first phase of the filtered time domain input data to a first phase of the frequency domain data; and a second channel circuit configured to transform a second phase of the filtered time domain input data to a second phase of the frequency domain data, wherein at each stage, the first channel circuit and the second channel share the butterfly circuit associated with that stage.
Scott – US 20200036398 teaches a dynamic reconfigurable channelizer having an adaptive polyphase filter 120 to filter time domain digital signal and output the filtered data to an FFT 122 to transform the filtered time domain data to frequency domain data. Figure 3 illustrates a multi-stage FFT having at least 2 stage that is serially cascaded, wherein each stage perform butterfly operation. However, the output of the adaptive filter 120 does not split into first and second phase to be transformed by the first and second transform circuit to generate first and second phases of the frequency domain data, wherein at each stage, the first and second channel circuits share the butterfly circuit associated with that stage. Furthermore, Scott does not teach or suggest two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage.
Brede – US 20020098795 teaches a receiver having ADC, polyphase filter, and FFT circuit as illustrated in figure 31, wherein each polyphase filter branch includes 5 taps, and figure 70 describes the FFT to have various sizes that can be selected. However, Brede does not teach or suggest the FFT circuit comprises: two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage; a first channel circuit configured to transform a first phase of the filtered time domain input data to a first phase of the frequency domain data; and a second channel circuit configured to transform a second phase of the filtered time domain input data to a second phase of the frequency domain data, wherein at each stage, the first channel circuit and the second channel share the butterfly circuit associated with that stage.
Thompson – US 20190104002 teaches a frequency channelizer including FIR filter and FFT circuit to generate frequency domain data, wherein the FIR filter is an adaptive polyphase filter that can dynamically update filter coefficients. However, Thompson does not teach or suggest splitting the filtered time domain output of the FIR filter into first and second phase and also does not teach or suggest the implementation of the FFT circuit as required in claims 5 and 13.
Shibayama – US 20160224093 teaches a digital filtering device having a data rearranging circuit, a series of cascaded FFT circuits to perform data transformation. However, Shibayama does not teach or suggest the configuration of a dynamic reconfigurable channelizer having a polyphase filter, FFT circuit, first channel circuit, and second channel circuit to transform first and second filtered time domain data, wherein the FFT circuit comprises two or more serially cascaded processing stages, each stage comprising a butterfly circuit configured to compute an N-point FFT butterfly, where N increases by a factor of two for each stage as required in claims 3 and 13.
Song – US 20230336161 teaches a sub-band channelizer for randomly-spaced frequency groups, wherein figure 4 illustrates a polyphase filter having a plurality of branches 402a-402b, wherein each row of 402 includes N taps and each of the N taps 404 may be associated with a different coefficient. As illustrated in figure 4, k number of frequency bins are generated using K point FFT. However, Song does not teach or suggest that the number of frequency bins, coefficient filter, or number of folds by dynamically programmable, and also does not illustrate implementation of FFT circuit as required in claims 3 and 13.
Harris – US 8958510 teaches a channelizer in figure 1, wherein the channelizer is configured to generate M channels at a rate equal to two times the channel spacing, wherein the channel spacing is Fs/M, where Fs corresponds to input sampling rate, M corresponds to the number of bins. Thus, the channelizer output frequency domain data at a rate of 2Fs/M. However, Harris does not teach or suggest that the number of frequency bins, coefficient filter, or number of folds by dynamically programmable, and also does not illustrate implementation of FFT circuit as required in claims 3 and 13.
Therefore, the prior art of record fails to teach or suggest a combination of limitations as claimed in claims 3 and 13. Accordingly, Claims 3-6 and 13-15 would be allowable if rewritten to overcome the claim objections, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182