DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under pre-AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 8-15, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “an input buffer configured to buffer a first group of samples of the input data provided on a first clock cycle and provide the buffered first group of samples, along with a second group of samples of the input data provided on a second clock cycle, to the multiplexer circuit”. It is unclear what is meant by providing the buffered first group of samples, along with a second group of samples … to the multiplexer circuit. It is unclear whether along with means “in addition to” or “together with” as in at the same time. See Merriam-Webster definition of “along with” at https://www.merriam-webster.com/dictionary/along%20with. Claim 10, and claim 18 recite substantially the same limitation and are rejected for the same reason. For purposes of examination, Examiner interprets as “in addition to”.
Claim 8 line 3 recites “the channelizer output”. This limitation lacks antecedent basis. It is unclear whether this limitation recites an output of the reconfigurable channelizer recited in the preamble of an output of a different channelizer. Claims 9-15 inherit the same deficiency as claim 8 based on dependence. For purposes of examination, Examiner interprets as an output of the reconfigurable channelizer.
Allowable Subject Matter
Claims 1-2, 4-7, 16-17, and 19-20 are allowed. Claims 3, 8-15, and 18 would be allowable if rewritten to overcome the rejections under 35 USC 112(b).
The following is a statement of reasons for indication of allowed subject matter. The apparatus as in claim 1, a polyphase filter circuit comprises:
a first plurality of dual port memory circuits;
a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits;
a second plurality of dual port memory circuits configured to store polyphase filter coefficients;
a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits;
a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients; and
an adder circuit to sum the results of the multiplications to generate a filtered output.
The prior art of record considered individually and in combination, fail to teach or suggest the above highlighted limitations in combination with the remaining limitations.
US 5594675 Peng (hereinafter “Peng”) discloses a digital FIR filter comprising a polyphase interpolator (abstract, col 1 line 25-32, col 4 line 65-67, fig 3, fig 7). Peng further discloses a RAM for receiving and storing input samples and a ROM for storing coefficient values for each bank filter term (col 9 line 60-61, col 10 line 28-31). Peng further discloses a multiplier to perform multiplications input data with filter coefficients, and an adder to sum results of the multiplications (fig 7 640, 644, col 10 line 41-col 11 line 3). Peng further discloses aligning the coefficient and input data (fig 7 620, col 10 line 8-22). Peng does not, however, teach or suggest a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits; or a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. Furthermore Peng does not teach or suggest wherein the ROM and the RAM comprise dual port memory circuits.
US 20060285019 A1 Matschullat (hereinafter “Matschullat”) discloses a digital filter including a polyphase filter wherein filter coefficients are calculated in real time (abstract, [0016]). Matschullat further discloses wherein the polyphase filter includes a ROM and RAM memory for storing filter coefficients (fig 1-4,5, [0018-0020]). Matschullat further discloses multiplier circuitry to multiply the input data by the filter coefficient, and adder circuitry to sum the results of the multiplications (fig 1-11:16,17 [0023]). Matschullat further discloses a unit for selection of the phase associated with the assigned coefficient, and a unit for reconstruction of coefficients based on offset, and phase ([0020], fig 1-6,7), but does not teach or suggest a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits; or a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. Furthermore Matschullat does not teach or suggest disclose wherein the ROM and the RAM comprise dual port memory circuits.
P. Vallance, Channelization using RFN0C, Proceedings of the 7th GNU Radio Conference, (GRCON 2017), 2017, (hereinafter “Vallance”), discloses an FPGA implementation of a channelizer including a polyphase filter (fig 7, fig 9). Vallance further discloses a multiplexer to mux the write enable input values to the Dual Port RAM (fig 9, fig 8 input multiplexer, section 2.1).Vallance further discloses a plurality of dual port memory circuits storing input data (fig 10). Vallance further discloses a plurality of ROM for storing coefficient data (fig 9 single port RPM). Vallance further discloses a multiply circuit configured to perform multiplications of the input data with the filter coefficients, and a adder to sum results of the multiplications (fig 9 multipliers, adder). Vallance does not, however, teach or suggest a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. Furthermore Peng does not teach or suggest wherein the ROM comprise dual port memory circuits.
S.A. Fahmy et al., Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing, LNCS 5992, ARC 2010, p. 343-350, 2010, (hereinafter “Fahmy”) discloses implementing filter backs on FPGAs for spectrum sensing using subband filters with parameters changed at runtime using a polyphase FIR filter (abstract, fig 2, fig 3, section 2, section 3). Fahmy further discloses loading coefficients into a plurality of dual port memories, a second plurality of dual port memories storing intermediate states, and a plurality of MAC units for multiplication and addition (fig 4, section 4.2). Fahmy does not, however teach or suggest a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits; or a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Andrew Caldwell can be reached on 571-272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILY E LAROCQUE/ Primary Examiner, Art Unit 2182