DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Authorization for Internet Communications submitted 3/16/2026 on page 3 of Remarks must be submitted as a separate paper as required by 37 CFR 1.4(c). See MPEP 502.03(II). Therefore, the authorization for internet communications is currently not effective.
Response to Arguments
Claim Rejections – 35 USC 112
Applicant asserts claims 10-13 have been amended to correct antecedent basis errors in page 1 of Remarks, however the submitted claims 10-13 have not been amended. Therefore, the rejections are maintained.
Applicant asserts whether the multi-stage FFT circuit is internal or external to a sample reorder circuit has no material impact on how a person skilled in the art would interpret the scope of claim 1, and that a person skilled in the art would view “to” as an output interface to a separate FFT block that may be internal or external to a sample reorder circuit. Examiner respectfully disagrees. The lack of clarity is whether the multi-stage FFT circuit is a structural element of the claimed invention, and not one of whether one of ordinary skill in the art would understand the limitation as describing an output interface. In other words, it is not clear that the scope of the claimed invention only covers the positively recited elements, or that the scope of the claimed invention also requires the multi-stage FFT circuit for consideration of what constitutes infringement of the claimed invention. Specifically, the question is whether claim 1 is only an FFT sample reorder circuit, or a system comprising an FFT sample reorder circuit and a multi-stage FFT circuit.
Prior Art Rejections
Applicant’s arguments, filed 3/16/2026, with respect to 35 U.S.C 103 of claim 1 have been fully considered.
Applicant’s assertions with respect to Li is persuasive. However, Applicant has not addressed all prior art in the combination of the 35 U.S.C. 103 rejection. Szedo and Koehn also do not teach a controller routing reordered output data samples based on a selection of a stage of the multi-stage FFT circuit. Thus, the prior art of record does not teach claim 1.
Applicant asserts claim 8 includes similar controller-based features as claim 1. Examiner respectfully disagrees. The controller-based features of Applicant’s arguments are not present in claim 8, but are present in claim 9. Applicant has not addressed the prior art rejections in regards to the limitations of claim 8. Thus, the rejections of claim 8 are maintained. Furthermore, the rejections of claims 12-13 and 15-16 are maintained.
Therefore, the prior art rejections for claims 1-7, 9-11, 14, 17-20 have been withdrawn, while the prior art rejections of claims 8, 12-13, 15-16 are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 10-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation " multi-stage FFT circuit". It is unclear whether the “multi-stage FFT circuit” is a component within the claimed sample reorder circuit or external to the sample reorder circuit, i.e., it is not clear whether or not the “multi-stage FFT circuit” is a positively recited structural element of the claim.
Claims 10-13 recites the limitations "the controller circuit", “the first crossbar circuit”, “the second crossbar circuit”, and/or “the plurality of dual port memory circuits”. There is insufficient antecedent basis for the limitations in the claims. The parent claims do not declare the above limitations, however claim 9 does declare the above limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8, 12-13, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Szedo et al. (US 8572148 B1, hereinafter “Szedo”) in view of Li et al. (A 128/256-Point Pipeline FFT/IFFT Processor for MIMO OFDM System IEEE 802.16e, hereinafter “Li”) in further view of Koehn et al. (Data staging for efficient high throughput stream processing, hereinafter “Koehn”).
As per claim 8, Szedo teaches a sample reorder circuit configured to reorder samples of the time domain input data based on a selection of a stage of the multi-stage FFT circuit (Szedo: Fig. 2 element 200;).
However, while Szedo discloses reordering data for FFT processing, Szedo does not explicitly disclose specific details of the FFT processing. Thus, Szedo does not teach A reconfigurable channelizer comprising: a multi-stage fast Fourier transform (FFT) circuit configured to transform time domain input data to output frequency domain data distributed into frequency bins, wherein a number of the frequency bins is dynamically programmable;
Li teaches A reconfigurable channelizer comprising: a multi-stage fast Fourier transform (FFT) circuit configured to transform time domain input data to output frequency domain data distributed into frequency bins, wherein a number of the frequency bins is dynamically programmable (Li: section III.A; wherein the FFT circuit can process 128-point or 256-point);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the FFt circuit of Szedo (Fig. 5B element 501B) with the FFT circuit of Li. One would have been motivated to combine these references because both references disclose FFT processing with reordering, and combining prior art elements according to known methods to yield predictable results (an FFT processing circuit design).
As per claim 15, Szedo/Li further teaches The channelizer of claim 8, wherein the number of frequency bins is dynamically programmable to one of 128, or 256 (Li: abstract).
As per claim 16, Szedo/Li further teaches The channelizer of claim 8, wherein the channelizer is implemented in an application specific integrated circuit or a field programmable gate array (Szedo: col 6 lines 21-26).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Szedo/Li in view of Koehn et al. (Data staging for efficient high throughput stream processing, hereinafter “Koehn”).
As per claim 12, Szedo/Li teaches teaches The channelizer of claim 8,
However, while Szedo discloses reordering data for FFT processing, Szedo does not explicitly disclose specific details of the FFT processing. Thus, Szedo/Li does not teach wherein each dual port memory circuit of the plurality of dual port memory circuits comprise one read address port and one write address port
Koehn teaches wherein each dual port memory circuit of the plurality of dual port memory circuits comprise one read address port and one write address port (Koehn: Fig. 2 elements A.sub.I and A.sub.O; pg 4 left col second paragraph last sentence).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to modify, with a reasonable expectation of success, the select signals of Szedo (Fig. 2 elements 221, 222) with the radix mode control signal of Li. One would have been motivated to combine these references because both references disclose reordering data prior to FFT processing, and combining prior art elements according to known methods to yield predictable results (determining select signal values based on FFT circuit design).
As per claim 13, Szedo/Koehn/Li further teaches The channelizer of claim 8, wherein the controller circuit is configured to control the routing of the input data samples and the routing of the reordered output data samples so that the read address port and the write address port of each dual port memory circuit of the plurality of dual port memory circuits are utilized for memory access no more than once in a clock cycle (Koehn: pg 4 left col third and fourth paragraphs).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHAT N LE whose telephone number is (571)272-0546. The examiner can normally be reached Monday-Friday 8:30AM-5PM ET.
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/P.N.L./
Phat LeExaminer, Art Unit 2182 (571) 272-0546
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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