Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (PG Pub 2001/0038099 A1), Chang et al (PG Pub 2019/0148215 A1), Paek et al (PG Pub 2013/0256781 A1), Kato et al (PG Pub 2011/0114941 A1), and Saito (PG Pub 2012/0231589 A1).
Regarding claim 5, Yamazaki in view of Chang, Paek, Kato and Saito (see previous rejection of claim 1) teaches a method of fabricating an integrated circuit, the method comprising: forming a first transistor structure and a second transistor structure, the second transistor structure spaced from a first transistor structure by a gap no greater than 100 nm, wherein the first transistor structure and the second transistor structure each include a body of semiconductor material having a channel region therein, a layer of dielectric material, and a gate electrode beneath and vertically aligned with the layer of semiconductor material, and spaced from the layer of semiconductor material by the layer of dielectric material; and depositing a layer of isolation material (190, fig. 1C of Paek, paragraph [0043]) in the gap, thereby encapsulating a gas pocket laterally between the first transistor structure and the second transistor structure, wherein at least a portion of the gas pocket is laterally spaced apart from the gate electrodes of the first transistor and the second transistor, and wherein the gas pocket is laterally spaced apart from the channel regions of the bodies of semiconductor material of the first transistor and the second transistor; and wherein the layer of isolation material is in direct contact with each of the channel region, the source region, and the drain region of each of the first transistor and the second transistor; and forming a source electrode and a drain electrode, wherein the drain electrode and the source electrode are on a side of the body of semiconductor material opposite the gate electrode.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al (PG Pub 2001/0038099 A1), Chang et al (PG Pub 2019/0148215 A1), Paek et al (PG Pub 2013/0256781 A1), Kato et al (PG Pub 2011/0114941 A1), and Saito (PG Pub 2012/0231589 A1) as applied to claim 5 above, and further in view of Kautzsch et al (PG Pub 2015/0163915 A1).
Regarding claim 6, the previous combination remains as applied in claim 5.
The previous combination does not teach depositing the layer of insulator material is performed at least in part by atomic layer deposition or physical vapor deposition.
In the same field of endeavor, Kautzsch teaches depositing the layer of insulator material is performed at least in part by atomic layer deposition for the benefit of depositing a conformal layer in a trench even high aspect ratio (paragraph [0033]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to deposit the layer of insulator material at least in part by atomic layer deposition or physical vapor deposition, for the benefit of depositing a conformal layer in a trench even with the trench having high aspect ratio.
Allowable Subject Matter
Claims 1-4 and 7-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“an isolation material at least partially encapsulating a gas pocket between adjacent transistor structures in the array… and wherein the isolation material is in direct contact with each of the channel region, the source region, the drain region, the gate electrode, and the gate dielectric of each of the adjacent transistors” (claims 1 and 7).
Response to Arguments
Applicant’s arguments with respect to claim(s) 5 and 6 have been considered but are not persuasive because the allowable features are not in claim 5.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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