DETAILED ACTION
This Office Action is in response to the Request for Continued Examination filed on 19 August 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 August 2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 8, and 10-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bower et al. (US 2017/0287789 A1; previously made of record; cited in the prior Office Action dated 23 December 2025; hereinafter Bower).
In regards to claim 1, Bower teaches a hybrid-control pixel, comprising:
a TFT substrate (20) ([0005], [0113]);
a TFT circuit ([0113]: e.g. (20) is a PCB) formed on or in the TFT substrate;
a micro-device (e.g. (10) or (12)) [0120] comprising a micro-circuit (fig. 15: e.g. circuit portion (83/84) of circuit device element (80)) formed on or in a semiconductor integrated-circuit substrate ([0145]: (10) includes semiconductor devices including semiconductor layers such as an integrated circuit, e.g. a semiconductor substrate), wherein the semiconductor integrated-circuit substrate is non-native to the TFT substrate (fig. 2: e.g. (10) is a distinct element from (20)) and the micro-circuit is electrically connected to the TFT circuit ([0114]; fig. 2: (80) is connected to (20) by (16)); and
an LED (81) [0121] separate from the micro-device (e.g. fig. 15: (81) in (10) is a discreet element separate from (12)), wherein the LED is electrically connected (e.g. by (83)) [0121] to the micro-circuit or to the TFT circuit (fig. 15: (81) is electrically connected to (83/84)),
wherein the TFT circuit and the micro-circuit are together operable to control the LED [0114].
In regards to claim 4, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the LED is an OLED [0124].
In regards to claim 5, Bower teaches the limitations discussed above in addressing claim 4. Bower further teaches the limitations wherein the OLED is native to (e.g. formed on) the micro-device [0124].
In regards to claim 8, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the LED (81) is an iLED ([0121]; fig. 15).
In regards to claim 10, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the LED (81) [0121] comprises one or more connection posts (83) [0121] electrically connected to the micro-circuit ([0120]; fig. 2: (10)).
In regards to claim 11, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-device (10) [0120] comprises one or more connection posts (16) [0114] electrically connected to the TFT circuit ([0113]; fig. 2: (20)).
In regards to claim 12, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the TFT circuit comprises signal selection circuitry [0127].
In regards to claim 13, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-circuit comprises LED driving circuitry [0114].
In regards to claim 14, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the TFT circuit comprises a thin-film capacitor and the micro-circuit is responsive to the thin-film capacitor [0069].
In regards to claim 15, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-circuit is responsive to a voltage provided by the TFT circuit [0114].
In regards to claim 16, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-circuit comprises a storage device and the storage device stores a value corresponding to a value provided by the TFT circuit ([0069]: e.g. capacitor).
In regards to claim 17, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein (i) the micro-device comprises a micro-device tether, (ii) the LED comprises an LED tether, or both (i) and (ii) [0090].
In regards to claim 18, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-device (10) is disposed on (e.g. over) the TFT substrate (20) (fig. 2).
In regards to claim 19, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the TFT circuit comprises circuitry formed in one or more of: amorphous silicon (aSi), low-temperature polycrystalline silicon (LTPS), high-temperature polycrystalline silicon (HTPS) [0147], and indium-gallium-zinc-oxide (IGZO).
In regards to claim 20, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the TFT circuit comprises (i) circuitry formed in low-temperature polycrystalline silicon (LTPS) [0147], (ii) circuitry formed in indium-gallium-zinc-oxide (IGZO), or (iii) both (i) and (ii).
In regards to claim 57, Bower teaches the limitations discussed above in addressing claim 1. Bower further teaches the limitations wherein the micro-circuit comprises a transistor ([0114]: (80) includes transistors).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bower as applied to claim 1 above, in view of Bower et al. (US 2016/0093600 A1; previously made of record; cited in the prior Office Action dated 23 December 2025; hereinafter Bower’600).
In regards to claim 2, Bower teaches the limitations discussed above in addressing claim 1. Bower appears to be silent as to, but does not preclude, the limitations comprising three different LEDs disposed on the micro-device. Bower’600 teaches the limitations comprising three different LEDs disposed on the micro-device [0118]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Bower with the aforementioned limitations taught by Bower’600 such that three LEDs are disposed on the micro-device to have a resulting system that has a homogeneous appearance resembling a monolithic system (Bower’600 [0118]).
In regards to claim 3, the combination of Bower and Bower’600 teaches the limitations discussed above in addressing claim 2. Bower’600 further teaches the limitations wherein the three different LEDs comprise a red LED operable to emit red light, a green LED operable to emit green light, and a blue LED operable to emit blue light [0118]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Bower with the aforementioned limitations taught by Bower’600 such that three LEDs are disposed on the micro-device to have a resulting system that has a homogeneous appearance resembling a monolithic system (Bower’600 [0118]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 8, 10-20, and 57 have been considered but are moot because the new ground of rejection does not rely on the references as applied in the prior rejection of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
Prosecution Insights