Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments / Arguments
Regarding the rejection(s) of claims under 35 USC 103:
Applicant’s arguments, filed on 10/29/2025, in view of the amended claims, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Coulon et al. (US 20240012886 A1, referred to as Coulon), in view of Abadi et al. (US 20060161978 A1, referred to as Abadi)
DETAILED ACTION
This is a reply to the arguments filed on 10/29/2025, in which, claims 1-20 are pending. Claims 1, 9, and 15 are independent.
When making claim amendments, the applicant is encouraged to consider the references in their entireties, including those portions that have not been cited by the examiner and their equivalents as they may most broadly and appropriately apply to any particular anticipated claim amendments.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Coulon et al. (US 20240012886 A1, referred to as Coulon), in view of Abadi et al. (US 20060161978 A1, referred to as Abadi)
In reference to claim 1 . A method comprising: at a device including one or more memory units for storing one or more of instructions corresponding to compiled source codes and modified codes, and an extended compiler unit (Coulon: [0062]-[0064] Provides for a system with memory units for storing both original program instructions and modified (ciphered) codes.)
scanning the compiled source codes to construct a table including addresses of the instructions in the compiled source codes (Coulon: [0074]-[0075] Provides for scanning the compiled code to identify instruction addresses, particularly those containing control flow instructions, and creating a table (instruction flow signature memory FSM) that includes these addresses.)
indicating in the table a set of code addresses corresponding to a set of instructions among the instructions that is accessible from more than one address (Coulon: [0024]-[0026] Provides for identifying and storing addresses of branch targets in the instruction flow signature memory. These branch targets are precisely the instructions that are accessible from more than one address, as they can be reached through normal sequential execution or through branches.)
generating the modified codes from the instructions according to the table using a function, including, determining whether or not an instruction is a first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for determining whether an instruction is the first executed instruction of a function and using special handling for such instructions by resetting the calculation of the instruction flow signature..)
For each of the instructions that is not the first executed instruction and not in the set of instructions, generating the modified codes by applying the function to a current instruction and an instruction preceding the current instruction (Coulon: [0018]-[0019] and [0085]-[0090] Provides for applying a chaining function to generate modified codes for normal sequential instructions, where each instruction's signature depends on the previous instruction's signature.)
storing the modified codes in the one or more memory units (Coulon: [0063] Provides for the modified (ciphered) codes are stored in the system memory.)
Coulon does not explicitly disclose for a respective instruction in the set of instructions, injecting before the respective instruction a reset instruction to each address in the set of code addresses, and applying the function to the reset instruction and the respective instruction and wherein the reset instruction has a fixed value and is not modified during compilation
for a respective instruction in the set of instructions, injecting before the respective instruction a reset instruction to each address in the set of code addresses, and applying the function to the reset instruction and the respective instruction (Abadie: Fig.4A-4B, [0030]-[0036] and [0041]-[0042] Provides for inserting IDs as data/prefetch instructions (that don't affect execution) before destination instructions, particularly at the start of equivalent destinations (multi-access points). These IDs serve the same purpose as the claimed "reset instruction" - they're markers that maintain security without adding significant runtime overhead.)
Wherein the reset instruction has a fixed value and is not modified during compilation (Abadi: [0032]-[0036] and [0041]-0042] Provides for using fixed ID values that are chosen arbitrarily or randomly and inserted as constants. The document specifically mentions "ID constants" and describes them as 32-bit values that remain fixed.)
*It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Coulon, which provides a method for scanning compiled code to identify multi-access instructions, constructing address tables, and generating modified codes using chaining functions that depend on instruction execution order, with the teachings of Abadie, which introduces inserting fixed-value reset instructions (ID markers) before multi-access destination instructions to maintain security without affecting execution. One of ordinary skill in the art would recognize the ability to incorporate Abadie's reset instruction injection technique into Coulon's code modification system to enhance security at multi-entry points. One of ordinary skill in the art would be motivated to make this modification in order to provide explicit security markers at instructions accessible from multiple addresses.
In reference to claim 4, The method of claim 1, wherein the function is a symmetric encryption function (Coulon: [0009]-[0015] Provides for using ciphering and deciphering functions for the instructions.)
In reference to claim 5, The method of claim 1, wherein generating the modified codes from the instructions according to the table using the function includes: generating a second modified code corresponding to a second instruction by applying the function to the second instruction and a first instruction (Coulon: [0018]-[0019] and [0085]-[0091] Provides for a process where each instruction's modification (ciphering) depends on both the instruction itself and the previous instruction's signature.)
In reference to claim 6, The method of claim 1, wherein generating the modified codes from the instructions according to the table using the function includes; generating a modified code corresponding to the instruction by applying the function to the instruction and a pre-defined first instruction value in accordance with determining the instruction is the first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for a process for handling first executed instructions (particularly at function entry points).)
In reference to claim 7, The method of claim 1, wherein generating the modified codes from the instructions using the function includes: determining whether or not a respective modified code corresponding to a respective instruction has a same value as the reset instruction; and modifying the respective modified code to a different code in accordance with determining the respective modified code has the same value as the reset instruction (Abadi: [0036]-[0042] Provides for ensuring that the IDs (reset instructions) don't conflict with existing code.)
In reference to claim 8, The method of claim 1, wherein generating the modified codes from the instructions according to the table using the function includes: adding a key to the function when applying the function to the reset instruction and the respective instruction (Coulon: [0020]-[0023] and [0099]-[0100] Provides for using additional values in the function that are specific to the execution system.)
In reference to claim 9, A method comprising: at a device including a memory unit for storing modified codes and a processor: loading the modified codes, wherein the modified codes are generated from instructions according to a table using a function (Coulon: [0062]-[0065] Provides for a system with a processor (CPU) and memory unit that stores modified (ciphered) codes.)
Determining whether or not an instruction is a first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for determining whether an instruction is the first executed instruction of a function and using special handling for such instructions by resetting the calculation of the instruction flow signature..)
For each of the instructions that is not the first executed instruction and not in the set of instructions, generating the modified codes by applying the function to a current instruction and an instruction preceding the current instruction (Coulon: [0018]-[0019] and [0085]-[0090] Provides for applying a chaining function to generate modified codes for normal sequential instructions, where each instruction's signature depends on the previous instruction's signature.)
for a respective instruction in the set of instructions, injecting before the respective instruction a reset instruction to each address in the set of code addresses, and applying the function to the reset instruction and the respective instruction (Abadie: Fig.4A-4B, [0030]-[0036] and [0041]-[0042] Provides for inserting IDs as data/prefetch instructions (that don't affect execution) before destination instructions, particularly at the start of equivalent destinations (multi-access points). These IDs serve the same purpose as the claimed "reset instruction" - they're markers that maintain security without adding significant runtime overhead.)
obtaining extracted instructions from the modified codes by applying a reverse function of the function to the modified codes, including forgoing applying the reverse function to the reset instruction at each address in the set of code addresses (Coulon: [0084]-[0086] Provides for applying a reverse function (deciphering) to extract the original instructions from the modified codes before execution.)
executing the extracted instructions (Coulon: [0086] Provides for the extracted (deciphered) instructions are sent to the CPU for execution.)
In reference to claim 10, The method of claim 9, wherein the modified codes are generated by generating a second modified code corresponding to a second instruction, including applying the function to the second instruction and a first instruction (Coulon: [0018]-[0019] and [0085]-[0091] Provides for a process where each instruction's modification (ciphering) depends on both the instruction itself and the previous instruction's signature.)
In reference to claim 11, The method of claim 10, wherein obtaining the extracted instruction from the modified codes includes obtaining the second instruction, including applying the reverse function to the second modified code and the first instruction (Coulon: [0084]-[0086] Provides for applying a reverse function (deciphering) to extract the original instructions from the modified codes before execution.)
In reference to claim 12, The method of claim 9, wherein the modified codes are generated by: generating a modified code corresponding to the instruction by applying the function to the instruction and a pre-defined first instruction value in accordance with determining the instruction is the first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for a process for handling first executed instructions (particularly at function entry points).)
In reference to claim 13, The method of claim 12, wherein obtaining the extracted instructions includes: obtaining the instruction by applying the reverse function to the modified code and the pre-defined first instruction value (Coulon: [0099]-[0100] and [0116] Provides for a process for handling first executed instructions (particularly at function entry points).)
In reference to claim 14, The method of claim 9, further comprising: performing a validity check when extracting a respective extracted instruction; and generating an exception upon determining the respective extracted instruction is invalid (Coulon: [0112]-[0113] Provides for performing a validity check on extracted (deciphered) instructions and raising an alarm (generating an exception) when an invalid instruction is detected.)
In reference to claim 15, A system comprising: a first device including an extended compiler unit, one or more memory units for storing one or more of instructions corresponding to compiled source codes and modified codes, and one or more first programs, stored in the one or more memory units, which, when executed by the extended compiler unit, cause the first device to: scan the instructions to identify a set of code addresses in the one or more memory units that is accessible from more than one address (Coulon: [0062]-[0065] Provides for a system with a processor (CPU) and memory unit that stores modified (ciphered) codes.)
Determining whether or not an instruction is a first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for determining whether an instruction is the first executed instruction of a function and using special handling for such instructions by resetting the calculation of the instruction flow signature..)
For each of the instructions that is not the first executed instruction and not in the set of instructions, generating the modified codes by applying the function to a current instruction and an instruction preceding the current instruction (Coulon: [0018]-[0019] and [0085]-[0090] Provides for applying a chaining function to generate modified codes for normal sequential instructions, where each instruction's signature depends on the previous instruction's signature.)
for a respective instruction in the set of instructions, injecting before the respective instruction a reset instruction to each address in the set of code addresses, and applying the function to the reset instruction and the respective instruction (Abadie: Fig.4A-4B, [0030]-[0036] and [0041]-[0042] Provides for inserting IDs as data/prefetch instructions (that don't affect execution) before destination instructions, particularly at the start of equivalent destinations (multi-access points). These IDs serve the same purpose as the claimed "reset instruction" - they're markers that maintain security without adding significant runtime overhead.)
obtaining extracted instructions from the modified codes by applying a reverse function of the function to the modified codes, including forgoing applying the reverse function to the reset instruction at each address in the set of code addresses (Coulon: [0084]-[0086] Provides for applying a reverse function (deciphering) to extract the original instructions from the modified codes before execution.)
executing the extracted instructions (Coulon: [0086] Provides for the extracted (deciphered) instructions are sent to the CPU for execution.)
In reference to claim 16, The system of claim 15, wherein the function is a symmetric encryption function (Coulon: [0009]-[0015] Provides for using ciphering and deciphering functions for the instructions.)
In reference to claim 17, The system of claim 15, wherein the modified codes are generated by generating a second modified code corresponding to a second instruction, including applying the function to the second instruction and a first instruction (Coulon: [0018]-[0019] and [0085]-[0091] Provides for a process where each instruction's modification (ciphering) depends on both the instruction itself and the previous instruction's signature.)
In reference to claim 18, The system of claim 17, wherein obtaining the extracted instruction from the modified codes includes obtaining the second instruction, including applying the reverse function to the second modified code and the first instruction (Coulon: [0084]-[0086] Provides for applying a reverse function (deciphering) to extract the original instructions from the modified codes before execution.)
In reference to claim 19, The system of claim 15, wherein the modified codes are generated by: generating a modified code corresponding to the instruction by applying the function to the instruction and a pre-defined first instruction value in accordance with determining the instruction is the first executed instruction (Coulon: [0099]-[0100] and [0116] Provides for a process for handling first executed instructions (particularly at function entry points).)
In reference to claim 20, The system of claim 19, wherein obtaining the extracted instructions includes: obtaining the instruction by applying the reverse function to the modified code and the pre-defined first instruction value (Coulon: [0099]-[0100] and [0116] Provides for a process for handling first executed instructions (particularly at function entry points).)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable by Coulon et al. (US 20240012886 A1, referred to as Coulon), in view of Abadi et al. (US 20060161978 A1, referred to as Abadi) in further view of Niu et al. (“PLDI '14: Proceedings of the 35th ACM SIGPLAN Conference on Programming Language Design and Implementation”, referred to as Niu).
In reference to claim 2, Coulon in view of Abadi discloses the method of claim 1,this process involves generating modified codes from the instructions, including injecting a reset instruction to each address in the set, and storing the modified codes in the memory units
Coulon in view of Abadi do not explicitly disclose the method of constructing a table including instruction addresses of the instructions, adding to the table code addresses with an indicator for multi-access, and adding a pre-defined prefix to each of the code addresses. However, Niu discloses:
The method of claim 1, wherein indicating in the table the set of code addresses corresponding to the set of instructions among the instruction that is accessible from more than one address includes: adding to the table destination addresses referenced by branch instructions identified in the instructions, associating each of the destination addresses with an indicator indicating multi-access and being part of the set of code addresses; and adding a pre-defined prefix to each of the set of code addresses according to the table. (Niu: MCFI Section 5.1 (ID Tables) provides for constructing tables (Bary and Tary) that map addresses to IDs, which parallels constructing a table of instruction addresses. The use of reserved bits in IDs for validity checks aligns with the concept of an indicator indicating multi-access.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Coulon in view of Abadi, which involve scanning for control-affecting instructions accessible from multiple addresses, with the teachings of Niu, which include detailed methods of constructing tables to manage instruction addresses and their access properties. One of ordinary skill in the art would recognize the ability to integrate Niu’s structured approach to managing address mappings and access indicators into Coulon-Abadi’s framework for scanning and modifying instructions. One of ordinary skill in the art would be motivated to make this modification to enhance the precision and efficiency of identifying multi-accessible addresses, thereby improving the security and functionality of the compiled and modified codes.
In reference to claim 3, The method of claim 2, wherein associating each of the destination addresses, with the indicator indicating multi-access and being part of the set of code addresses includes: determining whether or not a respective code address is in the table; and updating the indicator for the respective code address indicating the respective code address is associated with multi-access and being part of the set of code addresses in accordance with a determination of the respective code address in the table (Niu: MCFI Section 5.2 (Table Transactions) provides for updating the Tary table based on new CFG information, which involves checking and updating entries for code addresses. The description aligns with determining whether a code address is in the table and updating indicators for multi-access.)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Applicant’s amendment necessitated the new ground(s) of rejection presented in this office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN EDWARD SHAUGHNESSY whose telephone number is (703)756-1423. The examiner can normally be reached on Monday-Friday from 7:30am to 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Nickerson, can be reached at telephone number (469) 295-9235. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.E.S./Examiner, Art Unit 2432
/SYED A ZAIDI/Primary Examiner, Art Unit 2432