DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 April 2026 has been entered.
Response to Arguments
The Examiner acknowledges Applicant’s amendments and remarks filed on 9 April 2026. They have been fully considered but they are not persuasive. Applicant’s amendments have necessitated a reinstatement of the previously withdrawn rejection under 35 U.S.C. 101. Claims 1 and 8 have removed the step of causing functional blocks to utilize excess power to reach respective higher performance and power states. This step was previously added after the Office Action mailed on 12 August 2025 to overcome the rejection based on 101 set forth in that action. The removal of that step has therefore necessitated a reinstatement of that rejection. Additionally, the amendments have also necessitated new grounds of rejection based on 35 U.S.C. 112(a) and 112(b), and also based on newly found prior art.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-8, and 10-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1 recites a method comprising the steps of determining allocations of respective portions of power based on a data center energy storage level, and determining respective higher power operational states. These steps comprise a process that can be performed entirely in the human mind. The broadest reasonable interpretation (BRI) “determining allocations” includes designations of power quantities into abstract categories that can be performed in the human mind. The BRI of “determining” higher power states also includes designations and decisions that may be performed in the human mind. More specifically, the BRI of “determining” higher performance and power states not explicitly place any of the system components into a different performance or power state. It may merely constitute an intention to do so, or a mental selection of a particular power/performance state from a plurality of states.
This judicial exception is not integrated into a practical application because the additional element of a data center in claim 1 merely provides a technological field of use, and/or uses a computer as a tool to perform the mental process. Dependent claims 3-5 merely recite additional descriptions of the data center and thereby are also directed to the field of use. Dependent claims 6 and 7 provide further limitations that describe what the quantities being manipulated by the mental process represent (i.e., that the respective portions of power are from ambient power sources that cause the data center storage level to exceed a limit), but they do not integrate the mental process into a practical application because they do not represent steps performed by the method, and also because they represent further descriptions of the technological field of use.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional limitations amount to a technological field of use and mere instructions to execute the mental process using a computer. These additional elements cannot provide an inventive concept. Therefore, claims 1 and 3-7 are not patent eligible. Claims 8 and 10-14 are rejected on the same basis.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 6, 7, 13, 14, 19, and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 6 has been amended to recite that the determining of the allocations is “based on the respective portions of power being provided from one or more ambient power sources”. The language may be interpreted as indicating that the allocation takes into account the nature of the power source when determining the allocation of power. For example, the BRI may include an embodiment wherein the invention determines whether a power source is an ambient power source, or what type of ambient power source is providing the power, and determines power allocations based on that determination. It may also be interpreted as determining that an ambient power source initiates provision of power. The specification fails to support such an interpretation. The specification does not teach that the nature of the power source or its behavior is a factor in determining allocations. The specification instead teaches that the invention determines the existence of excess power which is used to trigger allocation of power to different units of hardware [para. 0022, 0023: “FIG. 2 shows an architecture for a data center control function that causes certain hardware components within the data center to be placed in a higher performance state when the control function becomes aware that excess power exists. The higher power consumption of these components when placed in the higher performance state consumes the excess power resulting in little/no wasted power… As observed in FIG. 2, one or more aggregate power distribution units (APDUs) 201 receive information, e.g., from ‘green’ power providers, concerning the current existence of any excess ambient power, and, to the extent possible, how long such excess ambient power is expected to last.”]. That the excess power is provided from an “ambient” power source (or any other type of power source), does not appear to be a consideration in determining that there is excess power. Claims 13 and 19 are rejected on the same basis.
Claim 7 has been amended to recite that respective portions of power are based on an amount of power received by the data center from the one or more ambient power sources “causing the data center energy storage level to exceed a limit”. This language may be interpreted as indicating that the system performs a determination that the energy storage devices continue to charge beyond some unspecified level. The specification fails to teach such a determination. The specification instead teaches that when the devices are fully charged, the excess power is unused [para. 0012: “Notably, there can exist situations where the ambient power is generated at such a high rate that excess power remains after the storage devices have been fully replenished and the data center 101 is operating normally and being fed with all the power it needs. Such a situation, which can present a form of excess grid feed in, nominally results in wasted power (the excess power is not used) if the data center 101 continues to operate normally. That is, there is no additional storage capacity to store the excess power and the data center 101 is not consuming the excess power. As such, the excess power is simply lost.”], or is allocated to the computing devices to increase their performance [para. 0022: “FIG. 2 shows an architecture for a data center control function that causes certain hardware components within the data center to be placed in a higher performance state when the control function becomes aware that excess power exists.”]. The specification broadly discloses that the existence of excess power is determined, but it does not teach that this determination is based on, for example, exceeding a limit of the energy storage devices. Claims 14 and 20 are rejected on the same basis.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 12, and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “a higher power operational state for the memory system comprising main memory scrubbing or cache scrubbing”. It is unclear how this characterization of the higher power operational state for the memory system further limits the method of claim 4. The parent claims have not explicitly established that the method places the memory system in a higher power operational state. Claim 1 merely recites higher power operational states for “different units of hardware” without clearly attributing the higher power operational states to a memory system. Additionally, claim 5 recites a higher power operational state for the memory system without explicitly linking it to the determination step of the higher power operational state recited in claim 1. Consequently, it merely introduces a higher power operational state of a memory system without giving it any functional relevance to the invention. But even if this were not the case, claim 1 also merely recites that the higher power operational states are “determined”, the BRI of which may include a mental designation that does not affect any changes in the system. Given these factors, it is unclear how claim 5 further limits the steps of claim 4. It merely describes a feature of the system in which the method is executed without clearly linking the feature to a step carried out by the method. It may reasonably be interpreted as a statement of intended use (i.e., it describes a feature of the system that the method is intended to be used with) and therefore possibly non-limiting. Claims 12 and 18 are rejected on the same basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Bodas, U.S. Patent Application Publication No. 2004/0163001, in view of Chung et al., U.S. Patent Application Publication No. 2018/0275200.
Regarding claim 1, Bodas discloses a method comprising:
based, at least in part on a data center energy level [para. 0042: “In this example, because the power capacity of the rack is 6000 Watts, there is 1300 watts (6000-4700) of available power for the EPTM 250 to allocate when necessary.”], determining allocations of respective portions of power for different units of hardware within the data center [para. 0043: “The EPTM 250 may respond to the requests by dynamically allocating the available power to the computer systems 405 and 410.”]; and
determining respective higher power operational states for the different units of hardware to utilize the respective portions of power [para. 0043: “For example, the EPTM 250 may set the target power consumption level PTARGET for each of the computer systems 405 and 410 to a next higher target power consumption level and then allocate power to the computer systems 405 and 410 based on these higher PTARGETS. and the available 1300 watts. In this example, the power allocated to the computer system 405 is increased from 600 Watts to 700 Watts, and the power allocated to the computer system 410 is increased from 600 Watts to 650 Watts, as illustrated in FIG. 4B.”].
Bodas additionally teaches that a data center energy level includes power provided by utility companies and uninterruptible power supply (UPS) systems [para. 0039: “For one embodiment, the EPTM 250 may receive information that indicates status of source of electrical energy such as power from utility companies, uninterruptible power supplies (UPS) or back up generators such as generators that work on diesel engines, for example.”; para. 0051: “The data center administrators may use uninterruptible power supply (UPS) systems in case problems occur in receiving the power from the power utility companies.”]. However, Bodas does not explicitly teach a data center energy storage level.
Chung teaches a data center energy storage level [para. 0058: Referring to FIG. 1, a large-scale battery bank 100 is composed of many series-connected batteries. For example, the UPS system for the data center can have two battery banks for ensuring service contingency and continuity. Each bank can have more than 300 battery units connected in series.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Bodas and Chung by modifying Bodas to include a data center energy storage level as taught by Chung. Both Bodas and Chung are directed to power supply systems for data centers. Bodas discloses a UPS but does not explicitly disclose the composition of the UPS. Chung discloses that a UPS may be comprised of a battery storage unit. It would therefore have been obvious to one of ordinary skill in the art to determine the data center energy level as including a data center energy storage level based on Chung’s teaching that a UPS may comprise a battery storage unit (and thereby providing a data center energy storage level).
Regarding claim 3, Bodas teaches that the different units of hardware comprise a semiconductor chip within the data center [para. 0006: “The value of PMAX for such a computer system assumes that it is populated with four 2.2 GHz (max power) processors, fully utilized memory slots and I/O slots, and five hard drives.”].
Regarding claim 4, Bodas teaches that the semiconductor chip includes a memory system [para. 0006: fully utilized memory slots].
Claims 8, 10, and 11 are rejected on the same basis as claims 1, 3, and 4.
Claims 2, 9, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bodas in view of Chung as applied to claims 1 and 8 above, and further in view of Branover et al., U.S. Patent Application Publication No. 2013/0145180.
Regarding claim 2, Bodas and Chung disclose the method of claim 1. Bodas also teaches higher power operational states for the different units of hardware, but Bodas does not explicitly teach causing the different units of hardware to utilize the respective portions of power to reach the respective higher power operational states.
Branover teaches higher power operational states for different units of hardware [para. 0042, CPU TDP value: “…while the TDP value for the CPU 130 may increase from 40 watts to 50 watts.”], and causing the different units of hardware to utilize the excess power [para. 0042: “Therefore, the CPU 130 may operate at a higher clock frequency for higher performance and consume more power.”] to reach the respective higher performance and higher power operational states.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to combine the teachings of Bodas and Branover by modifying Bodas to employ higher performance and power operational states for certain functional blocks (i.e., a processor), and causing the certain functional block to utilize excess power to reach the higher performance and power operational state, as taught by Branover. Bodas and Branover are both directed to power control for computing systems. Bodas teaches determining a higher performance and higher power operational state for a computing system by increasing the number of watts allocated to the system, but does not explicitly indicate how the higher wattage is achieved. Branover discloses a step of increasing a wattage of a computing system by operating its CPU at a higher clock frequency. Branover additionally teaches that this increase would also result in higher performance. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Branover to Bodas based on Branover’s suggestion that increasing the CPU clock frequency also increases the performance.
Claims 9 and 15-17 are rejected on the same basis as claims 1-4.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bodas in view of Chung as applied to claims 4 and 11 above, and further in view of Roberts et al., U.S. Patent Application Publication No. 2016/0155491.
Regarding claim 5, Bodas and Chung disclose the method of claim 4, but do not teach that a higher power operational state for the memory system includes main memory scrubbing or cache scrubbing.
Roberts discloses a higher power operational state for a memory system including main memory scrubbing [para. 0048: “If the processor 104 and/or the computing system 100 are operating in a low power consumption state (e.g., ACPI G1), the asserted interrupt line 301 may cause the processor 104 to transition to a higher power consumption state in order to service the request to perform the memory maintenance operation. Memory maintenance operations that may be requested by the refresh control logic 311 may include, for example, memory refreshes, memory scrubbing, data migration, or other operations for maintaining data integrity and preventing data loss.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Bodas and Roberts by modifying Bodas to include a higher power operational state for the memory system that comprises memory scrubbing, as taught by Roberts. Roberts teaches that memory scrubbing operations aid in maintaining data integrity and preventing data loss [para. 0048]. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Roberts to Bodas based on this disclosed benefit. Claim 12 is rejected on the same basis.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Bodas in view of Chung in view of Branover as applied to claim 17 above, and further in view of Roberts et al., U.S. Patent Application Publication No. 2016/0155491.
Regarding claim 18, Bodas, Chung, and Branover disclose the method of claim 17, but do not teach that a higher power operational state for the memory system includes main memory scrubbing or cache scrubbing.
Roberts discloses a higher power operational state for a memory system including main memory scrubbing [para. 0048: “If the processor 104 and/or the computing system 100 are operating in a low power consumption state (e.g., ACPI G1), the asserted interrupt line 301 may cause the processor 104 to transition to a higher power consumption state in order to service the request to perform the memory maintenance operation. Memory maintenance operations that may be requested by the refresh control logic 311 may include, for example, memory refreshes, memory scrubbing, data migration, or other operations for maintaining data integrity and preventing data loss.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Bodas and Roberts by modifying Bodas to include a higher power operational state for the memory system that comprises memory scrubbing, as taught by Roberts. Roberts teaches that memory scrubbing operations aid in maintaining data integrity and preventing data loss [para. 0048]. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Roberts to Bodas based on this disclosed benefit.
Conclusion
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
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