DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 08/11/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 08/11/2026 in reply to the final rejection mailed on 06/11/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. According, pending in this Office action are Claims 1-5 & 7-25
Claim Rejections – 35 USC 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, & 7-24 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin (US 20210050300).
Regarding Claim 1, Lin (see, e.g., fig. 36a, fig. 39, fig. 41a, para.0681, para.0684) an apparatus comprising:
a substrate 79, 92, & 101 with a first side (top surface of layer 79) and a second side opposite the first side;
a plurality of electrical contacts 27 on the first side of the substrate;
and an electrical conductor 583 on the first side of the substrate
and extending from a surface of the first side of the substrate,
the electrical conductor electrically coupled with at least one of the plurality of electrical contacts.
a plurality of solder balls 563 (see, e.g., para.0715),
wherein individual ones of the plurality of solder balls are coupled to corresponding ones of the plurality of electrical contacts (see, e.g., fig. 39),
and wherein the plurality of solder balls are in a same horizontal plane as the electrical conductor,
the horizontal plane parallel with the first side of the substrate
Regarding Claim 2, Lin (see, e.g., annotated figure 39, para.0716) shows the apparatus of claim 1,
wherein the electrical conductor is electrically isolated from another one of the plurality of electrical contacts.
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Annotated Figure 39
Regarding Claim 4, Lin (see, e.g., para.0684) shows the apparatus of claim 1,
wherein the electrical conductor includes copper 32.
Regarding Claim 5, Lin (see, e.g., para.0681) shows the apparatus of claim 1,
wherein the electrical conductor 583 further includes a protective layer 42 surrounding at least a portion of the electrical conductor.
Regarding Claim 7, Lin (see, e.g., fig. 39, annotated figure 39) shows the apparatus of claim 1,
wherein the electrical conductor is a first electrical conductor (fosters electrical connection through the bump),
and wherein the at least one of the plurality of electrical contacts is a first of the at least one of the plurality of electrical contacts; and further comprising:
a second electrical conductor on the first side of the substrate (top surface of 79),
wherein the second electrical conductor is electrically isolated from the first electrical conductor;
and wherein the second electrical conductor is electrically coupled with a second of the at least one of the plurality of electrical contacts.
Regarding Claim 8, Lin (see, e.g., annotated figure 39, para.0716) shows the apparatus of claim 7,
wherein the first electrical conductor is associated with a first power domain 314,
and the second electrical conductor is associated with a second power domain 313.
Regarding Claim 9, Lin (see, e.g., annotated figure 36a) shows the apparatus of claim 1,
wherein the electrical conductor 583 has a uniform thickness (a uniform thickness of the top portion of the 583).
Regarding Claim 10, Lin (see, e.g., fig. 41a, annotated figure 39, para.0725) shows the apparatus of claim 1,
wherein the first side of the substrate is coupled with a printed circuit board (PCB) 335,
wherein the plurality of contacts are coupled with the PCB using a ball grid array (BGA) 337,
and wherein the electrical conductor is electrically coupled with a first solder ball of the BGA and is electrically isolated from a second solder ball of the BGA (routings 313 & 314 are separate and have their own solder ball 337 at the top, see, e.g., fig. 39, annotated figure 39, para.0716).
Regarding Claim 11, Lin (see, e.g., para.0716, para.0725) shows the apparatus of claim 10,
wherein the first solder ball is associated with a power domain.
Regarding Claim 12, Lin (see, e.g., fig. 41a, para.0726) shows the apparatus of claim 1, further comprising
a die 411 coupled with the first side of the substrate,
wherein the die is electrically coupled with the electrical conductor,
and wherein the electrical conductor is electrically coupled with the second side of the substrate through electrical pathways in the substrate.
Regarding Claim 13, Lin (see, e.g., para.0656, para.0680) shows the apparatus of claim 1,
wherein a thickness of the electrical conductor is greater than a thickness of another trace on the substrate.
Regarding Claim 14, Lin (see, e.g., fig. 36a, fig. 39, fig. 41b, para.0681, para.0684) shows a system comprising:
a package 306 that includes:
a substrate 79, 92, & 101 with a first side (top surface of 79) and a second side (bottom surface of 101) opposite the first side;
a plurality of electrical contacts 27 on the first side of the substrate;
and a power rail 583 on the first side of the substrate,
the power rail with a thickness that extends from the first side of the substrate,
and wherein the power rail is not in direct electrical contact with at least some of the plurality of electrical contacts;
a plurality of solder balls 563 (see, e.g., para.0715),
wherein individual ones of the plurality of solder balls are coupled to corresponding ones of the plurality of electrical contacts (see, e.g., fig. 39),
and wherein the plurality of solder balls are in a same horizontal plane as the power rail
the horizontal plane parallel with the first side of the substrate
and a board 335 (see, e.g., para.0725) coupled with the first side of the substrate,
wherein the power rail is not in direct physical contact with the board.
Lin (see, e.g., para.0716) states element 583 can be used for power delivery through interconnects 313 & 314. Thus, said element is interpreted as a power rail and Lin anticipates the limitation.
Regarding Claim 15, Lin (see, e.g., para.0725-0727) shows the system of claim 14, further comprising
a ball grid array (BGA) 337 between the board and the first side of the substrate,
wherein the power rail is in direct electrical contact
with a first ball (connected to 335, see, e.g., para.0727)
and with a second ball of the BGA (connected to 411, see, e.g., para.0726).
Regarding Claim 16, Lin (see, e.g., fig. 41a) shows the system of claim 15,
wherein the first ball is directly electrically coupled with the board (connected to 335, see, e.g., para.0727),
and wherein the second ball is not directly electrically coupled with the board (connected to 411, see, e.g., para.0726).
Regarding Claim 17, Lin (see, e.g., para.0725) shows the system of claim 14,
wherein the board is a printed circuit board (PCB) 335.
Regarding Claim 18, Lin (fig. 41b, para.0732) shows the system of claim 14, further comprising
an electrical component 411 coupled with the second side of the substrate (411 has a wiring that coupled to bump 570 on the second side of the substrate, see, e.g., para.0726),
wherein the electrical component is electrically coupled with the power rail 583 (horizontally through 27 of a portion of the substrate 79).
Regarding Claim 19, Lin (see, e.g., para.0732) shows the system of claim 18,
wherein the electrical component 411 includes a die (CS IC Chip).
Regarding Claim 20, Lin (see, e.g., fig. 41b, para.0732) shows the system of claim 18,
wherein the electrical component is a plurality of electrical components (411 have multiple dies as an alternate option, see, e.g., para.0732).
Regarding Claim 21, Lin (see, e.g., fig. 41b) shows a method comprising:
providing a substrate 79, 92, & 101,
wherein the substrate has a first side (top surface of 79) and a second side (bottom surface of 101) opposite the first side,
and wherein the first side of the substrate includes a plurality of electrical contacts 27;
and forming an electrical bus 583 on the first side of the substrate,
wherein the electrical bus has a thickness that extends from a surface of the first side of the substrate,
and wherein the electrical bus is not directly electrically coupled to at least some of the plurality of electrical contacts (see, e.g., para.0716).
and forming a plurality of solder balls 563 (see, e.g., para.0715),
wherein individual ones of the plurality of solder balls are coupled to corresponding ones of the plurality of electrical contacts (see, e.g., fig. 39),
and wherein the plurality of solder balls are in a same horizontal plane as the electrical bus
the horizontal plane parallel with the first side of the substrate
Lin (see, e.g., para.0716) states element 583 can be used for transferring data signals through interconnects 313 & 314. Thus, said element is interpreted as an electrical bus and Lin anticipates the limitation.
Regarding Claim 22, Lin (see, e.g., fig. 41a, para.0725) shows the method of claim 21, further comprising:
coupling the first side of the substrate to a printed circuit board (PCB) 335,
wherein the coupling includes
coupling a ball grid array (BGA) 337 to the plurality of electrical contacts
and coupling the BGA to the PCB (see, e.g., fig. 41a).
Regarding Claim 23, Lin shows the method of claim 22,
wherein the plurality of electrical contacts 27 is a first plurality of electrical contacts 27 (considered first now);
and wherein forming the electrical bus 583 further includes electrically coupling a second plurality of electrical contacts (elements 26a-b shown in fig. 36a which shows the same device 301 in fig. 4b , see, e.g., ).
Regarding Claim 24, Lin shows the method of claim 21,
wherein the electrical bus 583 is a first electrical bus (now the first); and further comprising:
forming a second electrical bus 571 on the second side of the substrate (on the bottom surface of 101);
and electrically coupling the first electrical bus and the second electrical bus using an electrical connection (electrical connection through interconnection elements 79, 158, & 101) within the substrate that extends from the first side of the substrate to the second side of the substrate.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210050300).
Regarding Claim 3, Lin (see, e.g., para.0656) shows the apparatus of claim 1,
wherein the electrical conductor has a thickness ranging from 1 µm to 60 µm.
Lin, however, fails to show wherein the electrical conductor has a thickness ranging from 30 µm to 150 µm, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976). See MPEP
However, ranges of thickness will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Criticality
The specification contains no disclosure of either the critical nature of the claimed temperature and pressure ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210050300) in view of Yu (US 20210296252).
Regarding Claim 25, Lin shows the method of claim 21,
Lin however, fails to show
wherein forming the electrical bus further includes forming the electrical bus using a selected one of: direct plating or cold spray.
Yu (see, e.g., fig. 1k, para.0048), in a similar device to Lin, teaches that direct plating would form the proper structure and conductive properties required for the electrical bus to have multiple connections in a semiconductor package.
It would be obvious to one at the time of filing the invention to one of ordinary skill in the art to use the direct plating of Yu in the device of Lin form the proper structure and conductive properties required for the electrical bus to have multiple connections in a semiconductor package.
Response to Amendments
Regarding the amended limitation “the horizontal plane parallel with the first side of the substrate” of Claims 1, 14, & 21, the elements 563 & 583 of Lin used for the different independent claims still are in a same horizontal plane after the amendment. Elements 583 & 563 are considered in a same horizontal plane parallel to the first side of the substrate (top surface of layer 79) because the bottom surface of 563 and the topmost surface 583 are in the horizontal plane contacting one another.
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Response to Arguments
Applicant's arguments filed 08/11/2026, with regard to the rejections under 35 U.S.C. 103 have been fully considered but they are not persuasive. See response to amendments above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
