DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
This Action is in response to communications filed 10/07/2025.
Claims 1, 3-5, 8, 10-12, and 16 have been amended.
Claims 1-22 are pending.
Claims 1-22 are rejected.
Response to Arguments
In Remarks filed on 10/07/2025, Applicant substantially argues:
On Pages 6-11, the term “circuitry” is not to be interpretation under invoking 35 U.S.C. 112(f) as determined in Linear Tech. Corp. v. Impala Linear Corp., 379 F.3d 1311, 72 USPQ2d 1065 (Fed. Cir. 2004). Applicant’s arguments filed have been fully considered and they are persuasive. The Examiner withdraws the notice that claims 1-15 are to be interpreted as invoking 35 U.S.C.112(f).
On Page 11, the 35 U.S.C. 112(b) rejection on Page 5 of the Office action dated 07/21/2025 contains no identification of claims rejected or rationale and therefore no response is required. The Examiner notes Applicant’s interpretation is correct as no rejection of the claims has been made under 35 U.S.C. 112(b) and the inclusion of the section is a typographical error.
On Pages 11-12, the applied references Chen, Lien and Huang fail to disclose the amended limitations of claim 1, and similarly amended claims 8 and 16, regarding circuitry that “is to determine whether a current error correction level and/or current lockstep mapping is sufficient to manage a hard error condition.” Applicant’s arguments filed have been fully considered but they are moot in view of the current rejection made in response to Applicant’s amendments.
All arguments by the applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated October 7, 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6-14, 16-19, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2020/0151056) in view of Lien et al. (US 10,783,973) and further in view of Das et al. (US 2016/0232063).
Regarding claim 1, Chen discloses, in the italicized portions, a compute device comprising: a memory including a plurality of ranks, each rank comprising a plurality of memory devices (Figure 3, memory module 202c comprising ranks 308 and 310 which further comprise a plurality of memory devices 114 and 104), each memory device comprising a plurality of banks (Figure 3, banks 0-15); and circuitry to use a bank error counter per bank in the memory to perform error management of the memory (Figure 3, error corrector 112); wherein the circuitry is to determine whether a current error correction level and/or current lockstep mapping is sufficient to manage a hard error condition. Herein Chen discloses a memory device monitoring system for detecting and correcting errors in volatile memory devices. In particular, the structure of the memory devices are detailed as being organized into ranks and banks as claimed. Chen discloses in Paragraph [0069] usage of error counter trackers to specific locations but does not explicitly disclose using bank error counter per bank to perform the error management steps or circuitry to determine whether the current error correction level or current lockstep mapping is sufficient to manage a hard error condition. Regarding bank error counter per bank to perform the error management steps, Lien discloses in Column 3, lines 58-60 “Each memory block or memory bank may correspond to a dedicated error counter. Alternatively, an error counter could be shared by multiple memory blocks or memory banks.” Herein Lien explicitly identifies error counters may be organized according to memory bank level. Furthermore, Lien discloses error counters associated with portions of a memory bank as well. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to utilize per bank error counters in order to perform the error management operations on a specified bank in memory as both Chen and Lien are involved with performing targeted error correction operations based on detected regional error counts. Lien does not explicitly address determining the sufficiency of managing a hard error condition. Regarding this aspect of the limitation, Das disclose in Paragraph [0055] “Error manager 134 includes determination logic to determine whether the current level of error correction or the current lockstep mapping 136 is sufficient to manage known hard errors. Error manager 134 includes determination logic to determine when and how to change lockstep partnerships to respond to additional errors that might occur in an existing lockstep partnership.” Herein Das explicitly discloses error manager 134, which is included in memory controller 130, as including and executing determination logic to address the whether the current level of error correction or the current lockstep mapping is sufficient to manage known hard errors. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory circuitry of Chen and Lien to include the determination logic as presented in Das to improve error detection and error handling (Das Abstract and Paragraphs [0054] and [0056-57]). Chen, Lien, and Das are analogous art because they are from the same field of endeavor of managing error correction operations.
Regarding claim 2, Chen further discloses the compute device of Claim 1, wherein an error checking code format used to perform error management is Adaptive Double Device Data Correction (ADDDC) ([0032] In the illustrated example of FIG. 1, the memory controller 100 includes the error corrector 112 to perform a memory correction action such as an ADDDC action or any other type of memory correction action.). Herein Chen explicitly recites performing an ADDDC error correction.
Regarding claim 3, Chen further discloses the compute device of Claim 2, wherein the circuitry is to use the bank error counter to perform ADDDC bank sparing ([0049] In some examples, the error corrector 112 determines whether a memory region (e.g., a rank, a bank, etc.) including a detected error was previously subjected to a memory correction action such as an AVL process. For example, the error corrector 112 may determine that the bank 0 316 of FIGS. 3-4 is governed by one or more AVL rules, lockstep partnerships, etc. In some examples, the error corrector 112 determines whether to perform a memory correction action or to move affected data to a spare region of an ECC device. For example, the error corrector 112 may compare a number of corrected errors in the bank 0 316, a number of corrected errors in the rank 0 308, etc. to a corrected errors threshold (e.g., more than two corrected errors in the bank 0 316, more than two corrected errors in the rank 0 308, etc.) and determine whether the number of corrected errors satisfies the corrected errors threshold.). Herein Chen recites moving data to spare data regions including on a rank or bank level basis.
Regarding claim 4, Chen further discloses the compute device of Claim 3, wherein the circuitry is to perform ADDDC bank sparing if the error count for a bank equals or exceeds a per bank ADDDC threshold ([0049] If, the example error corrector 112 determines that the number of corrected errors does satisfy the corrected errors threshold, then the error corrector 112 may map or move the data in the bank 0 316 to a spare region or a spare bank in the ECC device 114.). Herein Chen discloses performing the bank sparing operation when determining the error count satisfies the error threshold which is interpreted as being equal to or exceeding the per bank ADDDC threshold. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Regarding claim 6, Chen further discloses the compute device of Claim 1, wherein the memory is a Dynamic Random Access Memory ([0038] In the illustrated example, the memory modules 202 include sets of DRAM chips connected to the same address and data buses. Each set of DRAM chips forms a rank.). Herein Chen discloses the memory modules being managed include DRAM chips.
Regarding claim 7, Lien further discloses the compute device of Claim 1, wherein the bank error counter is stored in the memory (Figure 2, error counter 231). Herein Lien discloses the error counter as being stored within the memory.
Regarding claim 8, Chen discloses, in the italicized portions, a system comprising: a processor (Figure 10, processor 1012); a memory including a plurality of ranks, each rank comprising a plurality of memory devices, each memory device comprising a plurality of banks (Figure 3, memory module 202c comprising ranks 308 and 310 which further comprise a plurality of memory devices 114 and 104, banks 0-15); and circuitry to use a bank error counter per bank in the memory to perform error management of the memory (Figure 3, error corrector 112); wherein the circuitry is to determine whether a current error correction level and/or current lockstep mapping is sufficient to manage a hard error condition. Herein Chen discloses a memory device monitoring system for detecting and correcting errors in volatile memory devices. In particular, the structure of the memory devices are detailed as being organized into ranks and banks as claimed. Chen discloses in Paragraph [0069] usage of error counter trackers to specific locations but does not explicitly disclose using bank error counter per bank to perform the error management steps or circuitry to determine whether the current error correction level or current lockstep mapping is sufficient to manage a hard error condition. Regarding bank error counter per bank to perform the error management steps, Lien discloses in Column 3, lines 58-60 error counters may be organized according to memory bank level. Furthermore, Lien discloses error counters associated with portions of a memory bank as well. Lien does not explicitly address determining the sufficiency of managing a hard error condition. Regarding this aspect of the limitation, Das disclose in Paragraph [0055] error manager 134, which is included in memory controller 130, as including and executing determination logic to address the whether the current level of error correction or the current lockstep mapping is sufficient to manage known hard errors. Claim 8 is rejected on a similar basis as claim 1.
Regarding claim 9, Chen further discloses the system of Claim 8, wherein an error checking code format used to perform error management is Adaptive Double Device Data Correction (ADDDC) ([0032]). Claim 9 is rejected on a similar basis as claim 2.
Regarding claim 10, Chen further discloses the system of Claim 9, wherein the circuitry is to use the bank error counter to perform ADDDC bank sparing ([0049]). Claim 10 is rejected on a similar basis as claim 3.
Regarding claim 11, Chen further discloses the system of Claim 10, wherein the circuitry is to perform ADDDC bank sparing if the error count for a bank equals or exceeds a per bank ADDDC threshold ([0049]). Claim 11 is rejected on a similar basis as claim 4. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Regarding claim 13, Chen further discloses the system of Claim 8, wherein the memory is a Dynamic Random Access Memory ([0038]). Claim 13 is rejected on a similar basis as claim 6.
Regarding claim 14, Lien further discloses the system of Claim 8, wherein the bank error counter is stored in the memory (Figure 2, error counter 231). Claim 14 is rejected on a similar basis as claim 7.
Regarding claim 15, Chen further discloses the system of claim 8, further comprising one or more of: a display communicatively coupled to the processor; or a battery coupled to the processor ([0086] One or more output devices 1024 are also connected to the interface circuit 1020 of the illustrated example. [0100] The system 1200 of the illustrated example includes a chassis 1202, which includes removably attached power supplies 1204 and removably attached servers 1206.). Herein Chen discloses display and battery components coupled to the processor in the system.
Regarding claim 16, Chen discloses, in the italicized portions, one or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed ([0051] memory controller of Figs. 1-4 defined to include a non-transitory computer readable storage device including the software/firmware), cause a system to perform operations comprising: store data in a memory, the memory including a plurality of ranks, each rank comprising a plurality of memory devices, each memory device comprising a plurality of banks (Figure 3, memory module 202c comprising ranks 308 and 310 which further comprise a plurality of memory devices 114 and 104, banks 0-15); perform error management of the memory using a bank error counter per bank in the memory (Figure 3, error corrector 112); and determine whether a current error correction level and/or current lockstep mapping is sufficient to manage a hard error condition. Herein Chen discloses a memory device monitoring system for detecting and correcting errors in volatile memory devices. In particular, the structure of the memory devices are detailed as being organized into ranks and banks as claimed. Chen discloses in Paragraph [0069] usage of error counter trackers to specific locations but does not explicitly disclose using bank error counter per bank to perform the error management steps or circuitry to determine whether the current error correction level or current lockstep mapping is sufficient to manage a hard error condition. Regarding bank error counter per bank to perform the error management steps, Lien discloses in Column 3, lines 58-60 error counters may be organized according to memory bank level. Furthermore, Lien discloses error counters associated with portions of a memory bank as well. Lien does not explicitly address determining the sufficiency of managing a hard error condition. Regarding this aspect of the limitation, Das disclose in Paragraph [0055] error manager 134, which is included in memory controller 130, as including and executing determination logic to address the whether the current level of error correction or the current lockstep mapping is sufficient to manage known hard errors. Claim 16 is rejected on a similar basis as claim 1.
Regarding claim 17, Chen further discloses the one or more non-transitory machine-readable storage media of Claim 16, wherein an error checking code format used to perform error management is Adaptive Double Device Data Correction (ADDDC) ([0032]). Claim 16 is rejected on a similar basis as claim 2.
Regarding claim 18, Chen further discloses the one or more non-transitory machine-readable storage media of Claim 17, wherein the bank error counter is used to perform ADDDC bank sparing ([0049]). Claim 18 is rejected on a similar basis as claim 3.
Regarding claim 19, Chen further discloses the one or more non-transitory machine-readable storage media of Claim 18, wherein ADDDC bank sparing is performed if the error count for the respective bank equals or exceeds a per bank ADDDC threshold ([0049]). Claim 19 is rejected on a similar basis as claim 4. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Regarding claim 21, Chen further discloses the one or more non-transitory machine-readable storage media of Claim 16, wherein the memory is a Dynamic Random Access Memory ([0038]). Claim 21 is rejected on a similar basis as claim 6.
Regarding claim 22, Lien further discloses the one or more non-transitory machine-readable storage media of Claim 16, wherein the bank error counter is stored in the memory (Figure 2, error counter 231). Claim 22 is rejected on a similar basis as claim 7.
Claims 5, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lien and further in view of Das and still in further view of Huang et al. (US 2016/0093404).
Regarding claim 5, Chen, Lien and Das do not explicitly disclose the compute device of Claim 3, wherein the circuitry is to perform ADDDC rank sparing if the error count for the bank equals or exceeds a per bank ADDDC threshold and ADDDC bank sparing has been performed for another bank in a same rank as the respective bank. Chen, however, specifically addresses performing sparing at different granularities to address error detections which include reverse sparing. Regarding these limitations for performance of the rank sparing, Huang discloses in Paragraphs [0090-91] “[0090] When a DRAM device failure occurs which only affects a single bank, that bank will be forward spared to map out the bad device. If the same device failure later degrades to affect the entire rank, the entire rank needs to be spared. Reverse Sparing is then used to transition the bank failure to rank failure by first reversing the original bank spare, then forward sparing the entire rank. [0091] The benefit of this configuration is that with the addition of bank granular sparing, reverse sparing was invented to transition the granularity of the failed region. Reverse sparing may be used when a bank failure subsequently turns into a rank failure (or a second bank within the same device fails).” Herein Huang explicitly discloses the benefit of reverse sparing functionality by enabling rank sparing after having already performed bank sparing for a bank within the rank and sustaining another bank failure within the rank. In this manner, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the reverse sparing as being performed in Chen may be organized by the parameters as disclosed by Huang to perform the rank sparing in view of a second bank failure after a first bank sparing for a rank to transition the bank failures into rank failures and resolve the failures by substituting a new rank. Chen, Lien, Das, and Huang are analogous art because they are from the same field of endeavor of managing error correction operations. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Regarding claim 12, Chen, Lien, and Das do not explicitly disclose the system of Claim 10, wherein the circuitry is to perform ADDDC rank sparing if the error count for the bank equals or exceeds a per bank ADDDC threshold and ADDDC bank sparing has been performed for another bank in a same rank as the respective bank. Chen, however, specifically addresses performing sparing at different granularities to address error detections which include reverse sparing. Regarding these limitations for performance of the rank sparing, Huang discloses in Paragraphs [0090-91] the benefit of reverse sparing functionality by enabling rank sparing after having already performed bank sparing for a bank within the rank and sustaining another bank failure within the rank. Claim 12 is rejected on a similar basis as claim 5. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Regarding claim 20, Chen, Lien, and Das do not explicitly disclose the one or more non-transitory machine-readable storage media of Claim 18, wherein ADDDC rank sparing is performed if the error count for the respective bank equals or exceeds a per bank ADDDC threshold and ADDDC bank sparing has been performed for another bank in a same rank as the respective bank. Chen, however, specifically addresses performing sparing at different granularities to address error detections which include reverse sparing. Regarding these limitations for performance of the rank sparing, Huang discloses in Paragraphs [0090-91] the benefit of reverse sparing functionality by enabling rank sparing after having already performed bank sparing for a bank within the rank and sustaining another bank failure within the rank. Claim 20 is rejected on a similar basis as claim 5. The Examiner notes the limitation is recited in contingent form and therefore the broadest reasonable interpretation of the claim only requires the structure for performing the function should the condition occur. See MPEP 2111.04(II).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Riga et al. (US 2016/0321137) – Paragraph [0002] wherein soft and hard error correction is discussed.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER J YOON whose telephone number is (408)918-7629. The examiner can normally be reached on Monday-Friday 8am-3pm ET. The examiner’s email is alexander.yoon2@uspto.gov.
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/ALEXANDER YOON/
Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135