DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 08/10/2026 with respect to claims 1, 8, 13, 15 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 12-13, 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ponnuvel et al (US Publication No. 20200117565) in view of Sri-Jayantha et al (US Publication No. 20060013281) and in view of Soga et al (US Patent No. 5867809) and further in view of Matsui (US Publication No. 20180143655).
Regarding claim 1, Ponnuvel teaches discloses an apparatus (i.e., 104, see for example fig. 1, para. [0034]- [0040]) comprising: interface circuitry (i.e., such as PCB, PEX, HSI, see for example para. [0075]) to interface with one or more sensors (i.e., plurality of internal sensor 102 associated with each hardware component, see for example para. [0065]) that monitor one or more characteristics of a compute device (i.e., 100/1000; computing device 1000, see for example fig. 10, para. [0190]); machine readable instructions (i.e., such as the memory 1004 may include any of a variety of computer-readable media; see for example fig. 10, para. [0189]- [0202]); and at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0139]) to be programmed based on the machine-readable instructions (i.e., such as the memory 1004 may include any of a variety of computer-readable media; see for example fig. 10, para. [0189]- [0202]).
Ponnuvel does not teach wherein to calculate a value representative of degradation associated with a thermal interface material between an integrated circuit and a heat sink of the compute device, the value based on sensor information from the interface circuitry; and cause generation of a thermal degradation alert based on the value.
Sri-Jayantha teaches in a similar field of endeavor in electronic thermal sensors (i.e., fig. 1A, para. [0076]); wherein to calculate a value representative of degradation (Tij) associated with a thermal interface material (140) between an integrated circuit (110) and a heat sink (130) of the computer device (100), the value (i.e., to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); fig. 1B, para. [0086]) based on sensor information (i.e., by deploying an array of temperature sensors on the chip surface with (n.times.n) zones, (n.times.n) instantaneous temperature values are measured; fig. 1B, para. [0081]) from the interface circuitry (i.e., 400; fig. 4, para. [0107]) and cause generation of a thermal degradation alert (i.e., such as a state variable model of the thermal system can be driven by current input; fig. 1B, para. [0095]) based on the value (i.e., such as to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); see for example fig. 1B, para. [0086]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the thermal interface material in Ponnuvel, as taught by Sri- Jayantha, as it provides the advantage of optimizing the circuit design towards efficient heat dissipation and reliable cooling system.
Neither Ponnuvel nor Sri- Jayantha teaches and a model, the model to relate power to temperature under different dryness conditions of the thermal interface material, the sensor information including a measured power and a measured temperature associated with the compute device; and cause generation of a thermal degradation alert based on the value.
Soga teaches in a similar field of endeavor in electronic thermal sensors (i.e., such as model 15b; fig. 2, Col. 9 lines 32+), the model (i.e., such as model 15b; fig. 2, Col. 9 lines 32+) to relate power to temperature under (i.e., such as to relate power to temperature as in formula#1 and formula#2; fig. 2, Col. 9 lines 32+) different dryness conditions (i.e., such as different dryness conditions as humidity M; fig. 2, Col. 9 lines 32+) of the thermal interface material (i.e., such as thermal interface material as substrate having wiring conductors on the basis of the phenomenon of migration for chip 5; fig. 2, Col. 9 lines 32+), the sensor (i.e., such as the sensor 15a; fig. 2, Col. 9 lines 32+) information (i.e., such as measured power as measured power E in formula#1; see for example fig. 9, Col. 9 lines 32+) (i.e., such as measured temperature T in formula#2; see for example fig. 9, Col. 9 lines 32+) including a measured power (i.e., such as measured power as measured power E in formula#1; see for example fig. 9, Col. 9 lines 32+) and a measured temperature (i.e., such as measured temperature T in formula#2; see for example fig. 9, Col. 9 lines 32+) associated with the compute device (i.e., such as the compute device LSI chip 5; fig. 1, Col. 9 lines 32+), and cause generation of a thermal degradation alert based on the value (i.e., such as the temperature sensor 15a can use a system for detecting the temperature by measuring a change in thermal strain, or a resistance system (for example, thermal resistance of pn junction) for detecting the temperature by measuring a change in electric resistance, or a system for detecting the temperature by using thermal radiation, or a thermocouple system detecting the temperature by using thermoelectromotive force; see for example fig. 1, Col. 9 lines 32+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the humidity sensor device in Ponnuvel, as taught by Soga, as it provides the advantage of optimizing the circuit design towards prolonging the lifespan of semiconductor manufacturing equipment and maintaining end-product quality.
Neither Ponnuvel nor Sri- Jayantha nor Soga teaches the model based on test data including power consumption values and temperature values from other compute devices.
Matsui teaches in a similar field of endeavor in electronic thermal sensors (i.e., thermal system 11; fig. 2); wherein the model (model 12) based on test data (i.e., test data/information; para. [0036]) including power consumption values (i.e., power consumption values; para. [0036]) and temperature values (i.e., temperature values; para. [0036]) from other compute devices (i.e., compute devices 1; para. [0036]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the power consumption data in Ponnuvel, as taught by Matsui, as it provides the advantage of optimizing the circuit design.
Regarding claim 3, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; wherein the one or more sensors (i.e., plurality of internal sensor 102 associated with each hardware component, see for example para. [0065]) include an ultrasound receiver (i.e., such as ultrasonic sensors 962, see for example para. [0103]) and a timer (i.e., such as timers and interrupt controllers, see for example para. [0149]), the timer (i.e., such as timers and interrupt controllers, see for example para. [0149]) to determine an amount of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) an ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) generated by an ultrasound transmitter (i.e., such as ultrasonic sensors 962, see for example para. [0103]) takes to travel through the thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]) to the ultrasound receiver (i.e., such as ultrasonic sensors 962, see for example para. [0103]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 4, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; wherein one or more of the at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) is to determine whether the amount of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) satisfies (i.e., remedial action manager circuitry 118, see for example para. [0174]) a threshold (i.e., exceeds a threshold value, degradation threshold as of the thermal interface hardware component sensors; see for example para. [0047]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 5, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; wherein one or more of the at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) is to validate the thermal degradation alert (i.e., thermal degradation alert; remedial action manager 118; see for example para. [0139]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 6, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; wherein one or more of the at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) is to cause an ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) to be transmitted through a thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]); determine an amount of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) the ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) traverses a length of the thermal interface material (i.e., operating time versus thermal degradation in terms of modes, see for example fig. 3, para. [0074]); determine a state of degradation of the thermal interface material (i.e., such as test parameters that are applied during each state, see for example para. [0052]) based on the amount of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]); and validate (i.e., remedial action manager circuitry 118, see for example para. [0174]) the thermal degradation alert (i.e., thermal degradation alert; remedial action manager 118; see for example para. [0036]) based on the state of degradation of the thermal interface material (i.e., such as test parameters that are applied during each state, see for example para. [0052]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 7, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Sri-Jayantha further teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]); the sensor (i.e., such as the sensor 700; see for example fig. 7A, para. [0118]- [0125]) information (i.e., such as thermal information; see for example fig. 7A, para. [0118]- [0125]) includes a capacitive measurement (i.e., such as capacitive measurement C2; see for example fig. 7B, para. [0118]- [0125]) of the thermal interface material (i.e., such as thermal interface material TIM 340; see for example fig. 3, para. [0118]- [0125]), and one or more of the at least one processor circuit (i.e., such as one or more of the at least one processor circuit 725 and 775; see for example fig. 7A, para. [0118]- [0125]) is to estimate an amount of degradation (i.e., such as amount of degradation as in the equations of the energy balance as well as the equations of the dynamic model; see for example fig. 7B, para. [0118]- [0125]); based on the capacitive measurement (i.e., such as capacitive measurement C2; see for example fig. 7B, para. [0118]- [0125]).
Regarding claim 8, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; an apparatus (104, fig. 1, para. [0034]- [0040]), comprising: at least one memory (i.e., such as 1004; see for example fig. 10, para. [0189]- [0202]); machine readable instructions (i.e., such as the memory 1004 may include any of a variety of computer-readable media); and processor circuit (i.e., 100; configuration circuitry, see for example para. [0139]) to be programmed based on the machine-readable instructions (i.e., such as the memory 1004 may include any of a variety of computer-readable media; see for example fig. 10, para. [0189]- [0202]) to calculate a first value (i.e., degradation index value; degradation rate determiner) to represent an amount (i.e., such as test parameters that are applied during each state, see for example para. [0052]) of degradation associated with a thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]), the first value (i.e., degradation index value; degradation rate determiner) based on a model (i.e., such as model 104; see for example fig. 1, para. [0034]) of the compute device (i.e., 100/1000; computing device 1000, see for example fig. 10, para. [0190]) having different levels of degradation (i.e., operating time versus thermal degradation in terms of modes, see for example fig. 3, para. [0074]); and generate a first alert (i.e., such as trigger circuitry 118) based on comparison (i.e., such as comparing degradations circuitry 116) of the first value (i.e., degradation index value; degradation rate determiner) to a first threshold (i.e., degradation index threshold; degradation rate analyzer). And, for the rest of the limitations/features in claim 8 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Regarding claim 12, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; including; an ultrasound transmitter (i.e., such as ultrasonic sensors 962, see for example para. [0103]); an ultrasound receiver (i.e., such as ultrasonic sensors 962, see for example para. [0103]); and a timer (i.e., such as timers and interrupt controllers, see for example para. [0149]) to determine a travel time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) of an ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) generated by the ultrasound transmitter (i.e., such as ultrasonic sensors 962, see for example para. [0103]) through the thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]) to the ultrasound receiver (i.e., such as ultrasonic sensors 962, see for example para. [0103]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 13, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; a non-transitory machine-readable storage medium (i.e., such as SGRAM, SRAM, RAM, DRAM, VRAM; see for example fig. 1, para. [0034]- [0040]), comprising instructions (i.e., such as if the cutoff value exceeds a corresponding value on the threshold line 408, see for example fig. 4, para. [0072]), to cause at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) to at least calculate (i.e., such as degradation-calculations circuitry 114) a value (i.e., degradation index value; degradation rate determiner) (i.e., the degradation rate determiner circuit; see for example fig. 1, para. [0034]- [0040]) representative of degradation associated (i.e., degradation index value; degradation rate determiner) with a thermal interface material (i.e., degradation index value; degradation rate determiner) (i.e., such as degradation rate determiner circuit; see for example fig. 1, para. [0034]- [0040]). And, for the rest of the limitations/features in claim 13 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Regarding claim 16, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; the non-transitory machine-readable storage medium (i.e., such as SGRAM, SRAM, RAM, DRAM, VRAM; see for example fig. 1, para. [0034]- [0040]), wherein the instructions (i.e., such as if the cutoff value exceeds a corresponding value on the threshold line 408, see for example fig. 4, para. [0072]), are to cause one or more of at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0139]) to determine a travel time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) of an ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) through the thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]) of the compute device (i.e., 100/1000; computing device 1000, see for example fig. 10, para. [0190]); prior to triggering (i.e., such as trigger circuitry 118) the generation of the alert (i.e., thermal degradation alert; remedial action manager); based on the travel time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) exceeding a threshold (i.e., degradation index threshold; degradation rate analyzer); trigger (i.e., such as trigger circuitry 118) the generation of the alert (i.e., thermal degradation alert; remedial action manager); and based on the travel time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) not exceeding the threshold (i.e., degradation index threshold; degradation rate analyzer); delay the generation of the alert (i.e., thermal degradation alert; remedial action manager).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 17, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; a method (i.e., 700; see for example fig. 7, para. [0085]- [0089]). And, for the rest of the limitations/features in claim 17 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1}
Regarding claim 19, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; the method (i.e., 700; see for example fig. 7, para. [0085]- [0089]); including: determining a duration of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) an ultrasound signal (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) generated by an ultrasound transmitter (i.e., such as ultrasonic sensors 962, see for example para. [0103]) takes to travel through a length (i.e., operating time versus thermal degradation in terms of modes, see for example fig. 3, para. [0074]) of the thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]) of the compute device (i.e., 100/1000; computing device 1000, see for example fig. 10, para. [0190]); and based on the duration of time (i.e., such as based on a change to values of the performance characteristic over time, see for example para. [0042]) satisfying (i.e., remedial action manager circuitry 118, see for example para. [0174]) a threshold (i.e., degradation index threshold; degradation rate analyzer), validating (i.e., remedial action manager circuitry 118, see for example para. [0174]) the alert (i.e., thermal degradation alert; remedial action manager, see for example para. [0071]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Regarding claim 20, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; the method (i.e., 700; see for example fig. 7, para. [0085]- [0089]); including delaying (i.e., such as degradation calculations circuitry 114) generating (i.e., such as trigger circuitry 118) of the alert (i.e., thermal degradation alert; remedial action manager) until the alert (i.e., thermal degradation alert; remedial action manager) is validated (i.e., thermal degradation alert; remedial action manager, see for example para. [0071]).
Sri-Jayantha furthermore teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Claims 2, 9-11, 14-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ponnuvel et al (US Publication No. 20200117565) in view of Sri-Jayantha et al (US Publication No. 20060013281) and in view of Soga et al (US Patent No. 5867809) and in view of Matsui (US Publication No. 20180143655) and further in view of Casparian et al (US Publication No. 20170168531).
Regarding claim 2, Ponnuvel in view of Sri-Jayantha and in view of Soga and further in view of Matsui and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui have been discussed above as well.
Ponnuvel further teaches the apparatus; wherein the value (i.e., such as degradation-calculations circuitry 114) is a first value (i.e., such as degradation calculations circuitry 114) and one or more of at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0139]) is to calculate (i.e., such as degradation-calculations circuitry 114). Sri-Jayantha furthermore discloses the thermal system (i.e., see for example fig. 1A, para. [0076]); the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Neither Ponnuvel nor Sri- Jayantha nor Soga nor Matsui teaches wherein to calculate a second value representative of fan inlet/outlet blockage, the second value based on the sensor information from the interface circuitry, the sensor information to include one or more fan speed values; and cause generation of the thermal degradation alert based on the second value, the thermal degradation alert to at least one of i) indicate that a fan inlet/outlet vent associated with the compute device is blocked, ii) indicate that the compute device is operating at a temperature that can cause thermal degradation, or iii) trigger a self-cleaning operation to be performed.
Casparian teaches in a similar field of endeavor in electronic thermal sensors (i.e., 180; see for example fig. 1, para. [0039]- [0044]); wherein to calculate (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]) a second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) representative of fan inlet/outlet blockage (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]), the second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) based on the sensor information (i.e., such as sensors 114s; see for example para. [0029]) from the interface circuitry (i.e., such as SM Bus, LPC, SPI, etc.; see for example fig. 1, para. [0030]), the sensor information (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) to include one or more fan speed values (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) (i.e., such as sensors 114s; see for example para. [0029]); and cause generation of the thermal degradation alert (i.e., non-volatile persistent storage 107 or other nonvolatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) based on the second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]), the thermal degradation alert (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) to at least one of i) indicate that a fan inlet/outlet vent (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]) associated with the compute device (i.e., such as compute device 100, see for example para. [0074]) is blocked (i.e., such as control may be supplemented with leveraging the existing fan curve and chip temperature lookup table found in NVM 107 and the sensed supplemental cooling air temperature (e.g., as sensed by dock temperature sensor 194a and/or by an optional temperature sensor 194b mounted within chassis 179 to sense ambient temperature at an air inlet 161 and report this sensed temperature directly to CPU 105) entering into the air intake vents 161; see for example fig. 1, para. [0032]), ii) indicate that the compute device (i.e., such as compute device 100, see for example para. [0074]) is operating (i.e., such as to operate at a predefined high-level speed from about 75%-100% PWM, see for example para. [0072]) at a temperature (i.e., the temperature that activates the cooling circuit; (i.e., such as cooling dock control application 129 may be configured to further control overclocking (e.g., enable, disable and/or vary overclocking speed) and/or operating voltage of CPU and/or dGPU based on the selected mode of operation and/or real time CPU operating temperature, e.g., through appropriate APl's); see for example fig. 1, para. [0037]), that can cause thermal degradation (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]), or iii) trigger a self-cleaning operation to be performed (i.e., such as chilling system 175 may itself include a hot-side heat exchanger and associated fan for dissipating collected heat from the chilling system, see for example para. [0041]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the fans device in Ponnuvel, as taught by Casparian, as it provides the advantage of optimizing the circuit design towards regulating the temperature, ensuring optimal performance and longevity of the hardware.
Regarding claim 9, is rejected for the same reasons that have already been stated/discussed above in rejected claim 2. {See rejection of claim 2}
Regarding claim 10, Ponnuvel in view of Sri-Jayantha and in view of Soga and in view of Matsui and further in view of Casparian and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui and the teachings of Ponnuvel as modified by Casparian have been discussed above as well.
Ponnuvel teaches the apparatus; wherein one or more of the at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0139]) is to: prior to generation (i.e., such as comparing degradations circuitry 116) (i.e., such as trigger circuitry 118) of the first alert (i.e., such as trigger circuitry 118), verify the first alert (i.e., such as trigger circuitry 118) based on at least one of i) an amount of time an ultrasound signal (i.e., such as ultrasonic sensors 962, see for example para. [0103]) (i.e., such as ultrasonic sensors 962, see for example para. [0103]) travels (i.e., such as send signals to operate; signals representing commands to enable, see for example para. [0102]) through the thermal interface material (i.e., such as plurality of thermal interface hardware component, see for example para. [0152]); a capacitive value of the thermal interface material; based on the first alert (i.e., such as trigger circuitry 118) being validated (i.e., such as validated via degradation index threshold; degradation rate analyzer).
Sri-Jayantha further teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]); capacitive value (i.e., such as capacitive value C2; see for example fig. 7B, para. [0125]) of the thermal interface material (i.e., such as thermal interface material TIM 340; see for example fig. 3, para. [0083]) (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Casparian furthermore teaches the cooling system; determine whether the apparatus (180) includes a fan (i.e., such as fans 159 inlet/outlet vents (161/163)); and based on the apparatus (180) being fan-less (i.e., zero RPM), trigger the generation of the first alert (i.e., such as to operate at a predefined high-level speed from about 75%- 100% PWM, see for example para. [0072]).
Regarding claim 11, Ponnuvel in view of Sri-Jayantha and in view of Soga and in view of Matsui and further in view of Casparian and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui and the teachings of Ponnuvel as modified by Casparian have been discussed above as well.
Sri-Jayantha further teaches the thermal system; the thermal interface material (i.e., thermal interface material (TIM) 140; see for example fig. 1A, para. [0076]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Casparian furthermore teaches the cooling system; wherein one or more of the at least one processor circuit (i.e., such as CPU monitoring and reaction sequence 390 begins with initial step 358 where it is determined by cooling dock control application 129 whether CPU 105 is configured with overclocking capability, see for example fig. 3C, para. [0072]) is to: determine whether the fan is present (i.e., such as fans 159 inlet/outlet vents (161/163)); determine whether at least a first amount of area (i.e., such as a hot side heat exchanger, see for example para. [0041]) of a fan vent (i.e., such as vents 161 and 163) associated with the fan (i.e., such as fans 159 inlet/outlet vents (161/163)) is blocked (i.e., such as to check up the speed of the dock fan/s 178; chassis enclosure, e.g., between vents 161 and 163), the first amount of area (i.e., such as a hot-side heat exchanger, see for example para. [0041]) associated with thermal degradation (i.e., hot-side); and based on less than at least the first amount of area (i.e., such as a hot-side heat exchanger, see for example para. [0041]) of the fan vent (i.e., such as vents 161 and 163) being blocked (i.e., such as to check up the speed of the dock fan/s 178; chassis enclosure, e.g., between vents 161 and 163), delay generation of the first alert (i.e., such as starting bidirectional signal communication) until the at least the first amount of area (i.e., such as a hot-side heat exchanger, see for example para. [0041]) of the fan vent (i.e., such as vents 161 and 163) is blocked (i.e., such as to check up the speed of the dock fan/s 178; chassis enclosure, e.g., between vents 161 and 163).
Regarding claim 14, Ponnuvel in view of Sri-Jayantha and in view of Soga and in view of Matsui and further in view of Casparian and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui and the teachings of Ponnuvel as modified by Casparian have been discussed above as well.
Ponnuvel teaches the apparatus; the non-transitory machine-readable storage medium (i.e., such as SGRAM, SRAM, RAM, DRAM, VRAM; see for example fig. 1, para. [0034]- [0040]), comprising instructions (i.e., such as if the cutoff value exceeds a corresponding value on the threshold line 408, see for example fig. 4, para. [0072]), to cause at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) to at least calculate (i.e., such as degradation-calculations circuitry 114) a value representative of degradation associated with a thermal interface material (i.e., degradation index value; degradation rate determiner) based on runtime data collected (i.e., such as data/metadata received, see for example para. [0103]) from a compute device (i.e., 100/1000; computing device 1000, see for example fig. 10, para. [0190]), testing (i.e., such as testing data/metadata received, see for example para. [0103]) of thermal interface materials (i.e., such as test parameters that are applied during each state, see for example para. [0052]) having different levels of degradation (i.e., operating time versus thermal degradation in terms of modes, see for example fig. 3, para. [0074]); and trigger generation (i.e., such as trigger circuitry 118) of an alert (i.e., thermal degradation alert; remedial action manager) based on the value (i.e., the of degradation rate determiner circuit; see for example fig. 1, para. [0034]- [0040]).
Sri-Jayantha further teaches the thermal system; wherein to calculate a value representative of degradation (Tij) associated with a thermal interface material (140) between an integrated circuit (110) and a heat sink (130) of the computer device (100), the value (i.e., such as to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); see for example fig. 1B, para. [0086]) based on sensor information (i.e., such as by deploying an array of temperature sensors on the chip surface with (n.times.n) zones, (n.times.n) instantaneous temperature values are measured. Since it is economical to distribute the sensors as far apart as possible, the measured data requires an interpolation scheme to determine the true local and global maximum; see for example fig. 1B, para. [0081]) from the interface circuitry (i.e., 400; see for example fig. 4, para. [0107]) and cause generation of a thermal degradation alert (i.e., such as a state variable model of the thermal system can be driven by current input, and the model output can be organized to provide the corresponding temperature values. Typically, if the model is an exact representation of the real thermal system, then it should be able to compute the temperature distribution without any direct temperature measurements; see for example fig. 1B, para. [0095]) based on the value (i.e., such as to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); see for example fig. 1B, para. [0086]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Casparian furthermore teaches the cooling system; wherein to calculate (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]) a second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) representative of fan inlet/outlet blockage (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]), the second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) based on the sensor information (i.e., such as sensors 114s; see for example para. [0029]) from the interface circuitry (i.e., such as SM Bus, LPC, SPI, etc.; see for example fig. 1, para. [0030]), the sensor information (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) to include one or more fan speed values (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]) (i.e., such as sensors 114s; see for example para. [0029]); and cause generation of the thermal degradation alert (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) based on the second value (i.e., value in terms of data; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature; see for example para. [0035]), the thermal degradation alert (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]) to at least one of i) indicate that a fan inlet/outlet vent (i.e., such as fans 159 inlet/outlet vents 161/163; such as a static value maintained in register 155 of each of CPU 105 and dGPU 120, see for example para. [0030]) associated with the compute device (i.e., such as compute device 100, see for example para. [0074]) is blocked (i.e., such as control may be supplemented with leveraging the existing fan curve and chip temperature lookup table found in NVM 107 and the sensed supplemental cooling air temperature (e.g., as sensed by dock temperature sensor 194a and/or by an optional temperature sensor 194b mounted within chassis 179 to sense ambient temperature at an air inlet 161 and report this sensed temperature directly to CPU 105) entering into the air intake vents 161; see for example fig. 1, para. [0032]), ii) indicate that the compute device (i.e., such as compute device 100, see for example para. [0074]) is operating (i.e., such as to operate at a predefined high-level speed from about 75%-100% PWM, see for example para. [0072]) at a temperature (i.e., the temperature that activates the cooling circuit; (i.e., such as cooling dock control application 129 may be configured to further control overclocking (e.g., enable, disable and/or vary overclocking speed) and/or operating voltage of CPU and/or dGPU based on the selected mode of operation and/or real time CPU operating temperature, e.g., through appropriate APl's); see for example fig. 1, para. [0037]), that can cause thermal degradation (i.e., non-volatile persistent storage 107 or other non-volatile memory may be provided on motherboard 139 to store thermal control parameters that may be accessed by system EC 103 which may in turn control operation of cooling fan/s 159 based on the thermal control parameters and measured temperature information received from sensors 122 and/or 114; see for example fig. 1, para. [0029]), or iii) trigger a self-cleaning operation to be performed (i.e., such as chilling system 175 may itself include a hot-side heat exchanger and associated fan for dissipating collected heat from the chilling system, see for example para. [0041]); and trigger generation (i.e., such as starting bidirectional signal communication) of an alert (i.e., such as starting bidirectional signal communication) when the fan inlet/outlet blockage threshold (i.e., parameters; such as may be set by the component manufacturer below the component thermal throttling temperature threshold as a target component operating temperature) is satisfied (i.e., such as cooled by cold side cooling fan 178, see for example para. [0045]), the alert (i.e., such as starting bidirectional signal communication) to at least one of i) indicate (i.e., such as indicates that a CPU intensive application is running and CPU overclocking would be a beneficial performance gain, see for example para. [0072]) that blockage (i.e., such as to check up the speed of the dock fan/s 178; chassis enclosure, e.g., between vents 161 and 163) of a fan inlet/outlet (i.e., such as fans 159 inlet/outlet vents (161/163)) associated with the compute device (i.e., such as compute device 100, see for example para. [0074]) is negatively impacting operation (i.e., such as cooling dock control application 129 may be configured to further control overclocking (e.g., enable, disable and/or vary overclocking speed) and/or operating voltage of CPU and/or dGPU based on the selected mode of operation and/or real time CPU operating temperature, e.g., through appropriate AP l's) of the compute device (i.e., such as compute device 100, see for example para. [0074]), ii) trigger a self-cleaning operation to be performed on the fan inlet/outlet (i.e., such as chilling system 175 may itself include a hot-side heat exchanger and associated fan for dissipating collected heat from the chilling system, see for example para. [0041]), or iii) indicate the compute device (i.e., such as compute device 100, see for example para. [0074]) is operating at a temperature that can cause damage (i.e., such as cooling dock control application 129 may be configured to further control overclocking (e.g., enable, disable and/or vary overclocking speed) and/or operating voltage of CPU and/or dGPU based on the selected mode of operation and/or real time CPU operating temperature, e.g., through appropriate APl's) to the compute device (i.e., such as compute device 100, see for example para. [0074]).
Regarding claim 15, Ponnuvel in view of Sri-Jayantha and in view of Soga and in view of Matsui and further in view of Casparian and the teachings of Ponnuvel as modified by Sri-Jayantha have been discussed above. Also, the teachings of Ponnuvel as modified by Soga and the teachings of Ponnuvel as modified by Matsui and the teachings of Ponnuvel as modified by Casparian have been discussed above as well.
Ponnuvel teaches the apparatus; the non-transitory machine-readable storage medium (i.e., such as SGRAM, SRAM, RAM, DRAM, VRAM; see for example fig. 1, para. [0034]- [0040]), wherein the instructions (i.e., such as if the cutoff value exceeds a corresponding value on the threshold line 408, see for example fig. 4, para. [0072]) are to cause one or more of the at least one processor circuit (i.e., 100; configuration circuitry, see for example para. [0036]) to trigger generation (i.e., such as trigger circuitry 118) of the first alert (i.e., thermal degradation alert; remedial action manager) based on successful validation comparison (i.e., such as comparing degradations circuitry 116) of the first value (i.e., degradation index value; degradation rate determiner) (i.e., remedial action manager circuitry 118, see for example para. [0174]) to a threshold (i.e., degradation index threshold; degradation rate analyzer), the threshold (i.e., degradation index threshold; degradation rate analyzer) based on one or more thermal degradation curves (i.e., see operation curves in fig. 4; the degradation detection system 104/a test parameter determiner 112, a degradation rate determiner 114, a degradation rate analyzer 116, a remedial action manager 118, and a permanent fault predictor 120; see for example para. [0036]), the one or more thermal degradation curves (i.e., see operation curves in fig. 4; the degradation detection system 104/a test parameter determiner 112, a degradation rate determiner 114, a degradation rate analyzer 116, a remedial action manager 118, and a permanent fault predictor 120; see for example para. [0036]) based on the equation (i.e., the equation of degradation plot in fig. 4, see for example para. [0068]).
Sri-Jayantha further teaches the thermal system; wherein to calculate a value representative of degradation (Tij) associated with a thermal interface material (140) between an integrated circuit (110) and a heat sink (130) of the computer device (100), the value (i.e., such as to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); see for example fig. 1B, para. [0086]) based on sensor information (i.e., such as by deploying an array of temperature sensors on the chip surface with (n.times.n) zones, (n.times.n) instantaneous temperature values are measured. Since it is economical to distribute the sensors as far apart as possible, the measured data requires an interpolation scheme to determine the true local and global maximum; see for example fig. 1B, para. [0081]) from the interface circuitry (i.e., 400; see for example fig. 4, para. [0107]) and cause generation of a thermal degradation alert (i.e., such as a state variable model of the thermal system can be driven by current input, and the model output can be organized to provide the corresponding temperature values. Typically, if the model is an exact representation of the real thermal system, then it should be able to compute the temperature distribution without any direct temperature measurements; see for example fig. 1B, para. [0095]) based on the value (i.e., such as to establish a simple dynamic model to estimate the temperature, Tij, of a rectangle (or square) centered at coordinate (xi, yj); see for example fig. 1B, para. [0086]). (i.e., Also, see for example the parameters formula of the thermal interface material versus various responses to different temperatures thereby calibrating/adjusting the speed of the fan in the cooling module system; fig. 3, para. [0083]).
Soga furthermore teaches the model (i.e., such as model 15b; for instance, numeral 15b indicates a humidity sensor which particularly detects the humidity which affects the life of a substrate having wiring conductors on the basis of the phenomenon of migration. Therefore, it is desirable that the humidity sensor 15b is installed inside the cabinet 1 of the electric appliance. The humidity sensor 15b may be an electric resistance system using the property that the electric resistance of a thin film of hygroscopic material varies with humidity; see for example fig. 2, Col. 9 lines 32+); the thermal interface material (i.e., such as thermal interface material as substrate having wiring conductors on the basis of the phenomenon of migration for chip 5; for instance, numeral 15b indicates a humidity sensor which particularly detects the humidity which affects the life of a substrate having wiring conductors on the basis of the phenomenon of migration. Therefore, it is desirable that the humidity sensor 15b is installed inside the cabinet 1 of the electric appliance. The humidity sensor 15b may be an electric resistance system using the property that the electric resistance of a thin film of hygroscopic material varies with humidity. A numeral 14 indicates a microcomputer. Firstly, the microcomputer control program is written into a memory 18a from an input terminal 27. 18a and 18b consist of a nonvolatile memory such as ROM or EPROM. By the microcomputer 14, the mean temperature T, maximum temperature T max, minimum temperature T min, or temperature difference .DELTA.T (=T max-T min) which is detected from the temperature sensor 15a and the mean humidity, or maximum humidity, or minimum humidity, or humidity change which is detected from the humidity sensor 15b are written and stored in the memory 18b as history data (shown in FIG. 4) of the used condition including the used environment as shown in FIG. 3 in correspondence with the operation time per day, or week, or month and the count of turning ON and OFF which are counted by the timer 15a on the basis of the microcomputer control program which is written into the memory 18a; see for example fig. 2, Col. 9 lines 32+) having different levels of degradation (i.e., such as having different levels of degradation; for instance, there are the temperature cycle and ON-OFF power cycle as a used condition including used environment. In this case, the life of joints (degradation of joints) is compounded and varied. In the LSI module 3 and the printed circuit board body 2a, the degradation degree of the adhesion (adhesive property) between the wiring conductors and insulation material varies according to the used condition including the used environment (humidity, temperature, current flowing through wiring conductors, voltage applied between wiring conductors, energizing time for wiring conductors). The CPU 81 of the terminal device 8 calculates the remaining life which can be guaranteed on the basis of the degradation degree relating to each of components 2a and 3 and joints, against the guaranteed life which is stored in the external storage device 88. Such is calculated on the basis of the history data of the used condition including the used environment (which is read out and inputted from the memory 18b by the transmitter/receiver unit 9) in correspondence with the data 72 relating to the production number and production data (lot number for some products) 12 marked on the printed circuit board body 2a (which is inputted from the optical sensor 11), by the program stored in the memory, and such calculation decides (evaluates) whether the guaranteed remaining life being calculated is a sufficient useable remaining life or not, and outputs the decision (evaluation) result to the display means 84 or the output means 95. The program executes calculation of the remaining life of each of the components 2a and 3 and joints 7 such as solder, and decision of whether or not to reuse them; see for example fig. 9, Col. 9 lines 32+).
Regarding claim 18, is rejected for the same reasons that have already been stated/discussed above in rejected claim 14. {See rejection of claim 14}
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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