DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed August 21, 2026 has been entered.
Claims 1-20 remaining pending in the application.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed August 21, 2026, with respect to the rejection(s) of claims 1-20 under 35 U.S.C 103 have been fully considered in view of the Amendment and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly identified additional prior art in combination with that previously cited. Please see the updated claim rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-6, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng; Chung-Liang (US 2023/0238324; hereinafter Cheng324) in view of Liu; Jun (US 2020/0350014; hereinafter Liu) and Hsiao; Tsung-Chieh et al. US 2024/0421063; hereinafter Hsiao.
Regarding claim 1, Cheng324 discloses an integrated circuit structure (Fig 13B; ¶ [0012-71], entire document), comprising:
a front-side structure (Frontside; Fig 13B) comprising:
a device layer having a plurality of nanowire-based transistors (910,920,930; Figs 9-12,13B; ¶ [0052-57]); and
a plurality of metallization layers (1002,1004,1006,1008,1010,1012; Figs 10,13b; ¶ [0015,0053-54]) above the nanowire-based transistors of the device layer; and
a backside structure (Backside; Fig 13B) below the nanowire-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices (1350, comprising an array of memory cells; Fig 13B; ¶ [0068-75]), the plurality of DRAM devices comprising a capacitor structure (1364; Fig 13B; ¶ [0074,0071]) overlapping with the plurality of nanowire-based transistors.
Cheng324 does not disclose the plurality of DRAM devices comprise a capacitor structure vertically overlapping with and continuous between a stack of nanowires (204 {306}; Figs 2,{9-10},13B{unlabeled}; ¶ [0015,0052]) of a first one of the plurality of nano-wire based transistors (910; Fig 13B), a stack of nanowires of a second one of the plurality of nanowire- based transistors (920; Fig 13B), and a stack of nanowires of a third one of the plurality of nanowire-based transistors (930; Fig 13B).
In the same field of endeavor Liu discloses an integrated circuit structure (400; Fig 4; 0059-62]) comprising a plurality DRAM devices (transistors 448 connected with capacitors 450 {six exemplary DRAM devices shown}; Fig 4; ¶ [0060]) comprising a capacitor structure (comprising a common plate {451; Fig 4; ¶ [0060]} connected with and extending under the plurality of DRAM devices, and a plurality of other electrodes each connected with a node of a respective DRAM device {¶ [0060]}).
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the plurality of DRAM devices comprising the common plate capacitor structure of Liu with the integrated circuit structure of Cheng445 in order to form an integrated circuit structure comprising a plurality of DRAM devices comprising a capacitor structure vertically overlapping with and continuous between (via the common plate 451 of Liu) the stack of nanowires of the a first one of the plurality of nanowire-based transistors, a stack of a second one of a plurality of nanowire-based transistors, and a stack of nanowires of a third one of a plurality of nanowire-based transistors. One would have been motivated to do this as a substitution of one capacitor structure for another, since each of Liu (¶ [0060]) and Cheng324 (¶ [0071]) discloses a variety of capacitor structures may be used. One would have had a reasonable expectation of success because of Liu and Cheng324’s explicit disclosure of a variety of suitable capacitor structures, and because the common plate structure is well-known in the art.
Cheng324 in view of Liu does not disclose the backside structure comprising a second capacitor structure below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer.
In the same field of endeavor, Hsiao discloses a semiconductor structure (refer to Fig 15), comprising a substrate (201; ¶ [0020]) having semiconductor devices (202; ¶ [0020]) on a front side of the substrate (see 201,202,205; Fig 2; ¶ [0020]; the substrate is flipped to have the front side facing down in Fig 15) and a capacitor structure (812; ¶ [0034,0038]) over (or below with respect to the front side of the substrate) the semiconductor devices and near to bond pads (516; ¶ [0037]) through which the semiconductor structure receives input power signals, to act as filters to prevent undesirable signal noise from reaching the semiconductor devices (¶ [0038]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included such capacitors (decoupling capacitors) in the integrated circuit structure of Cheng324 in view of Liu, similarly positioning the capacitors close to external connection bond pads to ensure signals do not bypass the capacitors (Hsiao; ¶ [0018]; see also alternate positioning of the capacitors close to the backside (Figs 24,26,27); in keeping with Hsiao’s disclosure, in order that signals travel through decoupling capacitors before traveling to devices of the integrated circuit structure, it would be obvious for the backside structure to comprise a second capacitor structure (decoupling capacitor) below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer. One may have been motivated to do this for the same reason disclosed by Hsiao, that is, to filter noise and act as signal conditioning for the integrated circuit structure (Hsiao; ¶ [0003-5, 0038]). One would have had a reasonable expectation of success because of the similar back-end interconnect structures of Cheng324 and Hsiao, well known in the art.
Regarding claim 3, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 1, wherein the device layer of the front-side structure further includes a trench contact, a gate contact (902/1002; Figs 9-11,13B; ¶ [0047,0057]) or a contact via.
Regarding claim 5, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 1, wherein the nanowire-based transistors device layer are logic nanowire-based transistors (Cheng324; transistors of the logic portion; ¶ [0057]).
Regarding claim 6, Cheng324 discloses an integrated circuit structure (Fig 13B; ¶ [0012-71], entire document), comprising:
a front-side structure (Frontside; Fig 13B) comprising:
a device layer having a plurality of fin-based transistors (910,920,930, comprising fin structures 400 {Figs 4-8; ¶ [0025]}; Figs 9-12,13B; ¶ [0052-57]); and
a plurality of metallization layers (1002,1004,1006,1008,1010,1012; Figs 10,13b; ¶ [0015,0053-54]) above the fin-based transistors of the device layer; and
a backside structure (Backside; Fig 13B) below the fin-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices (1350, comprising an array of memory cells; Fig 13B; ¶ [0068-75]), the plurality of DRAM devices comprising a capacitor structure (1364; Fig 13B; ¶ [0074,0071]) overlapping with the plurality of fin-based transistors.
Cheng324 does not disclose the plurality of DRAM devices comprise a capacitor structure vertically overlapping with and continuous between a fin of (204 {306}; Figs 2,{9-10},13B{unlabeled}; ¶ [0015,0052]) of a first one of the plurality of fin-based transistors (910; Fig 13B), a fin of a second one of the plurality of fin-based transistors (920; Fig 13B), and a fin of a third one of the plurality of fin-based transistors (930; Fig 13B).
In the same field of endeavor Liu discloses an integrated circuit structure (400; Fig 4; 0059-62]) comprising a plurality DRAM devices (transistors 448 connected with capacitors 450 {six exemplary DRAM devices shown}; Fig 4; ¶ [0060]) comprising a capacitor structure (comprising a common plate {451; Fig 4; ¶ [0060]} connected with and extending under the plurality of DRAM devices, and a plurality of other electrodes each connected with a node of a respective DRAM device {¶ [0060]}).
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the plurality of DRAM devices comprising the common plate capacitor structure of Liu with the integrated circuit structure of Cheng445 in order to form an integrated circuit structure comprising a plurality of DRAM devices comprising a capacitor structure vertically overlapping with and continuous between (via the common plate 451 of Liu) the fin of the a first one of the plurality of fin-based transistors, a fin of a plurality of fin-based transistors, and a fin of a third one of a plurality of fin-based transistors. One would have been motivated to do this as a substitution of one capacitor structure for another, since each of Liu (¶ [0060]) and Cheng324 (¶ [0071]) discloses a variety of capacitor structures may be used. One would have had a reasonable expectation of success because of Liu and Cheng324’s explicit disclosure of a variety of suitable capacitor structures, and because the common plate structure is well-known in the art.
Cheng324 in view of Liu does not disclose the backside structure comprising a second capacitor structure below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer.
In the same field of endeavor, Hsiao discloses a semiconductor structure (refer to Fig 15), comprising a substrate (201; ¶ [0020]) having semiconductor devices (202; ¶ [0020]) on a front side of the substrate (see 201,202,205; Fig 2; ¶ [0020]; the substrate is flipped to have the front side facing down in Fig 15) and a capacitor structure (812; ¶ [0034,0038]) over (or below with respect to the front side of the substrate) the semiconductor devices and near to bond pads (516; ¶ [0037]) through which the semiconductor structure receives input power signals, to act as filters to prevent undesirable signal noise from reaching the semiconductor devices (¶ [0038]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included such capacitors (decoupling capacitors) in the integrated circuit structure of Cheng324 in view of Liu, similarly positioning the capacitors close to external connection bond pads to ensure signals do not bypass the capacitors (Hsiao; ¶ [0018]; see also alternate positioning of the capacitors close to the backside (Figs 24,26,27); in keeping with Hsiao’s disclosure, in order that signals travel through decoupling capacitors before traveling to devices of the integrated circuit structure, it would be obvious for the backside structure to comprise a second capacitor structure (decoupling capacitor) below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer. One may have been motivated to do this for the same reason disclosed by Hsiao, that is, to filter noise and act as signal conditioning for the integrated circuit structure (Hsiao; ¶ [0003-5, 0038]). One would have had a reasonable expectation of success because of the similar back-end interconnect structures of Cheng324 and Hsiao, well known in the art.
Regarding claim 8, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 6, wherein the device layer of the front-side structure further includes a trench contact, a gate contact (902/1002; Figs 9-11,13B; ¶ [0047,0057]) or a contact via.
Regarding claim 10, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 6, wherein the fin-based transistors device layer are logic fin-based transistors (Cheng324; transistors of the logic portion; ¶ [0057]).
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng; Chung-Liang (US 2023/0238324; hereinafter Cheng324) in view of Liu; Jun (US 2020/0350014; hereinafter Liu) and Hsiao; Tsung-Chieh et al. US 2024/0421063; hereinafter Hsiao, and further in view of Yu; Li-Zhen et al. (US 2022/0037192; hereinafter Yu).
Regarding claim 2, Cheng in view of Liu and Hsiao discloses the integrated circuit structure of claim 1, wherein the backside structure includes a stack of backside conductive structures (Cheng324; 1362; Fig 13B; ¶ [0073 {0053-56}]).
Cheng324 in view of Liu does not disclose the stack of backside conductive structures terminate at a conductive bump.
In the same field of endeavor, Yu discloses an integrated circuit structure (Figs. 40A-40C) comprising:
a front-side structure comprising: a device layer (109; Figs 40A-40C; ¶ [0065]) having a plurality of nanowire-based transistors (109, comprising nanowire-based FETs; Figs 40A-40C; ¶ [0011, 0065]); and a plurality of metallization layers (122; Fig 40A-40C; ¶ [0066]) above the nanowire-based transistors of the device layer; and a backside structure (164; Figs 40A-40C; ¶ [0065]) below the nanowire-based transistors of the device layer,
wherein the backside structure includes a stack of backside conductive structures (162, 168; Figs 40A-40C; ¶ [0104-106]) that terminate at a conductive bump (170; Figs 40A-40C; ¶ [0106]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the conductive bump of Yu with the integrated circuit structure of Cheng324 as applied to claim 1. One would have been motivated to do this in order to provide input/output connections to other electrical components (Yu; ¶ [0106]), as is well known and common in the art, because Cheng324 silent in regard to how the device may be connected for use. One would have had a reasonable expectation of success because of the similarity in the structures and endeavors of Cheng324 and Yu.
Regarding claim 7, Cheng in view of Liu and Hsiao discloses the integrated circuit structure of claim 6, wherein the backside structure includes a stack of backside conductive structures (Cheng324; 1362; Fig 13B; ¶ [0073 {0053-56}]).
Cheng324 in view of Liu does not disclose the stack of backside conductive structures terminate at a conductive bump.
In the same field of endeavor, Yu discloses an integrated circuit structure (Figs. 40A-40C) comprising:
a front-side structure comprising: a device layer (109; Figs 40A-40C; ¶ [0065]) having a plurality of nanowire-based transistors (109, comprising nanowire-based FETs; Figs 40A-40C; ¶ [0011, 0065]); and a plurality of metallization layers (122; Fig 40A-40C; ¶ [0066]) above the nanowire-based transistors of the device layer; and a backside structure (164; Figs 40A-40C; ¶ [0065]) below the nanowire-based transistors of the device layer,
wherein the backside structure includes a stack of backside conductive structures (162, 168; Figs 40A-40C; ¶ [0104-106]) that terminate at a conductive bump (170; Figs 40A-40C; ¶ [0106]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the conductive bump of Yu with the integrated circuit structure of Cheng324 as applied to claim 1. One would have been motivated to do this in order to provide input/output connections to other electrical components (Yu; ¶ [0106]), as is well known and common in the art, because Cheng324 silent in regard to how the device may be connected for use. One would have had a reasonable expectation of success because of the similarity in the structures and endeavors of Cheng324 and Yu.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng; Chung-Liang (US 2023/0238324; hereinafter Cheng324) in view of Liu; Jun (US 2020/0350014; hereinafter Liu) and Hsiao; Tsung-Chieh et al. US 2024/0421063; hereinafter Hsiao, and further in view of Cheng; Chung-Liang (US 2023/0065446; hereinafter Cheng446).
Regarding claim 4, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 1, but does not disclose wherein the front-side structure comprises a deep via layer between the nanowire-based transistors of the device layer and the DRAM devices of the backside structure.
In the same field of endeavor, Cheng446 discloses a similar integrated circuit structure (2; Fig 30; ¶ [100-107], entire document) wherein a front-side structure (GAAP, SP; Fig 30; ¶ [0025,0101]) comprises a deep via layer (EVP; Fig 30; ¶ [0106]) between nanowire-based transistors (10; Fig 30; ¶ [0101, {0043-76]) of a device layer and DRAM devices (TMF connected with MIMP, forming a 1T1C DRAM; Fig 30; ¶ [0025,0118]) of a backside structure (TP,MIMP; Fig 30; ¶ [0025,0101-115]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have configured the device of claim 1 with a similar deep via structure. One may have been motivated to do this, as an alternate or simpler connection method (versus Cheng324, making the connection through a via {1372; Fig 13B} and additional conductive structure), or in order to increase device density (Cheng446; ¶ [0030]) or to avoid problems such as “corner” stresses (Cheng446; ¶ [0099]). One would have had a reasonable expectation of success because of the similar structures of Cheng324 and Cheng446 in the similar endeavors.
Regarding claim 9, Cheng324 in view of Liu and Hsiao discloses the integrated circuit structure of claim 6, but does not disclose wherein the front-side structure comprises a deep via layer between the fin-based transistors of the device layer and the DRAM devices of the backside structure.
In the same field of endeavor, Cheng446 discloses a similar integrated circuit structure (2; Fig 30; ¶ [100-107], entire document) wherein a front-side structure (GAAP, SP; Fig 30; ¶ [0025,0101]) comprises a deep via layer (EVP; Fig 30; ¶ [0106]) between fin-based transistors (10; Fig 30; ¶ [0101, {0043-76]) of a device layer and DRAM devices (TMF connected with MIMP, forming a 1T1C DRAM; Fig 30; ¶ [0025,0118]) of a backside structure (TP,MIMP; Fig 30; ¶ [0025,0101-115]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have configured the device of claim 6 with a similar deep via structure. One may have been motivated to do this, as an alternate or simpler connection method (versus Cheng324, making the connection through a via {1372; Fig 13B} and additional conductive structure), or in order to increase device density (Cheng446; ¶ [0030]) or to avoid problems such as “corner” stresses (Cheng446; ¶ [0099]). One would have had a reasonable expectation of success because of the similar structures of Cheng324 and Cheng446 in the similar endeavors.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng; Chung-Liang (US 2023/0238324; hereinafter Cheng324) in view of Liu; Jun (US 2020/0350014; hereinafter Liu) and Hsiao; Tsung-Chieh et al. US 2024/0421063; hereinafter Hsiao, and further in view of Weber; Cory E. et al. (US 2021/0074703; hereinafter Weber).
Regarding claim 11, Cheng324 discloses an integrated circuit structure (Fig 13B; ¶ [0012-71], entire document), comprising:
a front-side structure (Frontside; Fig 13B) comprising:
a device layer having a plurality of nanowire-based transistors (910,920,930; Figs 9-12,13B; ¶ [0052-57]); and
a plurality of metallization layers (1002,1004,1006,1008,1010,1012; Figs 10,13b; ¶ [0015,0053-54]) above the nanowire-based transistors of the device layer; and
a backside structure (Backside; Fig 13B) below the nanowire-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices (1350, comprising an array of memory cells; Fig 13B; ¶ [0068-75]), the plurality of DRAM devices comprising a capacitor structure (1364; Fig 13B; ¶ [0074,0071]) overlapping with the plurality of nanowire-based transistors.
Cheng324 does not disclose the plurality of DRAM devices comprise a capacitor structure vertically overlapping with and continuous between a stack of nanowires (204 {306}; Figs 2,{9-10},13B{unlabeled}; ¶ [0015,0052]) of a first one of the plurality of nano-wire based transistors (910; Fig 13B), a stack of nanowires of a second one of the plurality of nanowire- based transistors (920; Fig 13B), and a stack of nanowires of a third one of the plurality of nanowire-based transistors (930; Fig 13B).
In the same field of endeavor Liu discloses an integrated circuit structure (400; Fig 4; 0059-62]) comprising a plurality DRAM devices (transistors 448 connected with capacitors 450 {six exemplary DRAM devices shown}; Fig 4; ¶ [0060]) comprising a capacitor structure (comprising a common plate {451; Fig 4; ¶ [0060]} connected with and extending under the plurality of DRAM devices, and a plurality of other electrodes each connected with a node of a respective DRAM device {¶ [0060]}).
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the plurality of DRAM devices comprising the common plate capacitor structure of Liu with the integrated circuit structure of Cheng445 in order to form an integrated circuit structure comprising a plurality of DRAM devices comprising a capacitor structure vertically overlapping with and continuous between (via the common plate 451 of Liu) the stack of nanowires of the a first one of the plurality of nanowire-based transistors, a stack of a second one of a plurality of nanowire-based transistors, and a stack of nanowires of a third one of a plurality of nanowire-based transistors. One would have been motivated to do this as a substitution of one capacitor structure for another, since each of Liu (¶ [0060]) and Cheng324 (¶ [0071]) discloses a variety of capacitor structures may be used. One would have had a reasonable expectation of success because of Liu and Cheng324’s explicit disclosure of a variety of suitable capacitor structures, and because the common plate structure is well-known in the art.
Cheng324 in view of Liu does not disclose the backside structure comprising a second capacitor structure below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer.
In the same field of endeavor, Hsiao discloses a semiconductor structure (refer to Fig 15), comprising a substrate (201; ¶ [0020]) having semiconductor devices (202; ¶ [0020]) on a front side of the substrate (see 201,202,205; Fig 2; ¶ [0020]; the substrate is flipped to have the front side facing down in Fig 15) and a capacitor structure (812; ¶ [0034,0038]) over (or below with respect to the front side of the substrate) the semiconductor devices and near to bond pads (516; ¶ [0037]) through which the semiconductor structure receives input power signals, to act as filters to prevent undesirable signal noise from reaching the semiconductor devices (¶ [0038]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included such capacitors (decoupling capacitors) in the integrated circuit structure of Cheng324 in view of Liu, similarly positioning the capacitors close to external connection bond pads to ensure signals do not bypass the capacitors (Hsiao; ¶ [0018]; see also alternate positioning of the capacitors close to the backside (Figs 24,26,27); in keeping with Hsiao’s disclosure, in order that signals travel through decoupling capacitors before traveling to devices of the integrated circuit structure, it would be obvious for the backside structure to comprise a second capacitor structure (decoupling capacitor) below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer. One may have been motivated to do this for the same reason disclosed by Hsiao, that is, to filter noise and act as signal conditioning for the integrated circuit structure (Hsiao; ¶ [0003-5, 0038]). One would have had a reasonable expectation of success because of the similar back-end interconnect structures of Cheng324 and Hsiao, well known in the art.
None of Cheng, Liu, and Hsiao disclose a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure.
In the same field of endeavor, Weber discloses a computing device (900; Fig 9; ¶ [0107]), comprising:
a board (902; Fig 9; ¶ [0107]); and
a component (processor 904, communication chip 906, DRAM, for example; ¶ [0107-108]) coupled to the board, the component including an integrated circuit structure (integrated circuit die; ¶ [0110-111]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the integrated circuit structure of Cheng in view of Liu and Hsiao with the computing device of Weber. One would have been motivated to do this in order to take advantage of the higher density memory cells (Cheng; ¶ [0012]) and efficient operation (Cheng; ¶ [0066]) provided by the DRAM device of Cheng in view of Liu for the computing device of Weber. One would have had a reasonable expectation of success because Weber discloses that a DRAM component may be included the board 902 of the computing device 900.
Regarding claim 12, Cheng324 in view of Liu, Hsiao, and Weber discloses the computing device of claim 11, further comprising: a memory coupled to the board (Weber; DRAM; ¶ [0108]).
Regarding claim 13, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 11, further comprising: a communication chip coupled to the board (Weber; communication chip 906; ¶ [0107-108]).
Regarding claim 14, Cheng324 in view of Liu, Hsiao, and Weber discloses the computing device of claim 11, wherein the component is a packaged integrated circuit die (Weber, 904, 906; ¶ [0110-111]).
Regarding claim 15, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 11, wherein the component is selected from the group consisting of a processor (Weber; processor 904; ¶ [0107-108]), a communications chip (Weber; communication chip 906; ¶ [0107-108]), and a digital signal processor (Weber; ¶ [0108]).
Regarding claim 16, Cheng324 discloses an integrated circuit structure (Fig 13B; ¶ [0012-71], entire document), comprising:
a front-side structure (Frontside; Fig 13B) comprising:
a device layer having a plurality of fin-based transistors (910,920,930, comprising fin structures 400 {Figs 4-8; ¶ [0025]}; Figs 9-12,13B; ¶ [0052-57]); and
a plurality of metallization layers (1002,1004,1006,1008,1010,1012; Figs 10,13b; ¶ [0015,0053-54]) above the fin-based transistors of the device layer; and
a backside structure (Backside; Fig 13B) below the fin-based transistors of the device layer, the backside structure including a plurality of dynamic random access memory (DRAM) devices (1350, comprising an array of memory cells; Fig 13B; ¶ [0068-75]), the plurality of DRAM devices comprising a capacitor structure (1364; Fig 13B; ¶ [0074,0071]) overlapping with the plurality of fin-based transistors.
Cheng324 does not disclose the plurality of DRAM devices comprise a capacitor structure vertically overlapping with and continuous between a fin of (204 {306}; Figs 2,{9-10},13B{unlabeled}; ¶ [0015,0052]) of a first one of the plurality of fin-based transistors (910; Fig 13B), a fin of a second one of the plurality of fin-based transistors (920; Fig 13B), and a fin of a third one of the plurality of fin-based transistors (930; Fig 13B).
In the same field of endeavor Liu discloses an integrated circuit structure (400; Fig 4; 0059-62]) comprising a plurality DRAM devices (transistors 448 connected with capacitors 450 {six exemplary DRAM devices shown}; Fig 4; ¶ [0060]) comprising a capacitor structure (comprising a common plate {451; Fig 4; ¶ [0060]} connected with and extending under the plurality of DRAM devices, and a plurality of other electrodes each connected with a node of a respective DRAM device {¶ [0060]}).
Accordingly, it would have been obvious to a person having ordinary skill in the art to combine the plurality of DRAM devices comprising the common plate capacitor structure of Liu with the integrated circuit structure of Cheng445 in order to form an integrated circuit structure comprising a plurality of DRAM devices comprising a capacitor structure vertically overlapping with and continuous between (via the common plate 451 of Liu) the fin of the a first one of the plurality of fin-based transistors, a fin of a plurality of fin-based transistors, and a fin of a third one of a plurality of fin-based transistors. One would have been motivated to do this as a substitution of one capacitor structure for another, since each of Liu (¶ [0060]) and Cheng324 (¶ [0071]) discloses a variety of capacitor structures may be used. One would have had a reasonable expectation of success because of Liu and Cheng324’s explicit disclosure of a variety of suitable capacitor structures, and because the common plate structure is well-known in the art.
Cheng324 in view of Liu does not disclose the backside structure comprising a second capacitor structure below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer.
In the same field of endeavor, Hsiao discloses a semiconductor structure (refer to Fig 15), comprising a substrate (201; ¶ [0020]) having semiconductor devices (202; ¶ [0020]) on a front side of the substrate (see 201,202,205; Fig 2; ¶ [0020]; the substrate is flipped to have the front side facing down in Fig 15) and a capacitor structure (812; ¶ [0034,0038]) over (or below with respect to the front side of the substrate) the semiconductor devices and near to bond pads (516; ¶ [0037]) through which the semiconductor structure receives input power signals, to act as filters to prevent undesirable signal noise from reaching the semiconductor devices (¶ [0038]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have included such capacitors (decoupling capacitors) in the integrated circuit structure of Cheng324 in view of Liu, similarly positioning the capacitors close to external connection bond pads to ensure signals do not bypass the capacitors (Hsiao; ¶ [0018]; see also alternate positioning of the capacitors close to the backside (Figs 24,26,27); in keeping with Hsiao’s disclosure, in order that signals travel through decoupling capacitors before traveling to devices of the integrated circuit structure, it would be obvious for the backside structure to comprise a second capacitor structure (decoupling capacitor) below the plurality of DRAM devices such that the first capacitor structure is vertically intervening between the second capacitor structure and the nanowire-based transistors of the device layer. One may have been motivated to do this for the same reason disclosed by Hsiao, that is, to filter noise and act as signal conditioning for the integrated circuit structure (Hsiao; ¶ [0003-5, 0038]). One would have had a reasonable expectation of success because of the similar back-end interconnect structures of Cheng324 and Hsiao, well known in the art.
None of Cheng324, Liu, and Hsiao disclose a computing device, comprising:
a board; and
a component coupled to the board, the component including the integrated circuit structure.
In the same field of endeavor, Weber discloses a computing device (900; Fig 9; ¶ [0107]), comprising:
a board (902; Fig 9; ¶ [0107]); and
a component (processor 904, communication chip 906, DRAM, for example; ¶ [0107-108]) coupled to the board, the component including an integrated circuit structure (integrated circuit die; ¶ [0110-111]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined the integrated circuit structure of Cheng in view of Liu with the computing device of Weber. One would have been motivated to do this in order to take advantage of the higher density memory cells (Cheng; ¶ [0012]) and efficient operation (Cheng; ¶ [0066]) provided by the DRAM device of Cheng in view of Liu for the computing device of Weber. One would have had a reasonable expectation of success because Weber discloses that a DRAM component may be included the board 902 of the computing device 900.
Regarding claim 17, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 16, further comprising: a memory coupled to the board (Weber; DRAM; ¶ [0108]).
Regarding claim 18, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 16, further comprising: a communication chip coupled to the board (Weber; communication chip 906; ¶ [0107-108]).
Regarding claim 19, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 16, wherein the component is a packaged integrated circuit die (Weber, 904, 906; ¶ [0110-111]).
Regarding claim 20, Cheng324 in view of Liu, Hsiao and Weber discloses the computing device of claim 16, wherein the component is selected from the group consisting of a processor (Weber; processor 904; ¶ [0107-108]), a communications chip (communication chip 906; ¶ [0107-108]), and a digital signal processor (¶ [0108]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.A.K./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
