DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/20/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments regarding the limitation “the second transistor consists of a single active layer” (Applicant’s remarks page 9) not being taught by prior art document US 20220190170 A1 (Lee et al) is acknowledged. Lee did not clearly show or suggest a pixel circuit structure wherein one transistor has a multilayer active layer, while another transistor in the same pixel circuit has a single-layer active layer.
However, after further search and consideration of the prior art, US 20150153599 A1 (Yamazaki et al) is found to suggest the claimed limitation.
Additionally, the phrase “the second transistor consists of a single active layer” is found to introduce an issue of indefiniteness into claims 1, 20, and their dependent claims which will be described in more detail below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 10-11, 13-15, and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1 and 20, the phrase “the second transistor consists of a single active layer” requires that the second transistor cannot further include the essential transistor elements of a source, drain, and gate, because it only “consists of” “a single active layer”. By lacking further essential features, the claimed second transistor cannot function as a transistor.
For purposes of examination in the merits, the limitation will be understood to convey “the second transistor comprises an active region consisting of a single layer, and the second transistor comprises no further active regions other than the active region”.
Due to their dependence on claim 1, claims 10-11, 13-15, and 17-19 are also rejected on this basis.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 10 depends on canceled claim 2, and is therefore rejected as incomplete (MPEP 608.01(n) V). Claim 10 will be interpreted as though it depends on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 10-11, 14, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20220190170 A1 (Lee et al hereinafter Lee) in view of US 20210126115 A1 (Koezuka et al hereinafter Koezuka) and US 20150153599 A1 (Yamazaki et al hereinafter Yamazaki).
Regarding claim 1, Lee discloses a display panel (display apparatus 700 of FIG. 12 includes display panel 310, which further includes transistors 200 of FIG. 5 ¶ [0166-0177]), comprising: a substrate (FIG. 5, substrate 110 ¶ [0070]); and a plurality of pixel circuits (FIGS. 12-13, pixels P include pixel circuits ¶ [0178-0180]) located on a side of the substrate (FIG. 5, transistors such as transistor 200 are located on an upper side of substrate 110; those transistors may be applied to TR1 or TR2 of the pixel circuit of FIG. 13 ¶ [0181-0182]; FIG. 17 presents an alternative pixel circuit configuration ¶ [0230-0241]), wherein each of at least part of the plurality of pixel circuits comprises a first transistor (FIG. 5, transistor 200 ¶ [0135, 0182]); the first transistor comprises at least two active layers (FIG. 5, active layer 130 includes oxide semiconductor layers 131 and 132 ¶ [0136]); wherein the at least two active layers comprise a first active layer (FIG. 5, oxide semiconductor layer 132 ¶ [0136]) and a second active layer (FIG. 5, oxide semiconductor layer 131 ¶ [0136]) which are laminated (FIG. 5, oxide semiconductor layers 131 and 132 are laminated),
wherein the first transistor further comprises a first gate (FIG. 5, gate electrode 150 ¶ [0140]); and the first gate is located on a side of the first active layer facing away from the second active layer (FIG. 5, gate electrode 150 is on the upper side of oxide layer 132, which is away from oxide layer 131), wherein the first transistor further comprises a second gate (FIG. 5, auxiliary electrode 140 ¶ [0141], which may function as a second gate ¶ [0107]); and the second gate is located on a side of the second active layer facing away from the first active layer (FIG. 5, auxiliary electrode 140 is on a lower side of oxide layer 131 away from oxide layer 132),
wherein the display panel further comprises: a first gate insulating layer (FIG. 5, gate insulating film 155 between oxide layer 132 and gate electrode 150 ¶ [0084]) located between the first gate and the first active layer; and a second gate insulating layer (FIG. 5, second buffer layer 122 between oxide layer 131 and auxiliary electrode 140 ¶ [0137]) located between the second gate and the second active layer;
wherein the each of at least part of the plurality of pixel circuits (in this case, the pixel circuit of FIG. 17 is used) comprising the first transistor is a first pixel circuit (FIG. 17’s pixel circuit may comprise the transistor 200 of FIG. 5 ¶ [0241], e.g. at transistor TR1 of the circuit to function as the first transistor), the first pixel circuit further comprises a second transistor (transistor 200 of FIG. 5 applied as TR3 of FIG. 17), the second transistor comprises a single active layer, which is a fourth active layer (FIG. 5, oxide semiconductor layer 131 ¶ [0136]), and the fourth active layer is disposed in a same layer as the second active layer or the fourth active layer is disposed in a same layer as the first active layer (FIG. 5, oxide semiconductor layer 131 of TR3 is disposed in the same layer as oxide semiconductor layer 131 of TR1, applied as the first transistor in the context of the pixel circuit of FIG. 17, since they both use the structure of transistor 200 of FIG. 5 ¶ [0241])
wherein the first pixel circuit further comprises a driving transistor (FIG. 17, TR2 is a driving transistor ¶ [0239]); and in a same first pixel circuit, the second transistor is configured to transmit a reset signal to the driving transistor to reset the driving transistor (FIG. 17, TR3 resets the driving transistor TR2 by connecting to the reference voltage Vref ¶ [0220]), and the first transistor is configured to transmit a compensation signal to the driving transistor to perform a threshold compensation on the driving transistor (FIG. 17, TR1 is connected to the Vdata voltage source ¶ [0184], and a person of ordinary skill in the art could send any signal, such as a compensation signal, through that voltage source).
Lee does not explicitly state that the two active layers have different mobilities, or that a mobility of the first active layer is larger than a mobility of the second active layer, comparing mobility of the two oxide semiconductor layers not being a parameter of particular importance to the disclosure of their invention; Lee also did not explicitly state that the second transistor consists of a single active layer, or that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer.
Regarding the limitations requiring that the two active layers have different mobilities, or that a mobility of the first active layer is larger than a mobility of the second active layer, Lee does suggest a number of different materials being suitable for each of the oxide semiconductor layers (layer 131 may be IGZO, for example ¶ [0138], and layer 132 may be IGZTO, for example ¶ [0139]). Those materials have different mobilities when compared to each other, and a person of ordinary skill in the art would recognize that the mobility of the active layers affects the current that passes through the transistor, the mobilities therefore being result-effective variables. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the materials selected for use in the two oxide semiconductor layers of Lee by routine experimentation when selecting the materials, and in so doing would have found it obvious to arrive at a configuration wherein, for example, the first active layer 132 is IGZTO and the second active layer 131 is IGZO; doing so could achieve desirable current properties in the transistor while using the materials explicitly suggested by Lee. That being the case, the two active layers have different mobilities, and a mobility of the first active layer is larger than a mobility of the second active layer.
Lee does not explicitly teach that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer, or that the second transistor consists of a single active layer.
However, Koezuka discloses a display device (a display device including transistor 100A of FIGS. 3A-3C ¶ [0121-0123]) comprising a first gate insulating layer (FIG. 3B, gate insulating layer 110 ¶ [0123]) and a second gate insulating layer (FIG. 3B, insulating layer 103 functions as a gate insulating layer ¶ [0123]). Koezuka also suggests that a dielectric constant of a first gate insulating layer (first gate insulating layer 110 can be hafnium oxide, having a higher dielectric constant than silicon oxide or silicon oxynitride ¶ [0153]) is larger than a dielectric constant of a second gate insulating layer (second gate dielectric layer 103 can be silicon oxide or silicon oxynitride ¶ [0144]). Koezuka further teaches that leakage current due to tunnel current can be inhibited with a hafnium oxide gate insulating layer for the first gate insulating layer (¶ [0153]) and when selecting a material for the second gate insulating layer, a person of ordinary skill in the art would have found it obvious to vary the material used via routine experimentation based on the suggested materials for layer 103 (¶ [0144]), due to considerations of materials cost from changing market conditions. For example, the second gate insulating layer 103 may be formed of silicon oxide or silicon oxynitride, which has a lower dielectric constant than the hafnium oxide of the first gate insulating layer 110.
Lee and Koezuka both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka such that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer, in order to inhibit the leakage current due to tunnel current in the first gate insulating layer, and in consideration of materials cost from changing market conditions for the second gate insulating layer.
Lee in view of Koezuka does not disclose that the second transistor consists of a single active layer.
However, Yamazaki discloses a display device (the device of FIG. 35) comprising a first transistor (FIG. 34, transistor 10kb, which may be used in place of transistor 10nb pictured in FIG. 35 ¶ [0378]) and a second transistor (FIG. 35, transistor 10m ¶ [0117]), wherein the first transistor includes a first active layer (FIG. 34, oxide semiconductor film 82 ¶ [0113-0114]) and a second active layer (FIG. 34, oxide semiconductor film 81 ¶ [0176]), and wherein an active region of the second transistor consists a single active layer (FIG. 35, oxide layer 84 ¶ [0113-0114]). Yamazaki also teaches that second transistor 10m has low off-state current (¶ [0117]) and that a multilayer active region such as that in first transistor 10kb has a channel which can enable high speed operation (¶ [0351, 0361-0363]). As Yamazaki indicates, different transistors of a same pixel circuit can be optimized for different functions based on having differing active layer configurations.
Lee, Koezuka, and Yamazaki all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka further in view of Yamazaki such that the second transistor consists of a single active layer, in order to optimize the active layers of the different transistors in the pixel circuit for different functions.
Regarding claim 10, Lee in view of Koezuka and Yamazaki discloses the limitations of claim 2 (claim 1) as detailed above, and Lee further discloses a plurality of light-emitting elements (Lee FIGS. 13-15, pixels include display elements 710 ¶ [0178-0187]) located on a side of the substrate (Lee FIG. 15, an upper side of substrate 110), and the plurality of pixel circuits is electrically connected to the plurality of light-emitting elements (Lee FIG. 15, source electrode S2 connects the pixel circuit to display element 710 ¶ [0186]; transistor TR2 may be transistor 200 of FIG. 5 ¶ [0182]); wherein the first gate is configured to receive a data signal (Lee FIG. 15, gate G2 of transistor TR2 receives a data voltage Vdata from data line DL ¶ [0186]), and the first transistor is configured to provide a driving current for the light-emitting elements according to the data signal (Lee FIG. 15, transistor TR2 supplies driving voltage to display element 710 ¶ [0185]).
Regarding claim 11, Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 as detailed above, and Lee further discloses that the second gate is configured to receive a scanning signal (FIG. 5, auxiliary electrode 140 may receive a threshold voltage Vth ¶ [0107]) and the first transistor is configured to be turned on or turned off under control of the scanning signal (the application of Vth on auxiliary electrode 140 is comparable to a gate-ON voltage which may turn the first transistor on or off ¶ [0107]).
Regarding claim 14, Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 as detailed above, and Lee further discloses that each of the at least two active layers of the first transistor comprises an oxide semiconductor (Lee ¶ [0138-0139]); and the oxide semiconductor comprises InGaXO, wherein X comprises one of Zn, Zn-Sn and Sn, and X in the first active layer is different from X in the second active layer (in view of the foregoing analysis with regards to claim 1 above, the first active layer’s “X” is Zn-Sn, and the second active layer’s “X” is Zn, Lee ¶ [0138-0139]).
Regarding claim 18, Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 as detailed above, and Lee further discloses a light shielding layer (Lee FIG. 5, light shielding layer 120 ¶ [0071]) located between the plurality of pixel circuits and the substrate (Lee FIG. 5, light shielding layer 120 is between transistor of the pixel circuit and substrate 110), wherein the light shielding layer comprises a light shielding structure (light shielding layer 120 is a structure that shields the active layer from incident light, Lee ¶ [0071]) and the light shielding structure overlaps the active layer in a thickness direction of the display panel (Lee FIG. 5, light shielding layer 120 overlaps active layer 130 along a vertical thickness direction).
Regarding claim 20, Lee discloses a display device (FIG. 12, display apparatus 700), comprising a display panel (display apparatus 700 of FIG. 12 includes display panel 310, which further includes transistors 200 of FIG. 5 ¶ [0166-0177]), wherein the display panel comprises: a substrate (FIG. 5, substrate 110 ¶ [0070]); and a plurality of pixel circuits (FIGS. 12-13, pixels P include pixel circuits ¶ [0178-0180]) located on a side of the substrate (FIG. 5, transistors such as transistor 200 are located on an upper side of substrate 110; those transistors may be applied to TR1 or TR2 of the pixel circuit of FIG. 13 ¶ [0181-0182]; FIG. 17 presents an alternative pixel circuit configuration ¶ [0230-0241]), wherein each of at least part of the plurality of pixel circuits comprises a first transistor (FIG. 5, transistor 200 ¶ [0135, 0182]); the first transistor comprises at least two active layers (FIG. 5, active layer 130 includes oxide semiconductor layers 131 and 132 ¶ [0136]); wherein the at least two active layers comprise a first active layer (FIG. 5, oxide semiconductor layer 132 ¶ [0136]) and a second active layer (FIG. 5, oxide semiconductor layer 131 ¶ [0136]) which are laminated (FIG. 5, oxide semiconductor layers 131 and 132 are laminated),
wherein the first transistor further comprises a first gate (FIG. 5, gate electrode 150 ¶ [0140]); and the first gate is located on a side of the first active layer facing away from the second active layer (FIG. 5, gate electrode 150 is on the upper side of oxide layer 132, which is away from oxide layer 131), wherein the first transistor further comprises a second gate (FIG. 5, auxiliary electrode 140 ¶ [0141], which may function as a second gate ¶ [0107]); and the second gate is located on a side of the second active layer facing away from the first active layer (FIG. 5, auxiliary electrode 140 is on a lower side of oxide layer 131 away from oxide layer 132),
wherein the display panel further comprises: a first gate insulating layer (FIG. 5, gate insulating film 155 between oxide layer 132 and gate electrode 150 ¶ [0084]) located between the first gate and the first active layer; and a second gate insulating layer (FIG. 5, second buffer layer 122 between oxide layer 131 and auxiliary electrode 140 ¶ [0137]) located between the second gate and the second active layer;
wherein the each of at least part of the plurality of pixel circuits (in this case, the pixel circuit of FIG. 17 is used) comprising the first transistor is a first pixel circuit (FIG. 17’s pixel circuit may comprise the transistor 200 of FIG. 5 ¶ [0241], e.g. at transistor TR1 of the circuit to function as the first transistor), the first pixel circuit further comprises a second transistor (transistor 200 of FIG. 5 applied as TR3 of FIG. 17), the second transistor comprises a single active layer, which is a fourth active layer (FIG. 5, oxide semiconductor layer 131 ¶ [0136]), and the fourth active layer is disposed in a same layer as the second active layer or the fourth active layer is disposed in a same layer as the first active layer (FIG. 5, oxide semiconductor layer 131 of TR3 is disposed in the same layer as oxide semiconductor layer 131 of TR1, applied as the first transistor in the context of the pixel circuit of FIG. 17, since they both use the structure of transistor 200 of FIG. 5 ¶ [0241])
wherein the first pixel circuit further comprises a driving transistor (FIG. 17, TR2 is a driving transistor ¶ [0239]); and in a same first pixel circuit, the second transistor is configured to transmit a reset signal to the driving transistor to reset the driving transistor (FIG. 17, TR3 resets the driving transistor TR2 by connecting to the reference voltage Vref ¶ [0220]), and the first transistor is configured to transmit a compensation signal to the driving transistor to perform a threshold compensation on the driving transistor (FIG. 17, TR1 is connected to the Vdata voltage source ¶ [0184], and a person of ordinary skill in the art could send any signal, such as a compensation signal, through that voltage source).
Lee does not explicitly state that the two active layers have different mobilities, or that a mobility of the first active layer is larger than a mobility of the second active layer, comparing mobility of the two oxide semiconductor layers not being a parameter of particular importance to the disclosure of their invention; Lee also did not explicitly state that the second transistor consists of a single active layer, or that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer.
Regarding the limitations requiring that the two active layers have different mobilities, or that a mobility of the first active layer is larger than a mobility of the second active layer, Lee does suggest a number of different materials being suitable for each of the oxide semiconductor layers (layer 131 may be IGZO, for example ¶ [0138], and layer 132 may be IGZTO, for example ¶ [0139]). Those materials have different mobilities when compared to each other, and a person of ordinary skill in the art would recognize that the mobility of the active layers affects the current that passes through the transistor, the mobilities therefore being result-effective variables. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the materials selected for use in the two oxide semiconductor layers of Lee by routine experimentation when selecting the materials, and in so doing would have found it obvious to arrive at a configuration wherein, for example, the first active layer 132 is IGZTO and the second active layer 131 is IGZO; doing so could achieve desirable current properties in the transistor while using the materials explicitly suggested by Lee. That being the case, the two active layers have different mobilities, and a mobility of the first active layer is larger than a mobility of the second active layer.
Lee does not explicitly teach that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer, or that the second transistor consists of a single active layer.
However, Koezuka discloses a display device (a display device including transistor 100A of FIGS. 3A-3C ¶ [0121-0123]) comprising a first gate insulating layer (FIG. 3B, gate insulating layer 110 ¶ [0123]) and a second gate insulating layer (FIG. 3B, insulating layer 103 functions as a gate insulating layer ¶ [0123]). Koezuka also suggests that a dielectric constant of a first gate insulating layer (first gate insulating layer 110 can be hafnium oxide, having a higher dielectric constant than silicon oxide or silicon oxynitride ¶ [0153]) is larger than a dielectric constant of a second gate insulating layer (second gate dielectric layer 103 can be silicon oxide or silicon oxynitride ¶ [0144]). Koezuka further teaches that leakage current due to tunnel current can be inhibited with a hafnium oxide gate insulating layer for the first gate insulating layer (¶ [0153]) and when selecting a material for the second gate insulating layer, a person of ordinary skill in the art would have found it obvious to vary the material used via routine experimentation based on the suggested materials for layer 103 (¶ [0144]), due to considerations of materials cost from changing market conditions. For example, the second gate insulating layer 103 may be formed of silicon oxide or silicon oxynitride, which has a lower dielectric constant than the hafnium oxide of the first gate insulating layer 110.
Lee and Koezuka both pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka such that a dielectric constant of the first gate insulating layer is larger than a dielectric constant of the second gate insulating layer, in order to inhibit the leakage current due to tunnel current in the first gate insulating layer, and in consideration of materials cost from changing market conditions for the second gate insulating layer.
Lee in view of Koezuka does not disclose that the second transistor consists of a single active layer.
However, Yamazaki discloses a display device (the device of FIG. 35) comprising a first transistor (FIG. 34, transistor 10kb, which may be used in place of transistor 10nb pictured in FIG. 35 ¶ [0378]) and a second transistor (FIG. 35, transistor 10m ¶ [0117]), wherein the first transistor includes a first active layer (FIG. 34, oxide semiconductor film 82 ¶ [0113-0114]) and a second active layer (FIG. 34, oxide semiconductor film 81 ¶ [0176]), and wherein an active region of the second transistor consists a single active layer (FIG. 35, oxide layer 84 ¶ [0113-0114]). Yamazaki also teaches that second transistor 10m has low off-state current (¶ [0117]) and that a multilayer active region such as that in first transistor 10kb has a channel which can enable high speed operation (¶ [0351, 0361-0363]). As Yamazaki indicates, different transistors of a same pixel circuit can be optimized for different functions based on having differing active layer configurations.
Lee, Koezuka, and Yamazaki all pertain to the field of display devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka further in view of Yamazaki such that the second transistor consists of a single active layer, in order to optimize the active layers of the different transistors in the pixel circuit for different functions.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Koezuka and Yamazaki as applied to claim 1 above, and further in view of US patent publication US 20210090991 A1 (Sharma et al hereinafter Sharma).
Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 above and further discloses that each of the at least two active layers of the first transistor comprises an oxide semiconductor, and the oxide semiconductor comprises indium (as detailed regarding claim 1, first active layer 132 may be IGZTO and second active layer 131 may be IGZO). Lee does not explicitly disclose that an indium content of the first active layer is larger than an indium content of the second active layer, an exact stoichiometric breakdown of the oxide semiconductor materials not considered necessary to the disclosure of their invention.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary, through routine optimization, the indium contents of the first and second active layers in view of the disclosure of Sharma, which discloses a display device including an active region comprising IGZO (FIG. 3A, semiconducting oxide material 302 ¶ [0099]), and identifies the indium content of IGZO as a result-effective variable: “High indium content IGZO may provide higher mobility and poorer interface properties relative to low indium content IGZO, while low indium content IGZO may provide a wider band gap, lower gate leakage, and better interface properties, although a lower mobility, relative to high indium content IGZO” (¶ [0099]). In order to balance the mobility with the interface properties, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a stoichiometric configuration wherein an indium content of the first active layer is larger than an indium content of the second active layer. See also MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed indium content is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed indium content disparity).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Koezuka and Yamazaki as applied to claim 1 above, and further in view of US patent publication US 20190148558 A1 (Suzuki et al hereinafter Suzuki).
Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 as detailed above, but does not further disclose that a thickness of the second active layer is larger than a thickness of the first active layer; relative thicknesses of the two active layers not being a parameter of particular importance to the disclosure of their invention.
However, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary, through routine optimization, the relative thicknesses of the first and second active layers in view of Suzuki, which discloses a display device (the device of FIG. 1A ¶ [0009, 0018]) comprising an active layer (FIG. 1A, oxide semiconductor layer 107 ¶ [0025]) including a first active layer (FIG. 1A, protective oxide semiconductor layer 107B ¶ [0025]) and a second active layer (FIG. 1A, channel oxide semiconductor layer 107A ¶ [0025]). Suzuki also teaches that the thicknesses of the first and second active layers affect the mobility of the TFT, the switching speed, protection against processing damage, and the resistance (¶ [0051]), making them both result-effective variables.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary, through routine optimization, the relative thicknesses of the first and second active layers, and would have a reasonable expectation of success to arrive at a configuration wherein a thickness of the second active layer is larger than a thickness of the first active layer, in order to balance the various parameters affected by the thicknesses of the active layers, as taught by Suzuki.
Furthermore, the applicant has not presented persuasive evidence that the claimed indium content is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed indium content disparity).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Koezuka and Yamazaki as applied to claim 1 above, and further in view of US patent publication US 20220122535 A1 (Jung et al hereinafter Jung).
Lee in view of Koezuka and Yamazaki discloses the limitations of claim 1 as detailed above and Lee further discloses that the display panel further comprises a display region (Lee FIG. 12, the region of display panel 310 comprising pixels P is a display region ¶ [0166-0168]); wherein the display panel further comprises: a second pixel circuit (the pixel circuit of FIG. 17 may be applied to a second pixel, Lee ¶ [0230-0235]), wherein the second pixel circuit comprises a third transistor (Lee FIG. 17, transistor TR3 of the second pixel may be a third transistor, having the structure of transistor 200 of FIG. 5 ¶ [0241]), the third transistor comprises a fifth active layer (Lee FIG. 5, oxide semiconductor layer 131 of FIG. 17’s transistor TR3 in the second pixel ¶ [0136]), and the fifth active layer is disposed in a same layer as the second active layer or the fifth active layer is disposed in a same layer as the first active layer (Lee FIG. 5, oxide semiconductor layer 131 of TR3 of the second pixel is disposed in the same layer as oxide semiconductor layer 131 of TR1 of the first pixel, applied as the first transistor in the context of the pixel circuit of FIG. 17, since they both use the structure of transistor 200 of FIG. 5 ¶ [0241]), wherein the fifth active layer and the fourth active layer are disposed in a same layer and are made of a same material (Lee FIG. 5, oxide semiconductor layer 131 of TR3 of the second pixel is disposed in the same layer and made of a same material as oxide semiconductor layer 131 of TR3 of the first pixel ¶ [0241]), but does not further disclose that the display region comprises a first display region and a second display region, wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region, and the second display region at least partially surrounds the first display region; and the second display region comprises the second pixel circuit, and the first display region comprises the first pixel circuit.
However, Jung discloses a display panel (FIGS. 1-2, display panel 100 ¶ [0047-0049]) which comprises a first display region (FIGS. 1-2, second region CA ¶ [0047-0049]) and a second display region (FIGS. 1-2, first region DA ¶ [0047-0049]), wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region (FIG. 1, region DA has lower light transmittance compared to region CA ¶ [0005, 0007-0008, 0049]), and the second display region at least partially surrounds the first display region (FIGS. 1-2, DA surrounds CA). Jung also discloses that the first display region (FIGS. 1-2 region CA) comprises one or more sensor modules (FIGS. 1-2 sensors SS1 and SS2 ¶ [0049]), the inclusion of which may add image sensing, infrared sensing, and/or illuminance sensing functionality to the device.
Lee, Koezuka, Yamazaki, and Jung all pertain to the field of display panels, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill of the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka and Yamazaki further in view of Jung such that the display region comprises a first display region and a second display region, wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region, and the second display region at least partially surrounds the first display region, in order to provide one or more sensor modules to add image sensing, infrared sensing, and/or illuminance sensing functionality to the device.
Regarding the limitation that the second display region comprises the second pixel circuit, and the first display region comprises the first pixel circuit: since the pixel circuits of Lee may comprise the same configuration throughout the device (Lee ¶ [0230-0235]), after applying the foregoing modification in view of Jung it naturally follows that one pixel circuit in the second display region is the second pixel circuit, and one pixel circuit in the first display region is the first pixel circuit.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Koezuka and Yamazaki as applied to claim 18 above, and further in view of Jung and US patent publication US 20210175303 A1 (Bang et al hereinafter Bang).
Lee in view of Koezuka and Yamazaki discloses the limitations of claim 18 as detailed above and Lee further discloses that the display panel further comprises a display region (Lee FIG. 12, the region of display panel 310 comprising pixels P is a display region ¶ [0166-0168]). Lee in view of Koezuka and Yamazaki does not further disclose that the display region comprises a first display region and a second display region, wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region, and the second display region at least partially surrounds the first display region; and a light shielding structure located in the first display region is connected to a first potential, and a light shielding structure located in the second display region is connected to a second potential, and the second potential is larger than the first potential.
Regarding the limitations “wherein the display region comprises a first display region and a second display region, wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region, and the second display region at least partially surrounds the first display region”, Jung discloses a display panel (FIGS. 1-2, display panel 100 ¶ [0047-0049]) which comprises a first display region (FIGS. 1-2, second region CA ¶ [0047-0049]) and a second display region (FIGS. 1-2, first region DA ¶ [0047-0049]), wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region (FIG. 1, region DA has lower light transmittance compared to region CA ¶ [0005, 0007-0008, 0049]), and the second display region at least partially surrounds the first display region (FIGS. 1-2, DA surrounds CA). Jung also discloses that the first display region (FIGS. 1-2 region CA) comprises one or more sensor modules (FIGS. 1-2 sensors SS1 and SS2 ¶ [0049]), the inclusion of which may add image sensing, infrared sensing, and/or illuminance sensing functionality to the device.
Lee, Koezuka, Yamazaki, and Jung all pertain to the field of display panels, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill of the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka and Yamazaki further in view of Jung such that the display region comprises a first display region and a second display region, wherein a light transmittance of the second display region is smaller than a light transmittance of the first display region, and the second display region at least partially surrounds the first display region, in order to provide one or more sensor modules to add image sensing, infrared sensing, and/or illuminance sensing functionality to the device.
Regarding the limitations “a light shielding structure located in the first display region is connected to a first potential, and a light shielding structure located in the second display region is connected to a second potential”, Lee discloses another embodiment of their transistor structure (Lee FIG. 9, transistor 600 ¶ [0153-0159]) wherein a light shielding structure is connected to a potential (Lee FIG. 9, light shielding layer 120 connects to source electrode 161 ¶ [0154]), and Lee further teaches that the connection improves the electric stability of the transistor (Lee ¶ [0154]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to modify the device of Lee in view of Koezuka, Yamazaki, and Jung further in view of Lee’s embodiment of FIG. 9 such that each transistor in each pixel’s circuit includes a light shielding structure connected to a potential, and correspondingly, a light shielding structure located in the first display region is connected to a first potential, and a light shielding structure located in the second display region is connected to a second potential, in order to improve the electric stability of the transistor.
Lee in view of Koezuka, Yamazaki, and Jung does not disclose that the second potential is larger than the first potential. However, Bang discloses a display panel comprising a first display region (FIG. 1, display area DA2 ¶ [0050]) and a second display region surrounding the first display region (FIG. 1, display area DA1 ¶ [0050]), further comprising light shielding structures in both the first display region and second display region (FIGS. 2, 5A, light blocking layer 400; a plurality of light blocking layers may be present in display area DA2 ¶ [0077]), that a constant voltage/signal is applied to the light shielding structures to protect against damage from electrostatic discharge, and that different voltages may be applied to the different light shielding structures of the plurality (¶ [0077]). While Bang does not explicitly state that the second potential is larger than the first potential, the potential has been identified as a result-effective variable for protecting against damage from electrostatic discharge, which may vary as necessary (¶ [0077]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the values of the first potential and second potential since they were identified as result-effective variables by Bang. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a configuration wherein the second potential is larger than the first potential, in order to balance the potential applied to the various light shielding structures as needed, according to the teaching of Bang.
Furthermore, the applicant has not presented persuasive evidence that the claimed difference in potentials is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed potential difference).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20210280719 A1 (notably FIG. 3A, 301A first transistor with two active layers, 301B second transistor with one active layer ¶ [0054, 0062-0063]), US 20180190824 A1 (notably FIG. 6 DT 130/140, ST1 230 ¶ [0064, 0075, 0103] discusses using single channel and single gate electrode for switching transistors), and US 20160254291 A1 (notably FIG. 2A OS1/2/3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights