Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments / Arguments
Regarding the rejection(s) of claims under 35 USC 103:
Applicant’s arguments filed on 03/03/2026, in view of the amended claims have been fully considered and they are not persuasive.
Applicant first argues that "Liu discloses a bus monitor system designed for real-time intrusion detection or performance analysis… Liu teaches configuring a range by writing to a 'monitoring initial address register' ([0047]), but Liu does not teach a mechanism where the specific bits corresponding to that range are explicitly set to zero (or a first value) upon receipt of the configuration to establish a fresh monitoring interval." In response, it is noted that Liu was relied upon only for the transmission of one or more address ranges of interest to monitoring hardware over a bus ([0045], [0047], and [0048]). The clearing of the corresponding bits is taught by Doshi, as discussed below.
Secondly, Applicant argues that "Doshi is directed toward memory management (e.g., identifying dirty pages for flushing)" and "does not teach a security subsystem that sends an address range to a bitmap unit which then sets those specific bits to zero (or a first value) as a precursor to a security monitoring interval." In response, Doshi is not relied upon for the security subsystem or the attestation context, which are taught by Nunes; Doshi is relied upon for the per-address bitmap and the range-scoped clearing of bits therein. As to the clearing operation itself, para. [0036] discloses that "a software library may perform a gather operation over any range in the range map and zero out corresponding bits in the stencil," which is an external agent specifying an arbitrary address range and causing the bits of the bitmap corresponding to that range to be set to zero. Para. [0032] further discloses that the eviction logic "may also be configured to clear the corresponding flags/bits in the modification tracking structure 54," and para. [0034] discloses that "each time that a given MSR is updated, the corresponding entry in the tracking table may be configured along with the modification tracking structure (e.g., radix-tree, stencil, or other tracking structure)."
Applicant's remaining distinction reduces to when the clearing occurs, namely upon receipt of the address ranges rather than following data movement. Doshi discloses a repeating cycle in which the stencil is cleared ([0032], [0036]), writes are accumulated by performing "a logical OR operation of a logical one (1) with the appropriate bit in the stencil 44" ([0029]), and the accumulated state is read out to indicate "which chunks of data are to be processed" ([0032]). Ultimately, applicant’s arguments are against the references individually, rather than the proposed modification set forth by the examiner.
Finally, Applicant argues that "[t]he claimed invention provides a specific technical solution for TOCTOU (Time-Of-Check Time-Of-Use) attacks by establishing a clear 'start time' for monitoring" and that "[t]he combination of Nunes, Doshi, and Liu does not reconstruct this specific logic of initializing the bitmap values to define a security window." In response, Nunes supplies both the problem and the motivation to bound the monitoring interval, and Doshi supplies a known hardware mechanism for recording, at per-address granularity, where within a specified range modifications occurred. The application of a known technique to a known device ready for improvement to yield predictable results constitutes a proper rationale for combination.
Therefore, the identified claim language is considered to be taught by the combination, and the rejection is maintained. Further, since Applicant has not separately argued the dependent claims, their rejections are likewise maintained.
It is further noted that the amendments raise a 112a issue that is addressed below.
DETAILED ACTION
This is a reply to the arguments filed on 03/03/2026, in which, claims 1-2 and 4-20 are pending. Claims 1, 5, and 13 are independent. Claim 3 is canceled.
When making claim amendments, the applicant is encouraged to consider the references in their entireties, including those portions that have not been cited by the examiner and their equivalents as they may most broadly and appropriately apply to any particular anticipated claim amendments.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2 and 4-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, as amended, recites "by setting a bit in the bitmap corresponding to each write address to non-zero" (claims 5 and 13 reciting equivalent subject matter in first value/second value terminology, and claims 8 and 16 specifying that the second value is non-zero). This amendment broadens the scope of the claimed invention beyond what is recited in now canceled dependent claim 3, which conditioned the set-to-non-zero behavior on a write address falling within the one or more address ranges of interest, whereas the amendment applies this mechanism universally to each write address regardless of any configured address range. Applicant's cited support at paragraphs [0060]-[0062] does not cure this gap, as those passages describe administrative operations performed by the remote attestation module's bitmap FSM (an external actor writing zeros to clear the bitmap based on a configured address range) rather than the internal sniff logic's write-tracking behavior, and paragraph [0062] explicitly conditions the bitmap FSM's operations on address range 678, directly contradicting the universal scope of the amendment. The closest explicit support for the set-to-non-zero mechanism, at paragraphs [0087]-[0088], appears in the context of method step 1007, which follows step 1005 requiring extraction of a write address within the one or more address ranges of interest.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nunes et al. (“On the TOCTOU Problem in Remote Attestation”, referred to as Nunes), in view of Doshi et al. (US 20190034340 A1, referred to as Doshi) in further view of Liu et al. (US 20130219452 A1, referred to as Liu)
In reference to claim 1, An integrated circuit device, comprising: a system interconnect (Nunes: Section 5.2 Figure 4 Provides for a hardware module (RATA) integrated into a larger system (VRASED remote attestation architecture). It is further provided that there is various components like the MCU core, memories, and RATA module are shown to be part of the same system.)
A set of memories coupled to the system interconnect, each of the set of memories having an address write channel at which write addresses associated with memory write operations can be extracted (Nunes: Section 3.1 Provides for signals that indicate memory read/write operations and the corresponding addresses. Nunes Section 5.2 Section 5.1 and Figure further provides for the same memory presence attached on the system interconnect.)
A security subsystem coupled to the system interconnect, wherein the security subsystem is configured to: receive an attestation request from a requester (Nunes: Section 5.2, Figure 4 Provides for the RATA which is a security module that is part of the overall system. Nunes Section 3.2 further provides for the verifier (requester) sends an attestation request to the prover device.)
Obtain a bitmap status from one of the set of write bitmaps indicating that a write address within the one or more address ranges of interest was detected (Nunes: Section 5.1 Provides for the attestation result including the value of LMT which indicates when the attested memory region AR was last modified. Nunes Figure 4 Provides for system interconnections between MCU Core, Program Memory and RATA module through which LMT status is obtained. Nunes Section 3.2 Further provides for communication of attestation results via system interconnect between Prover and Verifier.)
Compute a signature based at least in part on the bitmap status (Nunes: Section 5.1 Provides for the attestation result H is a HMAC signature computed over the attested memory AR, which includes the LMT value indicating the latest modification time.)
Return the signature to a requester (Nunes: 5.2 Figure 5 (13) Provides for the Vrf (requester) receiving the attestation information and verifying the information. Nunes Section 3.2 further provides for the prover returns the attestation result, which is a signature, to the verifier (requester)).
Nunes does not explicitly disclose a set of write bitmaps that are respectively associated with the set of memories, wherein each of the set of write bitmaps comprises: a bitmap that tracks the write addresses of detected memory write operations to a corresponding memory of the set of memories; and logic for extracting the write addresses associated with the memory write operations from the address write channel for the corresponding memory and modifying the bitmap based on the write addresses, however, Doshi discloses:
A set of write bitmaps that are respectively associated with the set of memories, wherein each of the set of write bitmaps comprises: a bitmap that tracks the write addresses of detected memory write operations to a corresponding memory of the set of memories (Doshi: [0012], [0024]-[0025] and [0027] Provides for using bitmaps associated with memories to track write addresses within specified memory ranges. Doshi paragraph [0031] Fig. 5 further provides for a bitmap vector in FIG. 4 directly tracks write addresses. Doshi paragraph [0031] Fig. 5 further provides a tracking table with tracker identification and memory ranges.)
Wherein different bits in the bitmap correspond to different addresses in the corresponding memory (Doshi: [0028]-[0032] Provides for how different bits in the bitmap correspond to different addresses in memory.)
Logic for extracting the write addresses associated with the memory write operations from the address write channel for the corresponding memory and modifying the bitmap based on the write addresses (Doshi: [0024]-[0025], [0027], [0029] and [0031] Provides for tracking logic that detects write addresses and modifies a bitmap structure accordingly.)
By setting a bit in the bitmap corresponding to each write address to non-zero (Doshi: [0029]-[0030] Provides for setting the corresponding bit to a logical one (non-zero) via an OR on each detected write.)
bits in the bitmap corresponding to the one or more address ranges of interest are set to zero (Doshi: [0028] and [0032]-[0043] Provides for range scoped zeroing of exactly the bits covering the addresses of interest, establishing a clean baseline before the next monitoring window.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes, which provides for a hardware module integrated into a larger VRASED remote attestation architecture, including various components like the MCU core, memories, and RATA module on a system interconnect, and includes security features for attestation processes, with the teachings of Doshi, which provides for using bitmaps associated with memories to track write addresses within specified memory ranges and includes logic for updating these bitmaps based on detected write addresses. One of ordinary skill in the art would recognize the ability to combine Nunes' system with Doshi's specific memory tracking features to enhance the security and efficiency of memory operations within the system. One of ordinary skill in the art would be motivated to make this modification in order to create a more robust and secure integrated circuit device capable of dynamically managing and verifying memory accesses and modifications, particularly in environments requiring secure data handling and attestation.
Nunes in view of Doshi do not explicitly disclose sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmap. However, Liu discloses:
sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmaps (Liu: [0015] and [0047] Provides for sending address information (monitoring initial address) to the monitoring system via the bus. The processor uses the bus to dispose configured information including address ranges to the configuration unit. Liu [0056] Provides that the configuration unit (part of the security subsystem) is a slave device that receives configuration information over the SOC system bus. The processor utilizes the bus to send configured information to the configuration unit. Liu [0047]-[0048] Provides for that address ranges of interest (monitoring initial address and monitoring length defining an address range) are configured and stored in the monitoring system. These address ranges correspond to specific monitoring functions and states in the bus monitor.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes in view of Doshi, which together provide an integrated circuit with security subsystem attestation capabilities and bitmap-based memory write tracking, with the teachings of Liu, which introduces sending specific address ranges of interest from a processor to monitoring systems via a system bus, where these ranges are configured to correspond to specific monitoring functions. One of ordinary skill in the art would recognize the ability to incorporate Liu's address range communication and configuration approach into the combined system to enable dynamic specification of memory regions to be monitored. One of ordinary skill in the art would be motivated to make this modification in order to provide flexible and configurable memory monitoring by allowing the security subsystem to specify which address ranges require attestation.
In reference to claim 2, The integrated circuit device of claim 1, further comprising:
a central processing unit (CPU) subsystem coupled to the system interconnect, the CPU subsystem including static random-access memory (SRAM), wherein the set of memories includes the SRAM (Nunes: Section 3.1 Provides for that the MCU (which includes the CPU) has SRAM used as data memory.) Nunes does not explicitly disclose, a memory subsystem coupled to the system interconnect, the memory subsystem including dynamic random-access memory (DRAM), wherein the set of memories includes the DRAM (Doshi: Fig.1 [0011] Provides for volatile memory, including DRAM, which supports the concept of a memory subsystem with DRAM.)
In reference to claim 3, The integrated circuit device of claim 1, wherein, after receiving the one or more address ranges of interest, the one of the set of write bitmaps is configured to:
set bits in the bitmap corresponding to the one or more address ranges of interest to zero; and
upon extracting the write address within the one or more address ranges of interest, set a bit in the bitmap corresponding to the write address to non-zero (Doshi: Fig. 4 [0030]-[0032] Provides for clearing flags/bits in the modification tracking structure after data movement. Doshi Fig.4 and paragraphs [0027] - [0029] further provides for setting and updating bits in a bitmap based on received write addresses.)
In reference to claim 4, The integrated circuit device of claim 1, wherein, in response to receiving the one or more address ranges of interest, the one of the set of write bitmaps is configured to: provide the bitmap status to the security subsystem indicating whether the write address within the one or more address ranges of interest was detected (Doshi: Fig. 5 [0032] Provides for the logic for checking and reporting the status of modified data ranges.)
In reference to claim 5, An integrated circuit device, comprising: a system interconnect: a memory coupled to the system interconnect; (Nunes: Section 5.2 Figure 4 Provides for a hardware module (RATA) integrated into a larger system (VRASED remote attestation architecture). It is further provided that there is various components like the MCU core, memories, and RATA module are shown to be part of the same system. Nunes Section 3.1 further provides for signals that indicate memory read/write operations and the corresponding addresses. Nunes Section 5.2 Section 5.1 and Figure 4 further provides for the same memory presence attached on the system interconnect.) A security subsystem coupled to the system interconnect, the security subsystem (Nunes: Section 5.2, Figure 4 Provides for the RATA which is a security module that is part of the overall system. Nunes Section 3.2 further provides for the verifier (requester) sends an attestation request to the prover device. Nunes Section 3.2 further provides for the request including a memory range AR (attested range). Nunes Section 5.1 and 5.2 further provides for detecting modification of the requested attested range (AR). Nunes Section 5.2, Figure 4 Provides for the RATA security module coupled to system interconnect allowing communication with other system components including MCU core and Program Memory.) Obtain, via the system interconnect, a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected (Nunes: Section 5.1 Provides for the attestation result including the value of LMT which indicates when the attested memory region AR was last modified. Nunes Section 5.1 Provides for obtaining LMT value through system interconnections shown in Figure 4. Nunes Section 3.2 Further provides for communication of attestation results containing LMT via system interconnect between system components.)
Nunes does not explicitly disclose a write bitmap for tracking write addresses, however, Doshi discloses:
A write bitmap comprising a bitmap that tracks write addresses of detected memory write operations to the memory (Doshi: [0012], [0024]-[0025] and [0027] Provides for using bitmaps associated with memories to track write addresses within specified memory ranges. Doshi Fig. 4 paragraph [0029] further provides for a bitmap vector in FIG. 4 directly tracks write addresses. Doshi Fig. 5 paragraph [0031] further provides for a tracking table with tracker identification and memory ranges.)
Wherein different bits in the bitmap correspond to different addresses in the corresponding memory (Doshi: [0028]-[0032] Provides for how different bits in the bitmap correspond to different addresses in memory.)
By setting a bit in the bitmap corresponding to each write address to a second value (Doshi: [0029]-[0030] Provides for setting the corresponding bit to a logical one (non-zero) via an OR on each detected write.)
bits in the bitmap corresponding to the one or more address ranges of interest are set to a first value different from the second value (Doshi: [0028] and [0032]-[0043] Provides for range scoped zeroing of exactly the bits covering the addresses of interest, establishing a clean baseline before the next monitoring window.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes, which provides a hardware module integrated into a larger VRASED remote attestation architecture including various components like the MCU core, memories, and a RATA security module, with the teachings of Doshi, which details the use of write bitmaps to track write addresses within specified memory ranges. One of ordinary skill in the art would recognize the ability to integrate Doshi’s memory tracking features into Nunes' security subsystem to enhance the accuracy and security of memory operation monitoring within the integrated circuit device. One of ordinary skill in the art would be motivated to make this modification in order to provide a more comprehensive security system capable of dynamically managing and verifying memory accesses and modifications, particularly suitable for environments requiring stringent security measures.
Nunes in view of Doshi do not explicitly disclose sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmap. However, Liu discloses:
sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmaps (Liu: [0015] and [0047] Provides for sending address information (monitoring initial address) to the monitoring system via the bus. The processor uses the bus to dispose configured information including address ranges to the configuration unit. Liu [0056] Provides that the configuration unit (part of the security subsystem) is a slave device that receives configuration information over the SOC system bus. The processor utilizes the bus to send configured information to the configuration unit. Liu [0047]-[0048] Provides for that address ranges of interest (monitoring initial address and monitoring length defining an address range) are configured and stored in the monitoring system. These address ranges correspond to specific monitoring functions and states in the bus monitor.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes in view of Doshi, which together provide an integrated circuit with security subsystem attestation capabilities and bitmap-based memory write tracking, with the teachings of Liu, which introduces sending specific address ranges of interest from a processor to monitoring systems via a system bus, where these ranges are configured to correspond to specific monitoring functions. One of ordinary skill in the art would recognize the ability to incorporate Liu's address range communication and configuration approach into the combined system to enable dynamic specification of memory regions to be monitored. One of ordinary skill in the art would be motivated to make this modification in order to provide flexible and configurable memory monitoring by allowing the security subsystem to specify which address ranges require attestation.
In reference to claim 6, The integrated circuit device of claim 5, wherein the write bitmap further comprises logic for extracting the write address from an address write channel associated with the memory (Nunes: Section 5.1 and 3.1 Provides for a logic to monitor CPU signals (Daddr, Wen, DMAaddr, DMAen) to detect writes to the attested memory region AR. Nunes Figure 4 and paragraph [0029] further provides for the function of extracting and updating based on write addresses.
In reference to claim 7, The integrated circuit device of claim 6, wherein the logic is further configured to modify the bitmap based on the write address by setting a bit in the bitmap corresponding to the write address to non-zero (Doshi: [0029] Fig. 4 Provides for modifying the bitmap based on the write address by setting a bit to indicate a write.)
In reference to claim 8, the integrated circuit deice of claim 5, wherein the first value is zero and the second value is non-zero (Doshi: [0029]-[0030] Provides for setting the corresponding bit to a logical one (non-zero) via an OR on each detected write. (Doshi: [0028] and [0032]-[0043] Provides for range scoped zeroing of exactly the bits covering the addresses of interest, establishing a clean baseline before the next monitoring window.)
In reference to claim 10, The integrated circuit device of claim 5, further comprising: a central processing unit (CPU) subsystem comprising the memory, wherein the memory is static random-access memory (SRAM) (Nunes: Section 2 Provides for that the targeted MCU devices, which include a CPU subsystem, use SRAM for data memory.)
In reference to claim 11, The integrated circuit device of claim 5, further comprising:
a memory subsystem comprising the memory, wherein the memory is dynamic random-access memory (DRAM) (Doshi: Fig. 1 [0011] Provides for volatile memory, including DRAM, which supports the concept of a memory subsystem with DRAM.)
In reference to claim 12, The integrated circuit device of claim 5, wherein the security subsystem is configured to compute a signature using the bitmap status (Nunes: Section 5.1 Provides for the attestation result H is a HMAC signature computed over the attested memory AR, which includes the LMT value indicating the latest modification time. Nunes Section 5.2 Figure 5 (13) further provides for the Vrf (requester) receiving the attestation information and verifying the information. Nunes Section 3.2 further provides that the prover returns the attestation result, which is a signature, to the verifier (requester)).
In reference to claim 13, A computer-implement method: (Nunes: Section 5.2 Figure 4 Provides for a hardware module (RATA) integrated into a larger system (VRASED remote attestation architecture). It is further provided that there is various components like the MCU core, memories, and RATA module are shown to be part of the same system. Nunes Section 3.1 further provides for signals that indicate memory read/write operations and the corresponding addresses. Nunes Section 5.2 Section 5.1 and Figure 4 further provides for the same memory presence attached on the system interconnect.)
Memory coupled to a system interconnect (Nunes Section 5.2, Figure 4 Provides for the RATA security module coupled to system interconnect allowing communication with other system components including MCU core and Program Memory.)
a security subsystem coupled to the system interconnect (Nunes: Section 5.2, Figure 4 Provides for the RATA which is a security module that is part of the overall system. Nunes Section 3.2 further provides for the verifier (requester) sends an attestation request to the prover device. Nunes Section 3.2 further provides for the request including a memory range AR (attested range). Nunes Section 5.1 and 5.2 further provides for detecting modification of the requested attested range (AR).)
Obtaining, at the security subsystem and via the system interconnect, a bitmap status from the write bitmap indicating that a write address within the one or more address ranges of interest was detected (Nunes: Section 5.1 Provides for the attestation result including the value of LMT which indicates when the attested memory region AR was last modified. Nunes Section 5.1 Provides for obtaining LMT value through system interconnections shown in Figure 4. Nunes Section 3.2 Further provides for communication of attestation results containing LMT via system interconnect between system components.)
Nunes does not explicitly disclose a write bitmap for tracking write addresses, however, Doshi discloses:
Tracking write addresses in a bitmap of a write bitmap, the write addresses associated with detected memory write operations to a memory (Doshi: [0012], [0024]-[0025] and [0027] Provides for using bitmaps associated with memories to track write addresses within specified memory ranges. Doshi Fig. 4 paragraph [0029] further provides for a bitmap vector in FIG. 4 directly tracks write addresses. Doshi Fig. 5 paragraph [0031] further provides for a tracking table with tracker identification and memory ranges.)
Wherein different bits in the bitmap correspond to different addresses in the corresponding memory (Doshi: [0028]-[0032] Provides for how different bits in the bitmap correspond to different addresses in memory.)
By setting a bit in the bitmap corresponding to each write address to a second value (Doshi: [0029]-[0030] Provides for setting the corresponding bit to a logical one (non-zero) via an OR on each detected write.)
bits in the bitmap corresponding to the one or more address ranges of interest are set to a first value different from the second value (Doshi: [0028] and [0032]-[0043] Provides for range scoped zeroing of exactly the bits covering the addresses of interest, establishing a clean baseline before the next monitoring window.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes, which provides a hardware module integrated into a larger VRASED remote attestation architecture including various components like the MCU core, memories, and a RATA security module, with the teachings of Doshi, which details the use of write bitmaps to track write addresses within specified memory ranges. One of ordinary skill in the art would recognize the ability to integrate Doshi’s memory tracking features into Nunes' security subsystem to enhance the accuracy and security of memory operation monitoring within the integrated circuit device. One of ordinary skill in the art would be motivated to make this modification in order to provide a more comprehensive security system capable of dynamically managing and verifying memory accesses and modifications, particularly suitable for environments requiring stringent security measures.
Nunes in view of Doshi do not explicitly disclose sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmap. However, Liu discloses:
sending one or more address ranges of interest to the set of write bitmaps, such that the one or more address ranges of interest are received by the set of write bitmaps from the security subsystem over the system interconnect the one or more address ranges of interest corresponding to one or more bits in the bitmap of one of the set of write bitmaps (Liu: [0015] and [0047] Provides for sending address information (monitoring initial address) to the monitoring system via the bus. The processor uses the bus to dispose configured information including address ranges to the configuration unit. Liu [0056] Provides that the configuration unit (part of the security subsystem) is a slave device that receives configuration information over the SOC system bus. The processor utilizes the bus to send configured information to the configuration unit. Liu [0043][0047]-[0048] Provides for that address ranges of interest (monitoring initial address and monitoring length defining an address range) are configured and stored in the monitoring system. These address ranges correspond to specific monitoring functions and states in the bus monitor.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Nunes in view of Doshi, which together provide an integrated circuit with security subsystem attestation capabilities and bitmap-based memory write tracking, with the teachings of Liu, which introduces sending specific address ranges of interest from a processor to monitoring systems via a system bus, where these ranges are configured to correspond to specific monitoring functions. One of ordinary skill in the art would recognize the ability to incorporate Liu's address range communication and configuration approach into the combined system to enable dynamic specification of memory regions to be monitored. One of ordinary skill in the art would be motivated to make this modification in order to provide flexible and configurable memory monitoring by allowing the security subsystem to specify which address ranges require attestation.
In reference to claim 14, The computer-implement method of claim 13, further comprising: extracting the write address from an address write channel associated with the memory (Nunes: Section 5.1 and 3.1 Provides for a logic to monitor CPU signals (Daddr, Wen, DMAaddr, DMAen) to detect writes to the attested memory region AR. Nunes Figure 4 and paragraph [0029] further provides for the function of extracting and updating based on write addresses.
In reference to claim 15, The computer-implement method of claim 14, further comprising: modifying the bitmap based on the write address by setting a bit in the bitmap corresponding to the write address to non-zero (Doshi: [0029] Fig. 4 Provides for modifying the bitmap based on the write address by setting a bit to indicate a write.)
In reference to claim 16, The computer-implement method of claim 13, wherein the first value is zero and the second value is non-zero (Doshi: [0029]-[0030] Provides for setting the corresponding bit to a logical one (non-zero) via an OR on each detected write. (Doshi: [0028] and [0032]-[0043] Provides for range scoped zeroing of exactly the bits covering the addresses of interest, establishing a clean baseline before the next monitoring window.)
In reference to claim 17, The computer-implement method of claim 13, wherein the write bitmap is configured to provide the bitmap status upon receiving the one or more address ranges of interest from the security subsystem (Doshi: [0029] - [0032] Provides for a scenario where specific bits set in a bitmap structure indicate areas of interest which can be acted upon, such as writing to storage or communicating with other components.)
In reference to claim 18, The computer-implement method of claim 13, wherein the memory is included in a central processing unit (CPU) subsystem, and wherein the memory is static random-access memory (SRAM) (Nunes: Section 2 Provides for that the targeted MCU devices, which include a CPU subsystem, use SRAM for data memory.)
In reference to claim 19, The computer-implement method of claim 13, wherein the memory is included in a memory subsystem, and wherein the memory is dynamic random-access memory (DRAM) (Doshi: Fig. 1 [0011] Provides for volatile memory, including DRAM, which supports the concept of a memory subsystem with DRAM.)
In reference to claim 20, The computer-implement method of claim 13, further comprising: computing, at the security subsystem, a signature using the bitmap status (Nunes: Section 5.1 Provides for the attestation result H is a HMAC signature computed over the attested memory AR, which includes the LMT value indicating the latest modification time. Nunes Section 5.2 Figure 5 (13) further provides for the Vrf (requester) receiving the attestation information and verifying the information. Nunes Section 3.2 further provides that the prover returns the attestation result, which is a signature, to the verifier (requester)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AIDAN EDWARD SHAUGHNESSY whose telephone number is (703)756-1423. The examiner can normally be reached on Monday-Friday from 7:30am to 5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey Nickerson, can be reached at telephone number (469) 295-9235. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR for authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/usptoautomated-interview-request-air-form.
/A.E.S./Examiner, Art Unit 2432
/Jeffrey Nickerson/Supervisory Patent Examiner, Art Unit 2432
Prosecution Insights