DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4 and 6-10 are presented for examination based on the amended claims in the application filed on November 18, 2025. Claims 5 and 11 have been cancelled by the applicant.
Claims 3 and 9 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. § 112, the applicant), regards as the invention.
Claims 1-4 and 6-10 rejected under 35 U.S.C. § 112(a) or 35 U.S.C. § 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, it has not been integrated into practical application.
Claims 1, 3-4, 6-7, and 9-10 are rejected under 35 U.S.C. § 103 as being unpatentable over Kunal, Kishor, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, and Sachin S. Sapatnekar. “GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.” In DATE, pp. 55-60. 2020 [herein “Kunal”] in view of Yang, Qihang, Guodong Qi, Weizhuo Gan, Zhenhua Wu, Huaxiang Yin, Tao Chen, Guangxi Hu, Jing Wan, Shaofeng Yu, and Ye Lu. “Transistor compact model based on multigradient neural network and its application in SPICE circuit simulations for gate-all-around Si cold source FETs.” IEEE Transactions on Electron Devices 68, no. 9 (2021): 4181-4188 [herein “Yang”], and further in view of US 2015/0143317 A1 Gibson, Patrick et al. [herein “Gibson”].
Claims 2 and 8 are rejected under 35 U.S.C. § 103 as being unpatentable over Kunal, Yang, and Gibson as applied to claim 1 above, and further in view of US 8,578,316 B1 Joshi, Rajiv et al [herein “Joshi”].
This action is made Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed November 18, 2025 has been entered. Claims 1-4 and 6-10 remain pending in the application. Applicant’s amendments to the Specification and Claims have overcome each and every objection and 112(b) rejections previously set forth in the Non-Final Office Action mailed August 28, 2025, with the exception of the 112(b) rejections reproduced in the subsequent sections. No acknowledge from applicant was made with respect to the examiner interpretation of the 112(f) limitation found in claims.
Specification
The amendment filed November 18, 2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: Para. 31, “Referring to FIG. 1, the semiconductor device simulation system 1 according to the present invention may be implemented by hardware such as a computer system with a processor and execution of programs installed therein”. The amendment to Para. 31 includes a system with a processor, but the original disclosure does not support that the computer has a processor in the specification nor in any of the drawings.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Interpretation
The following is a quotation of 35 U.S.C. § 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. § 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Regarding claim 1, such claim limitations are the “a region graph generation module”, “device determination module”, and the “an initial solution generating module”. Claims 2-4 and 6 will also be interpreted based on their claim dependencies. Because the structural modifier, being “a processor”, is not supported by the originally filed specification as noted above, it will not be considered in this interpretation.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. § 112(f) or pre-AIA 35 U.S.C. § 112, sixth paragraph.
The following limitations are interpreted as invoking 34 U.S.C 112(f) of pre-AIA 35 U.S.C 112, sixth
paragraph:
In claim 1, “a region graph generation module executed by the processor and configured to input a device structure file of a semiconductor device to be simulated, generate a region graph corresponding to the device structure file and output the region graph”. The corresponding structure in the discloser for performing the claimed inputting a structure file, generating a region graph, and outputting the region graph is the region graph generating module 20 included in the semiconductor device simulation system, as shown in Para. 34 (“In the region graph generating module 20 according to the present invention, a device structure file is input from the device structure file input module”), in Para. 42 (“The device determination module 30 classifies the types of semiconductor devices constituting the region graph generated by the region graph generation module”), and in Para. 31 (“Referring to FIG. 1, the semiconductor device simulation system 1 according to the present invention may be implemented by hardware such as a computer system with a processor and execution of programs installed therein. The semiconductor device simulation system 1 according to the present invention includes a device structure file input module 10, a region graph generation module 20, a device determination module 30, an initial solution generation module 40, a semiconductor device simulator 50, and a graph artificial neural network training module 60.”). Therefore, the interpretation of the “a region graph generation module executed by the processor and configured to input a device structure file of a semiconductor device to be simulated, generate a region graph corresponding to the device structure file and output the region graph” is the semiconductor device simulation system.
In claim 1, “a device determination module executed by the processor and configured to execute a graph artificial neural network model to determine a type of the semiconductor device corresponding to the region graph”. The corresponding structure in the discloser for performing the claimed executing a graph artificial neural network model is the device determination module 30 included in the semiconductor device simulation system, as shown in Para. 42 (“The device determination module 30 executes graph neutral network (GNN) model to classify the types of semiconductor devices constituting the region graph generated by the region graph generation module and output the classified types”) and in Para. 31 (“Referring to FIG. 1, the semiconductor device simulation system 1 according to the present invention may be implemented by hardware such as a computer system with a processor and execution of programs installed therein. The semiconductor device simulation system 1 according to the present invention includes a device structure file input module 10, a region graph generation module 20, a device determination module 30, an initial solution generation module 40, a semiconductor device simulator 50, and a graph artificial neural network training module 60.”). Therefore, the interpretation of the “a device determination module executed by the processor and configured to execute a graph artificial neural network model to determine a type of the semiconductor device corresponding to the region graph” is the semiconductor device simulation system.
In claim 1, “an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure”. The corresponding structure in the discloser for performing the claimed executing a compact model is the initial solution generating module 40 included in the semiconductor device simulation system, as shown in Para. 44 (“The initial solution generation module 40 executes the compact model to quickly obtains an approximate solution of the current-voltage characteristic for the physical quantity of each region according to the type of semiconductor device.”) and in Para. 31 (“Referring to FIG. 1, the semiconductor device simulation system 1 according to the present invention may be implemented by hardware such as a computer system with a processor and execution of programs installed therein. The semiconductor device simulation system 1 according to the present invention includes a device structure file input module 10, a region graph generation module 20, a device determination module 30, an initial solution generation module 40, a semiconductor device simulator 50, and a graph artificial neural network training module 60.”). Therefore, the interpretation of the “an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure” is the semiconductor device simulation system.
Claim Rejections - 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. § 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 9 are rejected under 35 U.S.C. § 112(b) or 35 U.S.C. § 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. § 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “re-divides” in claim 3 is used by the claim to mean “divide”, while the accepted meaning is “divide again” (see Merriam-Webster definition, “Redivide.” Merriam-Webster.com Dictionary, Merriam-Webster, https://www.merriam-webster.com/dictionary/redivide. Accessed 21 Aug. 2025.). The term is indefinite because the specification does not clearly redefine the term. Claim 9, having similar limitations of claim 3, is also rejected under the similar rationale.
The following is a quotation of the first paragraph of 35 U.S.C. § 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. § 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4 and 6-10 rejected under 35 U.S.C. § 112(a) or 35 U.S.C. § 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the original disclosure filed lacks support for the following limitation “A semiconductor device simulation system implemented by a computer system with a processor”. While the specification discloses semiconductor device simulation system implemented by a computer (see Para. 31), the specification as originally filed lacks support for computer system with a processor as stated above in the objection to the specification. Claim 7, having similar limitations of claim 1, is also rejected under the similar rationale. Claims 2-4 and 6 as well as claims 8-10, which are dependent on claims 1 and 7, respectively, are similarly rejected.
Claim Rejections - 35 U.S.C. § 101
35 U.S.C. § 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4 and 6-10 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1:
Claims 1-4 and 6 are directed to a system and fall within the statutory category of a machine, and claims 7-10 are directed to a method and fall within the statutory category of a process. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claims 1 and 7: The limitations of:
“generate a region graph corresponding to the device structure file and output the region graph, the region graph including nodes representing regions and terminals of the device structure file and edges representing connection relationships between the nodes”,
“determine a type of the semiconductor device corresponding to the region graph”,
“obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure”,
“initialized based on the initial solution and to perform semiconductor device simulation”,
“wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type”, and
“wherein simulation speed of the semiconductor device simulator is accelerated by using the initial solution corresponding to the semiconductor device structure”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, the limitations can be conducted as the following:
a person can mentally create or draw with pen and paper the physical connections between the internal doped material regions of a semiconductor device and its terminals using provided data about the device in a graph of the device regions,
a person can mentally recognize or draw with pen and paper the type of semiconductor device from the generated region graph such as a BJT or MOSFET depending on the number and doping-types,
a person can mentally recognize or draw with pen and paper what set of equations should be used from the type of semiconductor and use that set of the equations as the initial solution for a solution of the device,
a person can mentally determine or draw with pen and paper electrical voltage and current parameters of a MOSFET using the current equations for the saturation region that was selected from the type of semiconductor,
a person can mentally create or draw with pen and paper the physical connections between the internal doped material regions of a semiconductor device and its terminals using provided data about the device in a graph of the device regions and represent the region by nodes which are of the same constituent material and same impurity type, and
a person can mentally determine or draw with pen and paper electrical voltage and current parameters of a MOSFET by using the current equations for the saturation region that was selected from the type of semiconductor which will save time in the simulation, e.g., calculation of parameters.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, claims 1 and 7: The limitations of “initialized based on the initial solution and to perform semiconductor device simulation”, as drafted, is an operation that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating electrical voltage and current parameters of a MOSFET can be conducted using properties of the device and MOSFET current equations for the saturation region that was selected from the type of semiconductor which will save time in the simulation, e.g., calculation of parameters.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic operation but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Therefore, yes, claims 1 and 7 recite judicial exceptions. The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claims 1 and 7: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements: “A semiconductor device simulation system implemented by a computer system with a processor”, “a region graph generation module executed by the processor”, “a device determination module executed by the processor and configured to execute a graph artificial neural network model”, “an initial solution generation module executed by the processor and configured to execute a compact model”, and “a semiconductor device simulator executed by the processor and configured” which is merely a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) with the broadest reasonable interpretation, which does not integrate a judicial exception into elements. Further, the following additional element “configured to input a device structure file of a semiconductor device to be simulated” which is merely a recitation of insignificant extra-solution data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. The insignificant extra-solution activities are further addressed below under step 2B as also being Well-Understood, Routine, and Conventional (WURC).
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application?” No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluated the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1 and 7 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1 and 7: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components which do not amount to significantly more than the abstract idea. Further, the insignificant extra-solution data gathering, record update, and data transmission activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II), “The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, ii. Performing repetitive calculations, iii. Electronic recordkeeping, iv. Storing and retrieving information in memory”).
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception?” No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception. Having concluded the analysis within the provided framework, claims 1 and 7 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 2 and 8, they recite additional limitations of “wherein the device structure file is generated by a structure generator program or a semiconductor process simulation program”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally create or draw with a pencil and paper a device structure file by extracting and complying the properties of a semiconductor device together, such region size and doping type of the regions of the device.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claim 3 and 9, they recite additional limitations of
“wherein the region graph generation module re-divides regions of the device structure file based on constituent material and impurity type”,
“represents the re-divided regions and terminals of the device structure file as nodes of the region graph”,
“and represents connection relationships between the nodes as edges of the region graph”, and
“thereby generating the region graph represented by the nodes and the edges”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, the limitations can be conducted as the following:
a person can mentally separate or draw with pen and paper further the internal material regions of a semiconductor device by dividing the regions based on the material type and doping impurity type,
a person can mentally create or draw with pen and paper the internal doped material regions and its terminals of the semiconductor device as graphical nodes,
a person can mentally create or draw with pen and paper lines between the graphical nodes of both the internal doped material regions of a semiconductor device and its terminals to show the physical connections of the device, and
a person can mentally create or draw with pen and paper a region graph that shows the physical connections between the nodes of the internal doped material regions of a semiconductor device and the nodes of its terminals.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Regarding claims 4 and 10, they recite additional element recitations of “wherein the graph artificial neural network model is trained in a supervised manner of a machine learning method by using training data including a pair of the type of semiconductor device and the region graph corresponding to the type of semiconductor device” and “training the graph artificial neural network model” which is a recitation of generic computing components and functions being used as a tool to implement the judicial exception (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, these claims do not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, these claims also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 4 and 10 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claim 6, it recites additional limitations of “obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device” and “generate the initial solution by summing the approximate solutions for each region”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper. For example, a person can mentally choose or draw with pen and paper a current-voltage characteristic equation from a set of current-voltage characteristic equation that corresponds to each type of semiconductor device for each region of the devices to be used for simulation of the instant type of the semiconductor device, and a person can mentally combine or draw with pen and paper the approximate solutions of each region together to form the initial solution using simple arithmetic.
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind or with pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claim 6, it recites additional limitations of “obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device” and “generate the initial solution by summing the approximate solutions for each region”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation of mathematical evaluations. For example, calculating electrical voltage and current parameters for the saturation region of a MOSFET can be conducted using properties of the device and MOSFET current equations that was selected from the type of semiconductor which will save time in the simulation, e.g., calculation of parameters (Para. 45 has the equation for determining the drain current of a MOSET in the saturation region), and calculating the initial solution can be conducted by mathematically adding the approximate solution for each region together to create a combine solution for all regions of the device (Para. 44).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation of mathematic evaluations but for the recitation of generic computer components, then it falls within the “Mathematical Operation” grouping of abstract ideas. Accordingly, the claim recites an abstract idea under Prong I step 2A.
Furthermore, regarding claim 6, it recites additional element recitations of “wherein the initial solution generation module is configured to input information on the type of semiconductor device determined by the device determination module and physical quantity for each region”, “wherein the compact model is configured to obtain”, and “provide the initial solution to the semiconductor device simulator” which is merely insignificant extra-solution data gathering and data outputting activities (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application. Further, the insignificant extra-solution data gathering, record update, and data transmission activities are also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II), “The courts have recognized the following computer functions as well understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, ii. Performing repetitive calculations, iii. Electronic recordkeeping, iv. Storing and retrieving information in memory”). Further, this claim does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, this claim also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 6 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, having concluded the analysis within the provided framework, claims 1-4 and 6-10 do not recite patent eligible subject matter and are rejected under 35 U.S.C. § 101 because the claimed invention is directed to judicial exception, an abstract idea, that has not been integrated into a practical application. The claims further do not recite significantly more than the judicial exception. Claims 2-4 and 6 and Claims 8-10 are also rejected for incorporating the deficiency of their independent claim 1 and 7, respectively.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claims 1, 3-4, 6-7, and 9-10 are rejected under 35 U.S.C. § 103 as being unpatentable over Kunal, Kishor, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, and Sachin S. Sapatnekar. “GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.” In DATE, pp. 55-60. 2020 [herein “Kunal”] in view of Yang, Qihang, Guodong Qi, Weizhuo Gan, Zhenhua Wu, Huaxiang Yin, Tao Chen, Guangxi Hu, Jing Wan, Shaofeng Yu, and Ye Lu. “Transistor compact model based on multigradient neural network and its application in SPICE circuit simulations for gate-all-around Si cold source FETs.” IEEE Transactions on Electron Devices 68, no. 9 (2021): 4181-4188 [herein “Yang”], and further in view of US 2015/0143317 A1 Gibson, Patrick et al. [herein “Gibson”].
As per claim 1, Kunal teaches “a region graph generation module executed by the processor and configured to input a device structure file of a semiconductor device to be simulated, generate a region graph corresponding to the device structure file and output the region graph, the region graph including nodes representing regions and terminals of the device structure file and edges representing connection relationships between the nodes”. (Pg. 2 Sect. II, “we represent an element-level circuit netlist as an undirected bipartite graph G(V, E)” [a region graph generation module configured to generate a region graph using a device structure file of a device and output the region graph]. Pg. 4 Sect. V, “12 features that annotate the element type, e.g., whether it is an NMOS/PMOS transistor, resistor, inductor, capacitor, voltage reference, current reference, or a hierarchical block” [of a semiconductor device]. Pg. 1 Sect. I, “Our extracted circuit hierarchy can be used in various ways: for automated layout using hierarchical block assembly using the identified hierarchies; for automated constraint annotation (e.g., identifying symmetry, matching, common centroid); or constraint budgeting to each block while meeting system-level constraints” [i.e., to be simulated]. Pg. 2 Sect. II, “Our input is a SPICE circuit netlist, and a netlist for a library of primitive templates” [to input a device structure file of a semiconductor device to be simulated]. Pg. 6 Sect. V, “Our annotation scheme is fast, and is dominated by the runtime of the GCN. We report numbers on the more complex circuits on an Ubuntu host with an Intel Core i7 processor @2.6GHz with 8 cores and 32GB RAM: the procedure takes 135s for the switched capacitor filter circuit, and 514s for the phased array system” [executed by the processor]. Pg. 3 Sect. II, “Fig. 3 shows a differential OTA and its bipartite graph (without edge labels, for simplicity)”. Fig. 3(b) shows the bipartite graph that represents Vinn and Voutp, terminals, as nodes for the different regions of the device and the connections between the nodes of the device, e.g., the region graph including nodes representing regions and terminals of the device structure file and edges representing connection relationships between the nodes. Further see Sect. II and V. The examiner has interpreted that representing an element-level circuit netlist as an undirected bipartite graph that annotates the element type of the circuit such as a NMOS/PMOS transistor to meet system-level constraints in a bipartite graph with inputs and outputs connected by nodes for the different areas of the device by a processor as a region graph generation module executed by the processor and configured to input a device structure file of a semiconductor device to be simulated, generate a region graph corresponding to the device structure file and output the region graph, the region graph including nodes representing regions and terminals of the device structure file and edges representing connection relationships between the nodes.)
Kunal also teaches “a device determination module executed by the processor and configured to execute a graph artificial neural network model to determine a type of the semiconductor device corresponding to the region graph”. (Pg. 1, Abstract, “The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN)” [execute a graph artificial neural network model] “that identifies netlist elements for circuit blocks at upper levels of the design hierarch” [a device determination module configured to execute a graph artificial neural network model to determine a type of the semiconductor device corresponding to the region graph]. Furthermore, Pg. 4 Sect. V, “The input to the GCN is the circuit graph, G(V, E)”. Furthermore, Pg. 4 Sect. V, “12 features that annotate the element type, e.g., whether it is an NMOS/PMOS transistor, resistor, inductor, capacitor, voltage reference, current reference, or a hierarchical block” [a type of semiconductor device]. Furthermore, Pg. 4 Sect. 5, “The task of the GCN is to (a) identify and extract such features”. Pg. 6 Sect. V, “Our annotation scheme is fast, and is dominated by the runtime of the GCN. We report numbers on the more complex circuits on an Ubuntu host with an Intel Core i7 processor @2.6GHz with 8 cores and 32GB RAM: the procedure takes 135s for the switched capacitor filter circuit, and 514s for the phased array system” [executed by the processor]. Further see Sect. V and Abstract. The examiner has interpreted that identifying element types such as transistor type for circuit blocks and circuit graphs from a netlist using a trained graph convolutional neural network and a processor as a device determination module executed by the processor and configured to execute a graph artificial neural network model to determine a type of the semiconductor device corresponding to the region graph and the type of semiconductor device determined by the device discrimination module.)
Kunal does not specifically teach “an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure”, “a semiconductor device simulator executed by the processor and configured to be initialized based on the initial solution and to perform semiconductor device simulation”, “wherein simulation speed of the semiconductor device simulator is accelerated by using the initial solution corresponding to the semiconductor device structure”, and “a semiconductor device simulation system implemented by a computer system with a processor”.
However, in the same field of endeavor namely modeling electrical parameters from semiconductor devices, Yang teaches “an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure”. (Pg. 4182 Sect. I, “we propose a TCM scheme” [transistor compact model] “based on multigradient neural network (MNN), utilizing the computational graph within the PyTorch framework [26]. This model approach is able to simultaneously capture the transistor dc/ac characteristics such as I–V /Q–V, their high-order derivative terms, e.g., G–V, C–V , dG/dV–V, and dC/dV–V, with one set of neural network” [obtain a current-voltage characteristics for a semiconductor device structure]. “The model creation does not require complete knowledge of detailed underline device physics, and we also show that this model approach could facilitate the prediction of certain electrical characteristics outside the known data range due to the accurate capturing of inherent data curvature”. Pg. 4184 Sect III, “the mathematical equations with all the trained parameters of the established models are written to a Verilog-A file for further circuit simulation purposes” [current-voltage characteristic equation for a semiconductor device structure]. Pg. 4184 Sect. III, “After the processed device data input MOSFitApply, the software will calculate the number of data and give a suitable model structure that includes the number of hidden layers, the number of nodes, and activation function automatically” [for a device structure corresponding a device]. Furthermore, Pg. 4184-4185 Sect. IV, “we take the novel gate-all-around (GAA) Si CSFET as an example to demonstrate the MNN model capability. Si CSFET is a novel field-effect transistor (FET) design first proposed by Liu et al. [31], for which the conventional compact model formulations is not yet available” [for a semiconductor device structure corresponding to the determined type of semiconductor device], and further in Pg. 4185 Sect. IV, “Using the multiphysics framework, we generate the I–V and C–V characteristics of CSFET” [set the current-voltage characteristic equation as an initial solution for the semiconductor device structure for specific example]. Additionally, Pg. 4186 Sect. V, “we argue that this MNN scheme can be used to model linear or nonlinear semiconductor device characteristics of any other semiconductor devices where accurate high-order derivatives’ information is important” [also be used for other examples/different types of devices]. Pg. 6 Sect. V, “Our annotation scheme is fast, and is dominated by the runtime of the GCN. We report numbers on the more complex circuits on an Ubuntu host with an Intel Core i7 processor @2.6GHz with 8 cores and 32GB RAM: the procedure takes 135s for the switched capacitor filter circuit, and 514s for the phased array system” [executed by the processor]. Further see Sect. I and III-V. The examiner has interpreted that generating electrical characteristics for an example novel field-effect transistor (CSFET device) of a suitable model structure which can also be used to model other semiconductor characteristics of other semiconductor devices by use of a processor as an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure.)
Yang also teaches “A semiconductor device simulation system implemented by a computer system with a processor” and “a semiconductor device simulator executed by the processor and configured to be initialized based on the initial solution and to perform semiconductor device simulation”. (Pg. 4184 Sect. III, “After generation the Verilog-A model file by MOSFitApply, device characteristics, such as I–V and C–V, are simulated in circuit netlist using a standard HSPICE simulator” [a semiconductor device simulator configured to be initialized based on the initial solution and to perform semiconductor device simulation]. Pg. 6 Sect. V, “Our annotation scheme is fast, and is dominated by the runtime of the GCN. We report numbers on the more complex circuits on an Ubuntu host with an Intel Core i7 processor @2.6GHz with 8 cores and 32GB RAM: the procedure takes 135s for the switched capacitor filter circuit, and 514s for the phased array system” [semiconductor device simulation system implemented by a computer system with a processor and executed by the processor]. Further see Sect. III-V. The examiner has interpreted the simulating a model for which device characteristics were generated are then simulated using a standard HSPICE simulator using a Ubuntu host with an Intel Core i7 processor as a semiconductor device simulation system and a semiconductor device simulator executed by the processor and configured to be initialized based on the initial solution and to perform semiconductor device simulation.)
Yang also teaches “wherein simulation speed of the semiconductor device simulator is accelerated by using the initial solution corresponding to the semiconductor device structure.” (Pg. 4181 Abstract, “This work reduces the cycle of novel device compact model creation and circuit benchmark simulation from months or weeks to hours” [wherein simulation speed of the semiconductor device simulator is accelerated]. Pg. 4184 Sect. III “As a bridge between process technology and circuit design in modern ICs, the established model should be able to not only accurately fit the data but also converge smoothly in the circuit simulation. After generation the Verilog-A model file by MOSFitApply, device characteristics, such as I–V and C–V, are simulated in circuit netlist using a standard HSPICE simulator, to verify model accuracy and compatibility with SPICE simulation” [using the initial solution corresponding to the semiconductor device structure]. Further see Abstract and Sect. III. The examiner has interpreted that simulating the device characteristics that were generated using a HSPICE simulator to reduce cycle of the circuit simulation benchmark as wherein simulation speed of the semiconductor device simulator is accelerated by using the initial solution corresponding to the semiconductor device structure.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “an initial solution generation module executed by the processor and configured to execute a compact model to obtain a current-voltage characteristic equation for a semiconductor device structure corresponding to the determined type of semiconductor device and set the current-voltage characteristic equation as an initial solution for the semiconductor device structure”, “a semiconductor device simulator executed by the processor and configured to be initialized based on the initial solution and to perform semiconductor device simulation”, “wherein simulation speed of the semiconductor device simulator is accelerated by using the initial solution corresponding to the semiconductor device structure”, and “a semiconductor device simulation system implemented by a computer system with a processor”, as conceptually seen from the teaching of Yang, into that of Kunal because this modification of generating a initial solution for a device type to be simulated by a simulation system for the advantageous purpose of reducing the amount of work and time necessary to run a circuit simulation (Yang, Pg. 4181 Abstract). Further motivation to combine be that Yang and Kunal are analogous art to the current claim are directed to modeling electrical parameters from semiconductor devices.
Kunal and Yang do not specifically teach “wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type”,
However, in the same field of endeavor namely determining electrical parameters for circuit layout designs, Gibson teaches “wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type”. (Para. 0005, “The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit” [region and terminals]. Para. 0062, “the geometric element partitioning unit 403 obtains layout design data from the layout design database 413, and partitions geometric elements in the layout design data into portions” [wherein the nodes of the region graph respectively represent regions]. Para. 0050, “a design rule check process performed by the design rule check module 309 typically will perform two types of operations: "check" operations that confirm whether design data values comply with specified parameters, and "derivation" operations that create derived layer data. A transistor gate design data thus may be created by the following derivation operation: gate=diff AND poly. The results of this operation will be a "layer" of data identifying all intersections of diffusion layer geometric elements with polysilicon layer geometric elements. Likewise, a p-type transistor gate, formed by doping the diffusion layer with n-type material, is identified by the following derivation operation: pgate=nwell AND gate. The results of this operation then will be another "layer" of data identifying all transistor gates (i.e., intersections of diffusion layer geometric elements with polysilicon layer geometric elements) where the geometric elements in the diffusion layer have been doped with n-type material” [represent regions composed of a constituent material and a impurity type]. Furthermore, Para. 0067, “FIG. 7A illustrates one example of how the geometric element 603 may be partitioned at partition boundaries 703-717, forming six geometric element portions 719-729” [partitioning based on boundaries, e.g., represent regions composed of a same constituent material and a same impurity type]. Further see Para. 0005, 0049-0050, and 0062-0069. The examiner has interpreted that partitioning geometric elements that define the contacts, gates, and components of circuit devices based on the identified p-type and n-type transistor gates with the respective doping material and at partition boundaries as wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type” as conceptually seen from the teaching of Gibson, into that of Kunal and Yang because this modification of the creating a region graph with relationships across the separating regions on the device for the advantageous purpose of modeling and analyzing properties and features that may propagate across separating regions on the device (Gibson, Para. 0062-0063). Further motivation to combine be that Yang, Kunal, and Gibson are analogous art to the current claim are directed to determining electrical parameters for circuit layout designs.
As per claim 3, Kunal and Yang do not specifically teach “wherein the region graph generation module re-divides regions of the device structure file based on constituent material and impurity type”, “represents the re-divided regions and terminals of the device structure file as nodes of the region graph”, and “represents connection relationships between the nodes as edges of the region graph, thereby generating the region graph represented by the nodes and the edges.”
However, in the same field of endeavor namely determining electrical parameters for circuit layout designs, Gibson teaches “wherein the region graph generation module re-divides regions of the device structure file based on constituent material and impurity type”. (Para. 0005, “The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit” [region and terminals]. Para. 0062, “the geometric element partitioning unit 403 obtains layout design data from the layout design database 413, and partitions geometric elements in the layout design data into portions” [wherein the region graph generating module re-divides regions of the device structure file]. Para. 0050, “a design rule check process performed by the design rule check module 309 typically will perform two types of operations: "check" operations that confirm whether design data values comply with specified parameters, and "derivation" operations that create derived layer data. A transistor gate design data thus may be created by the following derivation operation: gate=diff AND poly. The results of this operation will be a "layer" of data identifying all intersections of diffusion layer geometric elements with polysilicon layer geometric elements. Likewise, a p-type transistor gate, formed by doping the diffusion layer with n-type material, is identified by the following derivation operation: pgate=nwell AND gate. The results of this operation then will be another "layer" of data identifying all transistor gates (i.e., intersections of diffusion layer geometric elements with polysilicon layer geometric elements) where the geometric elements in the diffusion layer have been doped with n-type material” [based on constituent material and impurity type]. Furthermore, Para. 0067, “FIG. 7A illustrates one example of how the geometric element 603 may be partitioned at partition boundaries 703-717, forming six geometric element portions 719-729” [based on constituent material]. Further see Para. 0005, 0049-0050, and 0062-0069. The examiner has interpreted that partitioning geometric elements that define the contacts, gates, and components of circuit devices based on the identified p-type and n-type transistor gates with the respective doping material and at partition boundaries as wherein the region graph generating module re-divides regions of the device structure file based on constituent material and impurity type).
Gibson also teaches “represents the re-divided regions and terminals of the device structure file as nodes of the region graph”. (Para. 0005, “The geometric elements define the shapes that will be created in various materials to actually manufacture the circuit device components (e.g., contacts, gates, etc.) making up the circuit” [region and terminals]. Para. 0062, “the geometric element partitioning unit 403 obtains layout design data from the layout design database 413, and partitions geometric elements in the layout design data into portions. These geometric element portions are stored as a graph, such as an undirected cyclic graph, in the circuit graph database 411. The graph partitioning unit 405 partitions the nodes of the graph into subgraphs, such that the nodes of each strongly connected geometric element or group of elements are categorized into a single corresponding subgraph” [represents the re-divided regions and terminals of the device structure file as nodes of the region graph]. Further see Para. 0061-0062. The examiner has interpreted that partitioning the geometric elements of the circuit graph into portions into nodes on the graph as represents the re-divided regions and terminals of the device structure file as nodes of the region graph.)
Gibson also teaches “represents connection relationships between the nodes as edges of the region graph, thereby generating the region graph represented by the nodes and the edges.” (Para. 0071, “the geometric element partitioning unit 403 creates a circuit graph describing the relationship of the geometric element portions. For example, FIG. 8A illustrates a circuit graph 801 describing the relationship between the geometric element portions 719-729 shown in FIG. 7A” [generating the region graph represented by the nodes and the edges]. “As seen in this figure, each partition boundary 703-717 is represented in the graph 801 by a corresponding node 803-817, respectively. Edges are placed connecting nodes such that the edges represent the geometric element portions between the corresponding electrical boundaries” [represents connection relationships between the nodes as edges of the region graph]. Further see Para. 0069-0072. The examiner has interpreted that placing edges to connect nodes to represent relationship between the geometric element portions and among its corresponding electrical boundaries in creating a circuit graph as represents connection relationships between the nodes as edges of the region graph, thereby generating the region graph represented by the nodes and the edges.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the region graph generation module re-divides regions of the device structure file based on constituent material and impurity type”, “represents the re-divided regions and terminals of the device structure file as nodes of the region graph”, and “represents connection relationships between the nodes as edges of the region graph, thereby generating the region graph represented by the nodes and the edges” as conceptually seen from the teaching of Gibson, into that of Kunal and Yang because this modification of the creating a region graph with relationships across the separating regions on the device for the advantageous purpose of modeling and analyzing properties and features that may propagate across separating regions on the device (Gibson, Para. 0062-0063). Further motivation to combine be that Yang, Kunal, and Gibson are analogous art to the current claim are directed to determining electrical parameters for circuit layout designs.
As per claim 4, Kunal teaches “wherein the graph artificial neural network model is trained in a supervised manner of a machine learning method by using training data including a pair of the type of semiconductor device and the region graph corresponding to the type of semiconductor device”. (Pg. 4 Sect. V, “The training set for the GCN was taken from several sources” [wherein the graph artificial neural network model is trained by using training data]. Pg. 1, Abstract, “The novel approach in this paper is based on the use of a trained graph convolutional neural network (GCN)” [using the graph artificial neural network trained] “that identifies netlist elements for circuit blocks at upper levels of the design hierarch”. Pg. 4 Sect. V, “Using these sources, two labeled datasets for OTA and radio frequency (RF) sub-blocks have been created with characteristics as listed in Table I” [wherein the graph artificial neural network model is trained in a supervised manner of a machine learning method]. “The OTA bias dataset consists of multiple OTA configuration with appropriate signal and bias subcircuit labels, while the RF data dataset consists of different RF circuits, with labels attached to elements that compose low noise amplifiers (LNAs), mixers and oscillators (OSC)” [using training data including a pair of the type of semiconductor device]. Furthermore, Pg. 4 Sect. V, “12 features that annotate the element type, e.g., whether it is an NMOS/PMOS transistor, resistor, inductor, capacitor, voltage reference, current reference, or a hierarchical block” [types of semiconductor device]. Pg. 4 Sect. V, “The input to the GCN is the circuit graph, G(V, E)” [the region graph corresponding to the type of semiconductor device]. Further see Sect. V. The examiner has interpreted that training a graph convolution neural network from multiple labeled training sets that identify the elements for the RF circuits and whose input into the graph convolution neural network is the circuit graph as wherein the graph artificial neural network model is trained in a supervised manner of a machine learning method by using training data including a pair of the type of semiconductor device and the region graph corresponding to the type of semiconductor device.)
As per claim 6, Kunal teaches “[wherein the initial solution generation module is configured to input information on] the type of semiconductor device determined by the device determination module [and physical quantity for each region].” (Pg. 4 Sect. V, “The input to the GCN is the circuit graph, G(V, E)” [for the region graph generated by the region graph generating module]. Pg. 4 Sect. V, “12 features that annotate the element type, e.g., whether it is an NMOS/PMOS transistor, resistor, inductor, capacitor, voltage reference, current reference, or a hierarchical block” [the type of semiconductor device determined by the device determination module]. Furthermore, Pg. 4 Sect. 5, “The task of the GCN is to (a) identify and extract such features”. Further see Sect. V and Abstract. The examiner has interpreted that identifying element types such as transistor type using a trained graph convolutional neural network as the type of semiconductor device determined by the device determination module.).
Kunal does not specifically teach “wherein the initial solution generation module is configured to input information on the type of semiconductor device determined by the device determination module and physical quantity for each region”, “wherein the compact model is configured to obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device” , and “generate the initial solution by summing the approximate solutions for each region, and provide the initial solution to the semiconductor device simulator.”
However, Yang teaches “wherein the initial solution generation module is configured to input information on the type of semiconductor device determined by the device determination module and the physical quantity for each region”. (Pg. 1485 Sect. IV, “Fig. 4(a) shows a sample CSFET structure designed in TCAD. The lengths of source I/Metal/Source II/Channel/Drain are 5 nm/3 nm/6 nm/12 nm/14 nm, respectively” [the physical quantity for each region, e.g., one for this case]. “The thickness and width of NS are 5 nm and 5 nm/10 nm/15 nm with effective oxide thickness of 0.7 nm. Besides, Source I/Source II are n-type/p-type doped in pMOS with the same concentration of 3 × 1020 cm−3” [wherein the initial solution generation module is configured to input information on the type of semiconductor device]. “Using the multiphysics framework, we generate the I–V and C–V characteristics of CSFET”. Further see Sect. IV. The examiner has interpreted that using the physical dimensions and types of each region of the CSFET as wherein the initial solution generation module is configured to input information on the type of semiconductor device determined by the device determination module and the physical quantity for each region.)
Yang also teaches “wherein the compact model is configured to obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device”. (Pg. 4182 Sect. I, “we propose a TCM” [the transistor compact model] “scheme based on multigradient neural network (MNN), utilizing the computational graph within the PyTorch framework [26]. This model approach is able to simultaneously capture the transistor dc/ac characteristics such as I–V /Q–V, their high-order derivative terms, e.g., G–V, C–V , dG/dV–V, and dC/dV–V, with one set of neural network” [wherein the compact model is configured to obtain approximate solutions of the current-voltage characteristic]. Pg. 4184 Sect III, “the mathematical equations with all the trained parameters of the established models are written to a Verilog-A file for further circuit simulation purposes” [current-voltage characteristic equation]. Pg. 4184-4185 Sect. IV, “we take the novel gate-all-around (GAA) Si CSFET as an example to demonstrate the MNN model capability. Si CSFET is a novel field-effect transistor (FET) design first proposed by Liu et al. [31], for which the conventional compact model formulations is not yet available” [according to the type of semiconductor device input], and further in Pg. 4185 Sect. IV, “Fig. 4(a) shows a sample CSFET structure designed in TCAD. The lengths of source I/Metal/Source II/Channel/Drain are 5 nm/3 nm/6 nm/12 nm/14 nm, respectively” [for the physical quantity of each region, e.g., one for this case]. “The thickness and width of NS are 5 nm and 5 nm/10 nm/15 nm with effective oxide thickness of 0.7 nm. Besides, Source I/Source II are n-type/p-type doped in pMOS with the same concentration of 3 × 1020 cm−3. Using the multiphysics framework, we generate the I–V and C–V characteristics of CSFET” [obtain approximate solutions of the current-voltage characteristic equation for for specific example for the entire device, e.g. for each region]. Further see Sect. I and III-V. The examiner has interpreted that proposing a scheme that utilizes transistor compact models to capture the transistor current-voltage characteristics in mathematical equations for an example novel field-effect transistor of a suitable model structure using the physical dimensions and types of each region of the CSFET to determine its characteristics as wherein the compact model is configured to obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device.)
Yang also teaches “generate the initial solution by summing the approximate solutions for each region, and provide the initial solution to the semiconductor device simulator.” (Pg. 4185 Sect. IV, “Fig. 4(a) shows a sample CSFET structure designed in TCAD. The lengths of source I/Metal/Source II/Channel/Drain are 5 nm/3 nm/6 nm/12 nm/14 nm, respectively” [the physical quantity for each region, e.g., one for this case]. “The thickness and width of NS are 5 nm and 5 nm/10 nm/15 nm with effective oxide thickness of 0.7 nm. Besides, Source I/Source II are n-type/p-type doped in pMOS with the same concentration of 3 × 1020 cm−3. Using the multiphysics framework, we generate the I–V and C–V characteristics of CSFET” [obtains total characteristics of the device, i.e., generate the initial solution by summing the approximate solutions for each region]. Pg. 4184 Sect III, “After generation the Verilog-A model file by MOSFitApply, device characteristics, such as I–V and C–V, are simulated in circuit netlist using a standard HSPICE simulator” [and provide the initial solution to the semiconductor device simulator]. Further see Sect. I and III-V. The examiner has interpreted that generating the current-voltage characteristics of the CSFET and providing the characteristics to HSPICE simulator as generate the initial solution by summing the approximate solutions for each region, and provide the initial solution to the semiconductor device simulator.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the initial solution generation module is configured to input information on the type of semiconductor device determined by the device determination module and physical quantity for each region”, “wherein the compact model is configured to obtain approximate solutions of the current-voltage characteristic equation for the physical quantity of each region according to the type of semiconductor device” , and “generate the initial solution by summing the approximate solutions for each region, and provide the initial solution to the semiconductor device simulator”, as conceptually seen from the teaching of Yang, into that of Kunal because this modification of generating a initial solution for the entire device to be simulated by a simulation system for the advantageous purpose of reducing the amount of work and time necessary to run a circuit simulation (Yang, Pg. 4181 Abstract). Further motivation to combine be that Yang and Kunal are analogous art to the current claim are directed to modeling electrical parameters from semiconductor devices.
Re Claim 7, it is a process claim, having similar limitations of claim 1. Thus, claim 7 is also rejected under the similar rationale as cited in the rejection of claim 1.
Re Claim 9, it is a process claim, having similar limitations of claim 3. Thus, claim 9 is also rejected under the similar rationale as cited in the rejection of claim 3.
Re Claim 10, it is a process claim, having similar limitations of claim 4. Thus, claim 10 is also rejected under the similar rationale as cited in the rejection of claim 4.
Claims 2 and 8 are rejected under 35 U.S.C. § 103 as being unpatentable over Kunal, Yang, and Gibson as applied to claim 1 above, and further in view of US 8,578,316 B1 Joshi, Rajiv et al [herein “Joshi”].
As per claim 2, Kunal, Yang, and Gibson do not specifically teach “wherein the device structure file is generated by a structure generator program or a semiconductor process simulation program.”
However, in the same field of endeavor namely modeling semiconductor devices for simulation, Joshi teaches “wherein the device structure file is generated by a structure generator program or a semiconductor process simulation program.” (Col. 7 Ln 36-45, “Referring to step 300 of FIG. 1, a structure file is generated from the annotated design layout provided at step 100, the device database provided at step 200 and a set of process assumptions for FEOL/BEOL regions outside the FET 40 regions. The generation of the structure file can be automatically performed employing an automated system such as a computer or a computing device configured to run a program. The program for generating the structure file is herein referred to as a full structure generator” [wherein the device structure file is generated by a structure generator program]. Further see Col. 7 Ln. 26 – 62. The examiner has interpreted that generating a structure file from an annotated design layout of a device by a full structure generator as wherein the device structure file is generated by a structure generator program or a semiconductor process simulation program.)
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add “wherein the device structure file is generated by a structure generator program or a semiconductor process simulation program” as conceptually seen from the teaching of Joshi, into that of Kunal, Yang, and Gibson because this modification of generating the device structure file for the advantageous purpose of obtaining a compatible structure file for a simulation that is accurate representation of the device (Joshi, Col.1 Ln. 47-57) and saving on computation costs and time when running a simulation (Joshi, Col.1 Ln. 35-42). Further motivation to combine be that Kunal, Yang, Gibson, and Joshi are analogous art to the current claim are directed to modeling semiconductor devices for simulation.
Re Claim 8, it is a process claim, having similar limitations of claim 2. Thus, claim 8 is also rejected under the similar rationale as cited in the rejection of claim 2.
Response to Arguments
Applicant's arguments filed on November 18, 2025 have been fully considered but they are not persuasive.
Applicant argues that the claim should be rejection under 35 U.S.C. § 112(b) since the claims have been amended, as a whole, and more clearly define the claimed invention (See Applicant’s response, Pg. 9).
MPEP § 2173.05(a)(III) recites “Consistent with the well-established axiom in patent law that a patentee or applicant is free to be his or her own lexicographer, a patentee or applicant may use terms in a manner contrary to or inconsistent with one or more of their ordinary meanings if the written description clearly redefines the terms.”.
The written description does not redefine the term “re-divides” which is used the claim to mean “divide”, while the accepted meaning is “divide again” (see Merriam-Webster definition, “Redivide.” Merriam-Webster.com Dictionary, Merriam-Webster, https://www.merriam-webster.com/dictionary/redivide. Accessed 21 Aug. 2025.). The term is indefinite because the specification does not clearly redefine the term.
Therefore, the examiner has properly identified the term “re-divides” is indefinite because the specification does not clearly redefine the term to mean “divide”.
Applicant argues that the amended claim features are patent eligible under 35 U.S.C. § 101 because the claims do not recite the use of a processor (See Applicant’s response, Pg. 9).
MPEP § 2106.04(a)(2)(III)(A) recites “claims do recite a mental process when they contain limitations that can practically be performed in the human mind, including for example, observations, evaluations, judgments, and opinions”, “claims can recite a mental process even if they are claimed as being performed on a computer”, and “in evaluating whether a claim that requires a computer recites a mental process, examiners should carefully consider the broadest reasonable interpretation of the claim in light of the specification. For instance, examiners should review the specification to determine if the claimed invention is described as a concept that is performed in the human mind and applicant is merely claiming that concept performed 1) on a generic computer, or 2) in a computer environment, or 3) is merely using a computer as a tool to perform the concept. In these situations, the claim is considered to recite a mental process.”
The examiner has provided the rational for the claim limitations that are being directed to a mental process and mathematical concepts in the rejection above, which was not traversed. The applicant is merely claiming that concept performed on a generic computer, or in a computer environment, or is merely using a computer as a tool to perform the concept.
The examiner has properly identified that the claims recite a mental concept as provided in the rejection above is proper under the framework provided in the 2019 Patent Eligibility Guidance and MPEP § 2106.04(a)(2)(III)(C). The claims are directed to judicial exception, an abstract idea.
Applicant’s arguments, see Pg. 9-11, filed November 18, 2025, with respect to the rejection(s) of claims 1 and 7 under 35 U.S.C. 103 as being unpatentable over Kunal in view of Yang has been fully considered and is persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the amended claims and previously cited art, necessitated by the applicant’s amendment, as detailed above and below.
Applicant argues that the combination of references does not teach each and every limitation in the amend claims 1 and 7 because cited references fail to teach “wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type” (See Applicant’s response, Pg. 9-11).
MPEP § 2143.03 states that “All words in a claim must be considered in judging the patentability of that claim against the prior art” and “Examiners must consider all claim limitations when determining patentability of an invention over the prior art.”
While Kunal nor Yang teach this limitation, so the examiner partially agrees with the applicant with respect to the rejection of claims 1 and 7 as amended. However, as similarly mapped in the previous Office Action in claim 5, Gibson discloses “wherein the nodes of the region graph respectively represent regions composed of a same constituent material and a same impurity type” as partitioning geometric elements that define the contacts, gates, and components of circuit devices based on the identified p-type and n-type transistor gates with the respective doping material and at partition boundaries. Additional emphasis has been added to this mapping in the rejection above to the amended limitation.
Therefore, all of the limitations of the amended claims 1 and 7 are disclosed in Kunal, Yang, and Gibson, and the combination of these references renders the claimed invention obvious. Therefore, applicant’s arguments are not persuasive and the rejection of claim 1 and 7 as obvious over Kunal and Yang in view of Gibson has been provided.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ren, Haoxing, George F. Kokai, Walker J. Turner, and Ting-Sheng Ku. "ParaGraph: Layout parasitics and device parameter prediction using graph neural networks." In 2020 57th ACM/IEEE Design Automation Conference (DAC), pp. 1-6. IEEE, 2020 teaches a method for predicting net parasitics and device parameters by converting circuit schematics into graphs and leveraging key modeling techniques such as graph neural networks
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner’s Note: The examiner has cited particular columns and line numbers in the reference that applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. In the case of amending the claimed invention, the applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for the proper interpretation and also to verify and ascertain the metes and bound of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Simeon P Drapeau whose telephone number is (571)-272-1173. The examiner can normally be reached Monday - Friday, 8 a.m. - 5 p.m. ET.
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/SIMEON P DRAPEAU/ Examiner, Art Unit 2188
/RYAN F PITARO/ Supervisory Patent Examiner, Art Unit 2188