DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 17-20 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak et al (US Patent No. 10338656) in view of Packard (US Publication No. 20200035436).
Regarding claim 1, Nayak discloses a computing system (notebook/200, fig. 2, Col. 3 lines 1+) comprising: a receptacle (i.e., 201/USB-C socket; VBUS = pin-E; female-side); a bulk capacitor (i.e., 1OmicroF/50V in path 213; driving pins: A, B, C, D, E); a bus voltage line (213/VBUS/pin-C) coupled (i.e., the bus voltage line via pins C, D and the receptacle via pin-E) to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) and the bulk capacitor (i.e., 1OmicroF/50V in path 213; driving pins: A, B, C, D, E); and a controller (i.e., 202; VBUS_P_CTRL = 11 = pin-C; VBUS_C_CTRL = 12 = pin-D) coupled to the bus voltage line (213/VBUS/pin-C) and the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side), the controller (i.e., 202; VBUS_P_CTRL = 11 = pin-C; VBUS_C_CTRL = 12 = pin-D) including a set of instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), which when executed by the controller (i.e., 202; VBUS_P_CTRL=11=pin-C; VBUS_C_CTRL=12 = pin-D), cause the controller (i.e., 202; VBUS_P_CTRL = 11 = pin-C; VBUS_C_CTRL = 12 = pin-D) to: detect (i.e., via ESD-sensor 242) a signal (i.e., indication for a potential ESD event) from a piezoelectric membrane (i.e., 101/connector plug terminals D+/D- section, which is subjected to human contact [ESD] and/or movement regardless of the polarity’s orientation; human-body-model [HBM] configuration, see for example fig. 1, Col. 2 lines 24+) of an adapter plug (i.e., 100/USB-C plug; male-side) adjacent to (i.e., male/female scheme) the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side), wherein the signal (i.e., indication for a potential ESD event) indicates user contact (i.e., HBM) with the adapter plug (i.e., 100/USB-C plug; male-side), and disconnect (i.e., neutralize) the bulk capacitor (i.e., ImicroF/213; driving pins: A, B, C, D, E) from the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) in response to a disconnect condition (i.e., protection against ESD event) associated with the user contact (i.e., HBM).
Nayak does not explicitly disclose one or more switches coupled between the bulk capacitor and the receptacle; wherein to decouple the bulk capacitor from the receptacle, the controller is to control the one or more switches to decouple the bulk capacitor from the receptacle.
Packard discloses a voltage protective device (i.e., 300'; see for example fig. 4, para. [0032]); wherein one or more switches (i.e., such as Q1, Z1; see for example fig. 4, para. [0032]) coupled between the bulk capacitor (i.e., C2; see for example fig. 4, para. [0032]) and the receptacle (i.e., SCR 308 clamped to the receptacle terminals 30 and 32; see for example fig. 4, para. [0032]); wherein to decouple (i.e., When open, reset switch 118′ decouples capacitor C2 from SCR 308; see for example fig. 4, para. [0032]) the bulk capacitor (i.e., C2; see for example fig. 4, para. [0032]) from the receptacle (i.e., SCR 308 clamped to the receptacle terminals 30 and 32; see for example fig. 4, para. [0032]), the controller (i.e, 310'; see for example fig. 4, para. [0032]) is to control (i.e., When there is an overvoltage condition, diode Z1 forward biases to turn on Q1. Q1 suppresses voltage on capacitor C2 as before, however, when Q1 is OFF, capacitor C2 is being charged by current through resistor R5′ even when reset button 17 is not being depressed. When open, reset switch 118′ decouples capacitor C2 from SCR 308; see for example fig. 4, para. [0032]) the one or more switches (i.e., such as Q1, Z1; see for example fig. 4, para. [0032]) to decouple (i.e., When open, reset switch 118′ decouples capacitor C2 from SCR 308; see for example fig. 4, para. [0032]) the bulk capacitor (i.e., C2; see for example fig. 4, para. [0032]) from the receptacle (i.e., SCR 308 clamped to the receptacle terminals 30 and 32; see for example fig. 4, para. [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the switch device in Nayak, as taught by Packard, as it provides the advantage of optimizing the circuit design towards protecting the receptacle against unexpected charges.
Regarding claim 2, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), when executed, further cause the controller (i.e., 202; VBUS P_CTRL = 11 = pin-C; VBUS_C_CTRL=12= pin-D) to monitor the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) for the disconnect condition (i.e., protection against ESD event) in response to the signal (i.e., indication for a potential ESD event).
Regarding claim 3, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the disconnect condition (i.e., protection against ESD event) includes a configuration channel line (i.e., such as CC1, CC2) state change (i.e., binary format as 0/1) within a predetermined amount of time (i.e., differential signal versus time, see for example fig. 6, Col. 9 lines 39+).
Regarding claim 4, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the disconnect condition (i.e., protection against ESD event) includes a bus voltage reduction (i.e., such as sideband-use-terminals SBU1, SBU2) within a predetermined amount of time (i.e., differential signal versus time, see for example fig. 6, Col. 9 lines 39+).
Regarding claim 6, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); further including an input capacitor (i.e., ImicroF/35V in path 213; driving pins: A, B, C, D, E) connected to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side), wherein the input capacitor (i.e., 1ImicroF/35V in path 213; driving pins: A, B, C, D, E) is to remain connected (i.e., no prior switch at the source-point/charge) to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) while the bulk capacitor (i.e., L1OmicroF/50V in path 213; driving pins: A, B, C, D, E) is disconnected (i.e., a switch at the sink-point/discharge) from the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side).
Regarding claim 7, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the signal (i.e., indication for a potential ESD event) is detected (i.e., via ESD-sensor 242) via a configuration channel line (i.e., such as CC1, CC2) and the instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), when executed, further cause the controller (i.e., 202; VBUS_P_CTRL = 11 = pin-C; VBUS_C_CTRL = 12 = pin-D) to negotiate a power delivery setting (i.e., such as sideband-use-terminals SBU1, SBU2) with the adapter plug (i.e., 100/USB-C plug; male-side) via the configuration channel line (i.e., such as CC1, CC2).
Regarding claim 8, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein disconnection (i.e., neutralize/discharge) of the bulk capacitor (i.e., L1OmicroF/50V in path 213; driving pins: A, B, C, D, E) from the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) prevents a current arc (i.e., protection against ESD event) from the adapter plug (i.e., 100/USB-C plug; male-side, fig. 1, Col. 2 lines 24+) to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side).
Regarding claim 17, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); at least one computer readable storage medium (notebook/200, fig. 2, Col. 3 lines 1+), comprising a set of instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), which when executed by a computing system (i.e., such as 222), cause the computing system (i.e., such as 222) to: detect a signal (i.e., indication for a potential ESD event) from a piezoelectric membrane (i.e., 101/connector plug terminals D+/D- section, which is subjected to human contact [ESD] and/or movement regardless of the polarity orientation; human-body-model [HBM] configuration, see for example fig. 1, Col. 2 lines 24+) of an adapter plug (i.e., 100/USB-C plug; male-side), wherein the signal (i.e., indication for a potential ESD event) indicates user contact (i.e., HBM) with the adapter plug (i.e., 100/USB-C plug; male-side); and disconnect (i.e., neutralize) a bulk capacitor (i.e., LOmicroF/50V in path 213; driving pins: A, B, C, D, E) from a receptacle (i.e., 201/USB- C; VBUS = pin-E; female-side) adjacent to (i.e., male/female scheme) the adapter plug (i.e., 100/USB-C plug; male-side) in response to a disconnect condition (i.e., protection against ESD event) associated with the user contact (i.e., HBM).
Packard furthermore discloses (i.e., 300'; see for example fig. 4, para. [0032]); and control (i.e., When there is an overvoltage condition, diode Z1 forward biases to turn on Q1. Q1 suppresses voltage on capacitor C2 as before, however, when Q1 is OFF, capacitor C2 is being charged by current through resistor R5′ even when reset button 17 is not being depressed. When open, reset switch 118′ decouples capacitor C2 from SCR 308; see for example fig. 4, para. [0032]) the one or more switches (i.e., such as Q1, Z1; see for example fig. 4, para. [0032]) coupled between the bulk capacitor (i.e., C2; see for example fig. 4, para. [0032]) and receptacle (i.e., SCR 308 clamped to the receptacle terminals 30 and 32; see for example fig. 4, para. [0032]) to decouple (i.e., When open, reset switch 118′ decouples capacitor C2 from SCR 308; see for example fig. 4, para. [0032]) the bulk capacitor (i.e., C2; see for example fig. 4, para. [0032]) from the receptacle (i.e., SCR 308 clamped to the receptacle terminals 30 and 32; see for example fig. 4, para. [0032]).
Regarding claim 18, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), when executed, further cause the computing system (i.e., such as 222) to monitor the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) for the disconnect condition (i.e., protection against ESD event) in response to the signal (i.e., indication for a potential ESD event).
Regarding claim 19, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the disconnect condition (i.e., protection against ESD event) includes a configuration channel line (i.e., such as CC1, CC2) state change (i.e., binary format 0/1) within a predetermined amount of time (i.e., differential signal versus time, see for example fig. 6, Col. 9 lines 39+).
Regarding claim 20, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the disconnect condition (i.e., protection against ESD event) includes a bus voltage reduction (i.e., such as sideband-use-terminals SBU1, SBU2) within a predetermined amount of time (i.e., differential signal versus time, see for example fig. 6, Col. 9 lines 39+).
Regarding claim 22, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein an input capacitor (i.e., ImicroF/35V in path 213; driving pins: A, B, C, D, E) is to remain connected (i.e., no prior switch at the source-point/charge) to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) while the bulk capacitor (i.e., 10microF/50V in path 213; driving pins: A, B, C, D, E) is disconnected (i.e., a switch at the sink-point/discharge) from the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side).
Regarding claim 23, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein the signal (i.e., indication for a potential ESD event) is detected (i.e., via ESD-sensor 242) via a configuration channel line (i.e., such as CC1, CC2) and the instructions (i.e., such as execution signals from embedded controller 232 and USB host controller 242), when executed, further cause the computing system (i.e., such as 222) to negotiate a power delivery setting (i.e., such as sideband-use-terminals SBU1, SBU2) with the adapter plug (i.e., 100/USB-C plug; male-side) via the configuration channel line (i.e., such as CC1, CC2).
Regarding claim 24, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); wherein disconnection (i.e., neutralize/discharge) of the bulk capacitor (i.e., 10microF/50V in path 213; driving pins: A, B, C, D, E) from the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side) prevents a current arc (i.e., protection against ESD event) from the adapter plug (i.e., 100/USB-C plug; male-side) to the receptacle (i.e., 201/USB-C; VBUS = pin-E; female-side).
Claims 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak et al (US Patent No. 10338656) in view of Packard (US Publication No. 20200035436) and further in view of Wu et al (US Patent No. 10498090).
Regarding claim 9, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above.
Nayak further discloses (notebook/200, fig. 2, Col. 3 lines 1+); the computing system (notebook/200, fig. 2, Col. 3 lines 1+), and an adapter plug (i.e., 100/USB-C plug; male-side).
Neither Nayak nor Packard explicitly discloses a housing; a plurality of contacts positioned within the housing, wherein the plurality of contacts includes one or more configuration channel contacts; and a piezoelectric membrane positioned on an external surface of the housing, wherein the piezoelectric membrane is electrically connected to the one or more configuration channel contacts.
Wu discloses cable connector assembly (100, fig. 4, Col. 4 lines 40+) includes an electrical connector and a cable connected with the electrical connector; wherein a housing (110); a plurality of contacts (111) positioned within the housing (110), wherein the plurality of contacts (111) includes one or more configuration channel contacts (122); and a piezoelectric membrane (12) positioned on an external surface (1310) of the housing (110), wherein the piezoelectric membrane (12) is electrically connected to the one or more configuration channel contacts (122).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the USB plug assembly in Nayak, as taught by Wu, as it provides the advantage of protecting the internal connections, providing durability, and ensuring proper signal integrity.
Regarding claim 10, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+); the adapter plug (i.e., 100/USB-C plug; male-side), wherein user contact (i.e., HBM) with the piezoelectric membrane (i.e., 101/connector plug terminals D+/D- section, which is subjected to human contact [ESD] and/or movement regardless of the polarity orientation; human-body-model [HBM] configuration, see for example fig. 1, Col. 2 lines 24+) is to generate a signal (i.e., indication for a potential ESD event) on the one or more configuration channel contacts (i.e., such as CC1, CC2).
Regarding claim 11, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); wherein the piezoelectric membrane (1302/1312) is electrically connected to the one or more configuration channel contacts (122) via an electrically conductive pillar (124).
Regarding claim 12, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); wherein the plurality of contacts (111) is compliant with a Universal Serial Bus (USB) Type-C standard (i.e., the electrical connector 10 conforms to the USB C specification, see for example fig. 1, Col. 4 lines 40+).
Regarding claim 13, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); wherein the adapter plug (100) supports standard power range power delivery (i.e., the electrical connector 10 conforms the power specs such as pair of large power core wires 212 is connected with the circuit board 12, so that it can achieve the total 5 A current transmission, low power loss, low temperature rise, voltage drop of 500 mv, and the temperature rise will not beyond 25 degree during the using; see for example fig. 9, Col. 4 lines 40+).
Regarding claim 14, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); wherein the adapter plug (100) supports standard power range power delivery (i.e., the electrical connector 10 conforms the power specs such as pair of large power core wires 212 is connected with the circuit board 12, so that it can achieve the total 5 A current transmission, low power loss, low temperature rise, voltage drop of 500 mv, and the temperature rise will not beyond 25 degree during the using; see for example fig. 9, Col. 4 lines 40+).
Regarding claim 15, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); wherein the plurality of contacts (111) further includes one or more bus voltage contacts (i.e., such as 125, 126).
Regarding claim 16, Nayak in view of Packard and the teachings of Nayak as modified by Packard have been discussed above. Also, the teachings of Nayak as modified by Wu have been discussed above as well.
Nayak further discloses (100, fig. 1, Col. 2 lines 24+).
Wu furthermore discloses (100, fig. 4, Col. 4 lines 40+); further including: a circuit board (12) coupled to the plurality of contacts (111); and a wiring harness (21) coupled to the circuit board (12).
Claims 5 and 21 are cancelled.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838