CTNF 17/852,979 CTNF 85929 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 02/11/2026 Response to Arguments Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on BRASSFIELD et al. 20200211760 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. 07-37 AIA Applicant's arguments filed on 02/11/2026 against Kawabata in US 20180138131 have been fully considered but they are not persuasive. Kawabata discloses an inductor coil (coil 32, FIG. 20, [0069]) mounted to the substrate (20/23/25/26); and a magnetic material (40, FIG. 20, [0126]; noting 40 is a composite material comprising magnetic particles 5/6 suspended in insulating layer 4, FIG. 6, [0081]) encapsulating the semiconductor die (31), the inductor (32), and the metal interconnects (24), the magnetic material filling a space within the inductor coil to form a magnetic core of the inductor (note that since the inductor coil inherently has spacing and magnetic material when forming would necessary be filling a space within the inductor coil to form a magnetic core of the inductor) . Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 7-8 and 23-25 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by BRASSFIELD et al. 20200211760 . PNG media_image1.png 727 526 media_image1.png Greyscale Regarding claim 1, fig. 6 of BRASSFIELD discloses an integrated circuit comprising: a substrate 210; a semiconductor die (see fig. 1 for semiconductor device and a power supply controller 204 and/or discrete transistors – note discrete transistor is a type of semiconductor die and it has been known that ON and OFF of the switching element is controlled by a power supply controller constituted by, for example, a semiconductor); metal interconnects (par [0025] - components may be affixed to pads on the surface of the module substrate by solder paste), the semiconductor die being mounted to the substrate via the metal interconnects; an inductor (par [0036] - molded inductor comprising the winding now shown as 302 in figs. 5-6) mounted to the substrate; and a magnetic material (par [0036] - magnetic molding material 502 and magnetic core 506 form a magnetic material and together as a whole) encapsulating the semiconductor die, the inductor, and the metal interconnects, the magnetic material filling a space within the inductor to form a magnetic core of the inductor (see fig. 6). Regarding claim 7, fig. 6 of BRASSFIELD discloses wherein the inductor includes a coil portion 302 and a stilt portion 404, the stilt portion coupled to the substrate. Regarding claim 8, fig. 6 of BRASSFIELD discloses wherein the coil portion is over the semiconductor die 204. Regarding claim 23, fig. 6 of BRASSFIELD discloses wherein the magnetic material fills gaps between individual coils of the coil portion. Regarding claim 24, fig. 6 of BRASSFIELD discloses wherein the coil portion has an opening between the 302 stacks) facing sideways in a direction parallel to the substrate. Regarding claim 25, fig. 6 discloses wherein the coil portion has an opening facing the semiconductor die 204 in a direction perpendicular to the substrate . 07-15 AIA Claim s 1-3 and 10-11 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kawabata in US 20180138131 (hereinafter Kawabata) . Regarding claim 1 , Kawabata teaches in FIGS. 6, 20 and related text, an integrated circuit (13b, [0126]) comprising: a substrate (elements 20/23/25/26 comprise a substrate [0070], FIG. 20); a semiconductor die (31, FIG. 20, [0069]); metal interconnects (24, FIG. 20, [0069]), the semiconductor die (31) being mounted to the substrate (20/23/25/26) via the metal interconnects (24); an inductor coil (coil 32, FIG. 20, [0069]) mounted to the substrate (20/23/25/26); and a magnetic material (40, FIG. 20, [0126]; noting 40 is a composite material comprising magnetic particles 5/6 suspended in insulating layer 4, FIG. 6, [0081]) encapsulating the semiconductor die (31), the inductor (32), and the metal interconnects (24), the magnetic material filling a space within the inductor coil to form a magnetic core of the inductor (note that since the inductor coil inherently has spacing and magnetic material when forming would necessary be filling a space within the inductor coil to form a magnetic core of the inductor). Regarding claim 2 , Kawabata teaches the integrated circuit of claim 1. Kawabata further teaches wherein the magnetic material (40) includes: metal particles (5/6, FIG. 6, [0081]) coated with a first insulation material (7, FIG. 6, [0088]); and a second insulation material (4, FIG. 6, [0081]) in which the coated metal particles (5/6) are suspended, and the second insulation material (4) includes an epoxy resin ([0081]). Regarding claim 3 , Kawabata teaches the integrated circuit of claim 2. Kawabata further teaches wherein the first insulation material (7, Fig. 6) includes a silicon oxide material ([0088]). Regarding claim 10 , Kawabata teaches the integrated circuit of claim 1. Kawabata further teaches wherein the metal interconnects (24, FIG. 20) are first metal interconnects, and the substrate (20/23/25/26) includes: first metal pads (23, FIG. 20, [0070]) on a first side (21, FIG. 20, [0067]) of the substrate (20/23/25/26), the first metal pads (23) coupled to the first metal interconnects (24) and to the inductor (32, FIG. 20); second metal pads (26, FIG. 20, [0070]) on a second side (22, FIG. 20, [0069]) of the substrate opposite to the first side (21); an insulation layer (20 can be one of various insulators, [0069]) between the first side (21) and the second side (22); and second metal interconnects (25, FIG. 20, [0070]) in the insulation layer (20) and coupled between the first metal pads (23) and the second metal pads (26). Regarding claim 11 , Kawabata teaches the integrated circuit of claim 10. Kawabata further teaches wherein: the first metal pads (34) and the second metal interconnects (25) include a Copper metal ([0070]); the second metal pads (26) include at least one of a Palladium metal or a Silver metal [0070]; and the insulation layer (20) includes at least one of: a polymer, an Ajinomoto Build-up Film, or a ceramic material (liquid crystal polymer [0069]) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 4, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Shimada in US 2004/0258552 A1 (hereinafter Shimada) . Regarding claim 4 , Kawabata teaches the integrated circuit of claim 2. Kawabata does not explicitly teach wherein the first insulation material includes a phosphate material. Shimada teaches in FIG. 1 and related text, a compound magnetic material comprising magnetic particles (10, [0046]), wherein a first insulation material (20, [0046]) includes a metal oxide including phosphorus (i.e. a phosphate, [0037]), in order to provide a thinner coating covering the surface of the magnetic particle and enable a high packing density of magnetic particles ([0030]). Kawabata and Shimada are analogous art to the claimed invention because they both are directed at compound magnetic materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata in view of Shimada because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first insulation material of Kawabata to include a phosphate material, as taught by Shimada, with the purpose of creating a thinner coating and increasing the packing density of magnetic particles (Shimada, [0030]), since Kawabata is also concerned with packing density of magnetic particles (Kawabata, [0087]) . 07-21-aia AIA Claim s 7 and 8, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Hebert in US 2017/0053904 A1 (hereafter, Hebert) . Regarding claim 7, Kawabata teaches the integrated circuit of claim 1. Kawabata further teaches wherein the inductor (32) includes a coil portion ([0069]). Kawabata does not explicitly teach wherein the inductor includes a stilt portion, the stilt portion coupled to the substrate. Hebert teaches in FIG. 11 and related text, an inductor (1402, [0045]) that includes a stilt portion (1404, [0045]), the stilt portion (1405) coupled to a substrate (1401, [0045]), in order to stack the inductor over additional circuit elements (see FIG. 11, [0045]). Kawabata and Hebert are analogous art to the claimed invention because they both are directed at integrated circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata in view of Hebert because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductor as taught by Kawabata to include a stilt portion as taught by Hebert with the purpose of stacking the inductor over additional circuit elements (Hebert, [0045]). Regarding claim 8 , Kawabata as modified by Hebert teaches the integrated circuit of claim 7. Kawabata does not explicitly teach wherein the coil portion is over the semiconductor die. Hebert teaches in FIG. 11 and related text, an inductor (1405) is over a semiconductor die (102, [0045]), in order to optimize the electrical properties of the device relative to the device footprint ([0048]). Kawabata and Hebert are analogous art to the claimed invention because they both are directed at integrated circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata in view of Hebert because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductor as taught by Kawabata such that the coil portion is over the semiconductor die, as taught by Hebert, with the purpose optimizing the electrical properties of the device relative to the device footprint (Hebert, [0048]) . 07-21-aia AIA Claim 9, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Hebert and in view of Lambert in US 9,230,944 A1 (hereinafter Lambert) . Regarding claim 9 , Kawabata as modified by Hebert teaches the integrated circuit of claim 7. Kawabata does not explicitly teach further comprising a capacitor encapsulated in the magnetic material, wherein the coil portion is over the capacitor. Lambert teaches in FIG. 6 and related text, a capacitor (614, [Col. 6, lines 23-24]) encapsulated in an encapsulation material (622, [Col. 6, lines 30-31]), wherein a coil portion (inductor 620, [Col. 6 line 28]) is over the capacitor (614), in order to provide torsional rigidity to a package assembly during the fabrication process ([Col. 6, line 15]). Kawabata, Hebert, and Lambert are analogous art to the claimed invention because they all are directed at integrated circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata in view of Hebert and Lambert because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined structure of Kawabata and Hebert such that integrated circuit comprises a capacitor encapsulated in the magnetic material, wherein the coil portion is over the capacitor, as taught by Lambert, with the purpose of providing torsional rigidity to a package assembly during the fabrication process (Lambert [Col. 6, line 15]) . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata in view of Albers in US 2016/0358897 A1 (hereinafter Albers) . Regarding claim 12 , Kawabata teaches the integrated circuit of claim 11. Kawabata does not explicitly teach further comprising a solder resist layer on the second side. Albers teaches in FIG. 6 and related text, an integrated circuit (100, [0032]) comprising a solder resist layer (180, [0033]) on a side of a substrate (160, [0033]) opposite to passive components (130A, 140A, [0032]) and first metal pads (120, [0029]), the solder resist layer (180) being on the same side of the substrate as second metal pads (170, [0033]), in order to create a package assembly with a reduced footprint ([0027]). Kawabata and Albers are analogous art to the claimed invention because they both are directed at integrated circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kawabata in view of Albers because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit as taught by Kawabata such that it further comprises a solder resist layer on the second side, as taught by Albers, with the purpose of creating a package assembly with reduced footprint (Albers, [0027]). It is also noted that a solder resist layer would facilitate the integration of Kawabata’s invention of Fig. 1 with additional circuitry or package components. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893 Application/Control Number: 17/852,979 Page 2 Art Unit: 2893 Application/Control Number: 17/852,979 Page 3 Art Unit: 2893 Application/Control Number: 17/852,979 Page 4 Art Unit: 2893 Application/Control Number: 17/852,979 Page 5 Art Unit: 2893 Application/Control Number: 17/852,979 Page 6 Art Unit: 2893 Application/Control Number: 17/852,979 Page 7 Art Unit: 2893 Application/Control Number: 17/852,979 Page 8 Art Unit: 2893 Application/Control Number: 17/852,979 Page 9 Art Unit: 2893 Application/Control Number: 17/852,979 Page 10 Art Unit: 2893 Application/Control Number: 17/852,979 Page 11 Art Unit: 2893
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