Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. Applicant’s IDs filed on 12/15/2025 have been fully considered and the Notice of Allowance of previous office action mailed on 8/12/2025 is hereby vacated, a new ground(s) of rejection as presented herein.
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Harriman et al. (Pub. No. US20130205053) in view of Iyer et al. (Pub. No. US 20180095923)
As per claim 1, Harriman discloses an apparatus comprising:
protocol circuitry (fig.14, PCIe/multi-protocol interconnect adapter) to implement a particular interconnect protocol, wherein the particular interconnect protocol defines a particular data format (fig.16 and paragraph 81-84, the multi-protocol interconnect layers/fabric, in the form multi-protocol interconnect packets), and the protocol circuitry is to:
receive an indication that a particular mode in a plurality of modes (paragraph 72, I/O hot-plug indication) associated with the particular interconnect protocol (paragraph 35, a multi-protocol switching fabric 114 configured to carry multiple I/O protocols) is to be utilized on a link (paragraph 90, the TLP exchanged with the data link layer), and a plurality of flit formats are defined to correspond to the plurality of modes (paragraph 56, the path may be assigned a locally unique identifier (e.g., Hop ID) that may be carried in the header of all the packets that are associated with the path);
generate data to be sent on the link (fig.17 & paragraph 90, the TLP exchanged with the data link layer), wherein the data is generated to adapt the particular data format to a particular flit format in the plurality of flit formats defined for use on the link in the particular mode (paragraph 47, the protocol adaptation function that built into the switch port to encapsulate the mapped I/O protocol packets into I/O packets that flow over the multi-protocol switching fabric) and adapting the particular data format to the particular flit format comprises providing a set of reserved fields (fig.17, adapter added TLP Marker, reserved bits as further cites in paragraph 90) to be completed by an adapter block positioned between the protocol circuitry and a physical layer block ( fig.14, PCIe Adapter layer); and
send the data to the adapter block to prepare the data for transmission over the link by the physical layer block (paragraph 90-91, the TLP exchanged with the data link layer may include the sequence number and link).
Harriman discloses all the limitations as the above but does not explicitly disclose the link is a die-to-die (D2D) link to connect a first die to a second die. However, Iyer discloses this. (fig.10, and paragraph 75, the transmission of PCIe packets over a multichip package link, MCPL)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Iyer with the teaching of Harriman so as to provide the system with a chip-to-chip configuration so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 2, Harriman wherein the indication is received from the adapter block, the adapter block is to populate the set of reserved fields with information prior to transmission of the data over the link (paragraph 71, a multi-level hot-plug signaling scheme to support the tunneling of multiple I/O protocols over a common I/O interconnect).
As per claim 3, Harriman wherein the set of reserved fields are to be populated by the protocol circuitry under a native version of the particular interconnect protocol, but are instead populated by the adapter blocks in the data based on the particular mode. (paragraph 71, a multi-level hot-plug signaling scheme to support the tunneling of multiple I/O protocols over a common I/O interconnect)
As per claim 4, Harriman wherein the protocol circuitry populates the set of reserved fields with all zeroes based on the particular mode (fig.17 & paragraph 90, reserved bits).
As per claim 5, Harriman wherein the set of reserved fields comprises a cyclic redundancy check (CRC) field (fig.17 & paragraph 90, link CRC).
As per claim 6, Harriman wherein the set of reserved fields comprises a header field (fig.17 & paragraph 90, reserved bits).
As per claim 7, Harriman wherein the indication is based on characteristics of the link determined during link training (paragraph 89, when the adapters recognize the existence of the established link, each adapter may be required to indicate to its corresponding PCIe stack that link training be initiated.)
As per claim 8, Harriman wherein the characteristics comprise whether the link includes extra lanes provisioned for lane repair on the link, and protocol data in a portion of the particular data format is allocated for transmission using the extra lanes (paragraph 121, link width and speed mechanisms may be applied such that the bandwidth allocated to the PCIe link 2102 over the multi-protocol I/O interconnect 2104 may be accurately reflected in the PCIe reporting mechanisms).
As per claim 9, Harriman wherein the particular mode is selected from a plurality of modes, and the plurality of modes comprise a standard flit mode, an optimized mode, and a raw mode (paragraph 56, unique identifier (e.g., Hop ID) that may be carried in the header of all the packets that are associated with the path).
As per claim 10, Harriman wherein the protocol circuitry is to generate data to include reserved portions to be completed by the adapter block in the standard mode and the optimized mode, and the protocol circuitry is to generate data in unmodified form in the raw mode (paragraph 47, the protocol adaptation function that may be built into the switch port to encapsulate the mapped I/O protocol packets into I/O packets that flow over the multi-protocol switching fabric), wherein the adapter block is to pass data generated by the protocol circuitry to the physical layer block as-is in the raw mode (paragraph 121, PCIe mechanisms for software notification of link bandwidth changes may be used to indicate changes to multi-protocol I/O interconnect bandwidth allocated to PCIe).
As per claim 11, Harriman wherein the set of reserved fields are defined according to a mapping for the particular interconnect protocol (paragraph 56, unique identifier (e.g., Hop ID) that may be carried in the header of all the packets that are associated with the path).
As per claim 12, Harriman wherein the particular interconnect protocol comprises one of Peripheral Component Interconnect Express (PCIe) or Compute Express Link (CXL), and a respective predefined mapping is provided for each of the standard mode, the optimized mode, and raw mode for the particular interconnect protocol (paragraph 121, link width and speed mechanisms may be applied such that the bandwidth allocated to the PCIe link 2102 over the multi-protocol I/O interconnect 2104 may be accurately reflected in the PCIe reporting mechanisms).
As per claim 13, Harriman wherein the particular flit format is defined in another interconnect protocol different from the particular interconnect protocol (paragraph 35, a multi-protocol switching fabric 114 configured to carry multiple I/O protocols).
As per claims 14 and 17, Harriman discloses a method comprising:
determining that a particular operational mode in a plurality of different operational modes for a particular interconnect protocol (paragraph 72, I/O hot-plug indication) is supported by both a first I/O interconnect (paragraph 45, an integrated circuit die packaged within the processor) and a second I/O interconnect for use on a link (paragraph 35, control one or more I/O links), wherein the first I/O interconnect and the second I/O interconnect are to be connected by the link (paragraph 71, a multi-level hot-plug signaling scheme to support the tunneling of multiple I/O protocols over a common I/O link);
generating data, at a protocol layer of the first I/O interconnect, to be sent over the link to the second I/O interconnect (fig.17 & paragraph 90, the TLP exchanged with the data link layer), wherein the protocol layer is to implement the particular interconnect protocol and the particular interconnect protocol defines a particular data format (fig.16 and paragraph 81-84, the multi-protocol interconnect layers/fabric, in the form multi-protocol interconnect packets);
converting the data from the particular data format to a flit format defined for use on the link to generate adapted data based on the particular operational mode (paragraph 71, a multi-level hot-plug signaling scheme to support the tunneling of multiple I/O protocols over a common I/O interconnect); and
passing the adapted data from the protocol layer to an adapter block of the first I/O, wherein the adapter block ( fig.14, PCIe Adapter layer) is positioned between the protocol layer (paragraph 35, a multi-protocol switching fabric 114 configured to carry multiple I/O protocols) and a physical layer (PHY) block of the first I/O, wherein the PHY block is to implement a physical layer of the link (paragraph 90-91, the TLP exchanged with the data link layer may include the sequence number and link).
Harriman discloses all the limitations as the above but does not explicitly disclose the link is a die-to-die (D2D) link to connect a first die to a second die. However, Iyer discloses this. (fig.10, and paragraph 75, the transmission of PCIe packets over a multichip package link, MCPL)
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Iyer with the teaching of Harriman so as to provide the system with a chip-to-chip configuration so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
As per claim 15, Harriman wherein the flit format comprises a set of reserved fields to replace fields defined in the particular interconnect protocol, and the adapter block is complete the set of reserved fields before forwarding the adapted data to the PHY block ((paragraph 56, unique identifier (e.g., Hop ID) that may be carried in the header of all the packets that are associated with the path).
As per claim 16, Harriman the method further comprising sending the adapted data with the completed set of reserved fields to the second I/O interconnect over the link. (paragraph 56, unique identifier (e.g., Hop ID) that may be carried in the header of all the packets that are associated with the path).
As per claim 18, Harriman discloses wherein the first die comprises a processor device, and the second I/O interconnect comprises one of another processor device, a hardware accelerator, or an input/output (I/O) device. (paragraph 45, an integrated circuit die packaged within the processor)
As per claim 19, Harriman wherein the first I/O interconnect and the second I/O interconnect are on a same package (paragraph 45, an integrated circuit die packaged within the processor 202. In some implementations, the integrated circuit die of the processor 202 may include one or more devices)
As per claim 20, Harriman wherein the first I/O interconnect comprises a first retimer, the second I/O interconnect comprises a second retimer, the first I/O interconnect and the second I/O interconnect are on separate packages, and the link implements an off-package interconnect. (paragraphs 46-47, the switches 316a, 316b each optionally include a time management unit 330a, 330b for use in distributing and synchronizing time throughout the multi-protocol switching fabric, the protocol adaptation function that may be built into the switch port to encapsulate the mapped I/O protocol packets into I/O packets that flow over the multi-protocol switching fabric.)
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Dukes [Pub. No. US20210232520] discloses a protocol to have multiple flit types that are predefined and understood by link layer and logPHY.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184