Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to amendment and RCE filed on 1/23/2026. Claims 1, 3-5, 9-10, 12, 16 and 19-20 have been amended. No claims have been cancelled, claims 1-20 are still pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Applicant’s Arguments
Applicant’s arguments, see page 6, filed 1/23/2026, with respect to the rejection(s) of claim(s) 1-20 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wang et al., US 8,359,421 B2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al., US 8,352,669 B2, in view of Wang et al., US 8,359,421 B2.
Regarding claims 1, 9 and 16, Wu teaches an integrated circuit (it is taught as buffered crossbar switch system 100) comprising:
logic circuits (col.2, lines 49-60; processing unit 102 might be a multi-core processor. For example, processing unit 102 might include N processors, where N is an integer greater than or equal to 1. As shown in FIG. 1, processing unit 102 includes processor 120(1), processor 120(2), and so on, through the Nth processor 120(N). Processors might be, for example, implemented as general-purpose processors, such as PowerPC or ARM processors, or the processors might be, for example, implemented as accelerators for specialized functions such as digital signal processing or security protocol processing. Processing unit 102 also includes arbiter 122(1), arbiter 122(2), and so on, through the Nth arbiter 122(N));
first buffer circuits (it is taught as buffered crossbar switches 103) coupled to external ports of the integrated circuit (col.3, lines 30-31; buffered crossbar switch 103 has N input ports and M output ports);
second buffer circuits (it is taught as buffered crossbar switch 104), wherein each of the second buffer circuits is coupled to one of the logic circuits (Fig.1); and
a crossbar circuit (applicant’s crossbar circuit is described section 0020-0021 and Fig.1; Wu teaches data provided from processor 120(1) of processing unit 102 might be provided to input port 132(1) of buffered crossbar switch 103. Arbiter 122(1) controls what data processor 120(1) provides to input port 132(1) of buffered crossbar switch 103. As indicated by dashed arrow 134, buffered crossbar switch 103 might be configured to provide this data to output port 138(2) of buffered crossbar switch 103 in Fig.1) coupled between the first and the second buffer circuits (see Fig.1 and Fig.2), wherein the crossbar circuit is configurable to provide data transfer between the logic circuits and the external ports of the integrated circuit through the first buffer circuits and the second buffer circuits (col.1; lines 44-47; the present invention provides for transfer of data between data modules. Each data module is at least one of a data processing module and a data storage module; claim 1), Each of the first buffer circuits and each of the second buffer circuits is a first-in-first-out buffer circuit (claim 3 and 8).
Wu does not clearly teach each of the first buffer circuits and each of the second buffer circuits is in bidirectional communication with the crossbar circuit.
However, Wang teaches each of the first buffer circuits and each of the second buffer circuits is in bidirectional communication with the crossbar circuit (claim 1 and Fig.6; identifying a first set of masters and a second set of masters from a plurality of masters included in a crossbar interconnect; partitioning the crossbar interconnect into a plurality of partitions comprising at least a, bidirectional first partition corresponding to the first set of masters and a bidirectional second partition corresponding to the second set of masters; allocating a first set of buffer areas within a multi-channel memory, the first set of buffer areas corresponding to the first set of masters, wherein the first set of masters has access to the first set of buffer areas within the multi-channel memory via the bidirectional first partition; and allocating a second set of buffer areas within the multi-channel memory, the second set of buffer areas corresponding to the second set of masters, wherein the second set of masters has access to the second set of buffer areas within the multi-channel memory via the bidirectional second partition)
It would have been obvious to the ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings Wang into Wu such as each of the first buffer circuits and each of the second buffer circuits is in bidirectional communication with the crossbar circuit because this is a substantial reduction in routing complexity of a crossbar interconnect. Reducing routing complexity may reduce the load of the interconnect partitions and may reduce power consumption by the crossbar interconnect. Another particular advantage provided by at least one of the disclosed embodiments is a reduction in arbitration delay and reduced congestion at a First In First Out (FIFO) queue of masters and slaves, thereby improving bandwidth (col.2, lines 13-33 of Wang).
For claim 9; Wu further teaches a first integrated circuit comprising a storage circuit (it is taught as memory unit 105)
For claim 16, Wu further teaches transferring first data from external ports of the processing integrated circuit to logic circuits through first buffer circuits; transferring second data from the logic circuits to the external ports through the second buffer circuits, the crossbar circuit, and the first buffer circuits (it is taught as memory unit 105 might employ memory controllers for coordination of reading and writing operations with memory. Memory might include, for example, at least one RAM buffer. Therefore, as shown in the exemplary embodiment, memory unit 105 might include M memory controllers for coordination of reading information from, and writing information to, one or more RAM buffers).
Regarding claim 2, Wu teaches the logic circuits comprise programmable logic circuits that are arranged in rows of sectors, wherein each of the second buffer circuits is coupled to one of the rows of the sectors, and wherein the crossbar circuit is configurable to provide data transfer between the sectors of the programmable logic circuits in the rows and the external ports (col.2, lines 61-67; processor 120(1) is in electrical communication with arbiter 122(1), processor 120(2) is in electrical communication with arbiter 122(2) and so on, through processor 120(N) that is in electrical communication with arbiter 122(N). Each of arbiters 122(1) through 122(N) has at least one input port and one output port for communication with processors 120(1) through 120(N), respectively).
Regarding claim 3, Wu teaches the crossbar is configurable to couple at least two of the first buffer circuits to at least two of the second buffer circuits (claim 5; it is taught as the N-input node by M-output node switch fabric).
Regarding claims 4 and 19, Wu teaches the crossbar circuit comprises an array of tristate buffer circuits that are controllable by controls signals to couple any of the first buffer circuits to any of the second buffer circuits (Fig.1-2; col.3, lines 34-38; buffered crossbar switch 103 has N input ports, shown as 132(1) through 132(N), and M output ports, shown as 138(1) through 138(M). Buffered crossbar switch 104 has M input ports, shown as 148(1) through 148(M), and N output ports, shown as 142(1) through 142(N). While two buffered crossbar switches are shown in FIG. 1, the present invention is not so limited, and, thus, buffered crossbar switch system 100 might include up to B buffered crossbar switches; col.4, lines 39-40; Buffered crossbar switch 226 includes a FIFO buffer at each crosspoint of the 3.times.3 switch matrix).
Regarding claim 5, Wu teaches the crossbar circuit is configurable to provide data transfer between the logic circuits and the external ports in a non-blocking configuration (col.4, lines 43-47; crosspoint queues temporarily store data before forwarding the data to the respective output port. Crosspoint queues allow the switch fabric to receive data nearly simultaneously at multiple input ports without blocking).
Regarding claim 6, Wu teaches the crossbar circuit couples the first buffer circuits that are selected based on control signals to the second buffer circuits that are selected based on the control signals (col.3, lines 59-66; buffered crossbar switches 103 and 104 might be used to set which ones of N processors of processing unit 102 are in communication with which ones of the M memory controllers of memory unit 105. For example, data provided from processor 120(1) of processing unit 102 might be provided to input port 132(1) of buffered crossbar switch 103. Arbiter 122(1) controls what data processor 120(1) provides to input port 132(1) of buffered crossbar switch 103).
Regarding claim 7, Wu teaches the logic circuits are arranged in sectors that are next to at least three sides of a core logic region of the integrated circuit (claim 5; it is taught as the N-input node by M-output node switch fabric).
Regarding claim 8, Wu teaches the crossbar circuit is configurable to provide bidirectional data transfers between the logic circuits and the external ports through the first buffer circuits and the second buffer circuits (Fig.1 and col.3, lines 1-3; memory unit 105 might employ memory controllers for coordination of reading and writing operations with memory).
Regarding claim 10, Wu teaches the logic circuits are arranged in rows in the second integrated circuit, wherein each of the second buffer circuits is coupled to one of the rows through an interconnect, and wherein the crossbar circuit is configurable to provide signal paths between the rows of the logic circuits and the storage circuit (col.2, lines 61-67; processor 120(1) is in electrical communication with arbiter 122(1), processor 120(2) is in electrical communication with arbiter 122(2) and so on, through processor 120(N) that is in electrical communication with arbiter 122(N). Each of arbiters 122(1) through 122(N) has at least one input port and one output port for communication with processors 120(1) through 120(N), respectively).
Regarding claim 11, Wu teaches the logic circuits are programmable logic circuits that are configurable with configuration data (col.2, lines 52-59; processing unit 102 might be a multi-core processor. For example, processing unit 102 might include N processors, where N is an integer greater than or equal to 1; processing unit 102 includes processor 120(1), processor 120(2), and so on, through the Nth processor 120(N). Processors might be, for example, implemented as general-purpose processors, such as PowerPC or ARM processors, or the processors might be, for example, implemented as accelerators for specialized functions such as digital signal processing or security protocol processing; Processing unit 102 also includes arbiter 122(1), arbiter 122(2), and so on, through the Nth arbiter 122(N), Each of arbiters 122(1) through 122(N) has at least one input port and one output port for communication with processors 120(1) through 120(N), respectively).
Regarding claim 12, Wu teaches the crossbar circuit is configurable to couple at least two of the first buffer circuits to at least two of the second buffer circuits (claim 3 and claim 8; the input buffer at each input node further comprises one of: a first-in, first-out (FIFO) buffer, a virtual output queue (VOQ), or a push-in, first-out buffer (FIFO).), and wherein at least one of the second buffer circuits is a first-in-first-out buffer circuit (Fig.1-2; col.3, lines 34-38; buffered crossbar switch 103 has N input ports, shown as 132(1) through 132(N), and M output ports, shown as 138(1) through 138(M). Buffered crossbar switch 104 has M input ports, shown as 148(1) through 148(M), and N output ports, shown as 142(1) through 142(N). While two buffered crossbar switches are shown in FIG. 1, the present invention is not so limited, and, thus, buffered crossbar switch system 100 might include up to B buffered crossbar switches; col.4, lines 39-40; Buffered crossbar switch 226 includes a FIFO buffer at each crosspoint of the 3.times.3 switch matrix).
Regarding claim 13, Wu teaches the crossbar circuit is configurable to transfer data from the logic circuits to the storage circuit through the second buffer circuits, the crossbar circuit, and the first buffer circuits (col.4, lines 43-47; crosspoint queues temporarily store data before forwarding the data to the respective output port. Crosspoint queues allow the switch fabric to receive data nearly simultaneously at multiple input ports without blocking).
Regarding claim 14, Wu teaches the crossbar circuit is configurable to bidirectionally transfer data between the storage circuit and the logic circuits through the first buffer circuits, the crossbar circuit, and the second buffer circuits (Fig.1 and col.3, lines 1-3; memory unit 105 might employ memory controllers for coordination of reading and writing operations with memory).
Regarding claim 15, Wu teaches the crossbar circuit couples the first buffer circuits to the second buffer circuits that are selected based on control signals (col.3, lines 59-66; buffered crossbar switches 103 and 104 might be used to set which ones of N processors of processing unit 102 are in communication with which ones of the M memory controllers of memory unit 105. For example, data provided from processor 120(1) of processing unit 102 might be provided to input port 132(1) of buffered crossbar switch 103. Arbiter 122(1) controls what data processor 120(1) provides to input port 132(1) of buffered crossbar switch 103).
Regarding claim 17, Wu teaches providing first signal paths from the first buffer circuits through the crossbar circuit to the second buffer circuits for transferring the first data (col.2, lines 61-67; processor 120(1) is in electrical communication with arbiter 122(1), processor 120(2) is in electrical communication with arbiter 122(2) and so on, through processor 120(N) that is in electrical communication with arbiter 122(N). Each of arbiters 122(1) through 122(N) has at least one input port and one output port for communication with processors 120(1) through 120(N), respectively; Fig.1 and col.3, lines 1-3; memory unit 105 might employ memory controllers for coordination of reading and writing operations with memory).
Regarding claim 18, Wu teaches providing second signal paths from the second buffer circuits through the crossbar circuit to the first buffer circuits for transferring the second data (Fig.1 and col.3, lines 1-3; memory unit 105 might employ memory controllers for coordination of reading and writing operations with memory).
Regarding claim 20, Wu teaches transferring the first data from the external ports of the processing integrated circuit to the logic circuits comprises transferring the first data to the logic circuits adjacent to first, second, and third sides of a region of logic circuits in the processing integrated circuit (claim 5; it is taught as the N-input node by M-output node switch fabric).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
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