Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Amendment filed on 11/10/2025.
Claims 1, 3-7, 9-13, and 15-18 are pending.
Response to Applicant’s Remarks
3. Applicant’s arguments with respect to claim(s) have been considered but are moot in view of new ground(s) of rejection(s) as follow:
Claim(s) 1, 3, 4, 7, 9, 10, 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over McIlrath (U.S. Pub. No. 2013/0024827 A1) in view of Woodard et al. (U.S. Pub. No. 2021/0034805 A1).
Claim(s) 5, 6, 11, 12, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over McIlrath (U.S. Pub. No. 2013/0024827 A1) in view of Woodard et al. (U.S. Pub. No. 2021/0034805 A1) and further in view of Boucher et al. (U.S. Pub. No. 2005/0278667 A1).
In the current rejection(s) of the claims, prior art Woodard teach generating of
strip/ribbon by identifying power rails within image, and extract standard cells within the
ribbon in order to perform comparison to a library (See Para [0015] & [0076]-[0079]).
The combination of Woodard into the teaching of McIlrath would improves cell boundary
detection between cells (See Woodard, Para [0011]). Therefore, the combination of
McIlrath and Woodard teach the limitations of the amended claims as cited below. The
rejection(s) of the claims are as cited below, this office action is Final.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1, 3, 4, 7, 9, 10, 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over McIlrath (U.S. Pub. No. 2013/0024827 A1) in view of Woodard et al. (U.S. Pub. No. 2021/0034805 A1).
As per claim 1, McIlrath discloses:
A circuit design validation system, comprising:
polygon extraction circuitry to determine, based on layer images of a fabricated integrated circuit (IC), a plurality of polygons associated with a layer of the fabricated IC (See Para [0037]-[0038], i.e. geometries of the fabricated material layers are recovered, See Para [0039]-[0040], i.e. transforming the geometric characteristics and/or shapes into set of numbers);
size and shape determination to define a search area and size of the layer image of the fabricated IC, wherein the size and shape of the search area are based on a given said cell template associated with original circuit design data (See Para [0042], i.e. identifies … likely cell boundaries…nearby geometric that co-appear, See Para [0043], i.e. determines a boundary of the cell);
cell pattern matching circuitry to search the polygons defined within a layer image of the fabricated IC to determine a match between a cell template of a standard cell library and the plurality of polygons defined within the layer image of the fabricated IC (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
McIlrath does not teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC: and cell pattern matching circuitry to search the polygons defined within the ribbon to determine a match between a cell template of a standard cell library and the plurality of polygons defined within the ribbon.
However, Woodard teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC (See Para [0076]-[0079], i.e. V.sub.cc supply lines are detected as described herein and to extract contact layer image strips from the binarized contact layer image. FIG. 16 illustrates a plurality of binarized contact layer SEM image strips 1600. Each extracted contact layer image strip includes a plurality of contact rows and a plurality of contact columns. The strip size can also be used in particular embodiments for standardization of extracted features… each contact layer image strip as described herein to extract standard cells) and cell pattern matching circuitry to search the polygons defined within the ribbon to determine a match between a cell template of a standard cell library and the plurality of polygons defined within the ribbon (See Para [0015], i.e. the extracted standard cells may be compared with one or more standard cells stored in the standard cell candidate library and segmented into a combination of the standard cells stored in the standard cell candidate library).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Woodard
into the teaching of McIlrath because it would improve cell boundary detection between
cells (See Para [0011]).
As per claim 3, McIlrath and Woodard discloses all of the features of claim 1 as discloses above wherein McIlrath also discloses wherein the cell template includes a plurality of polygons that define a particular cell type (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
As per claim 4, McIlrath and Woodard discloses all of the features of claim 1 as discloses above wherein McIlrath also discloses netlist generation circuitry to generate an as-fabricated netlist based on matching cells between the standard cell library and the layer images (See Para [0013], i.e. a netlist…can be extracted, See Para [0036], i.e. netlist for the integrated circuit can be extracted, See Para [0046]-[0048], See Para [0051]).
As per claim 7, McIlrath discloses:
A circuit design validation method, comprising:
extracting polygons associated with one or more layers of a fabricated integrated circuit (IC), based on layer images of the fabricated IC (See Para [0037]-[0038], i.e. geometries of the fabricated material layers are recovered, See Para [0039]-[0040], i.e. transforming the geometric characteristics and/or shapes into set of numbers);
defining a tile search area and size of the layer image of the fabricated IC, wherein a tile size and shape are based on a given cell type associated with original circuit design data (See Para [0042], i.e. identifies … likely cell boundaries…nearby geometric that co-appear, See Para [0043], i.e. determines a boundary of the cell);
searching the layer images of the fabricated IC to determine a match between polygons associated with the fabricated IC and a cell template information of a standard cell library (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
McIlrath does not teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC: and searching the polygons defined within the ribbon to determine a match between the polygons defined within the ribbon and a cell template of a standard cell library.
However, Woodard teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC (See Para [0076]-[0079], i.e. V.sub.cc supply lines are detected as described herein and to extract contact layer image strips from the binarized contact layer image. FIG. 16 illustrates a plurality of binarized contact layer SEM image strips 1600. Each extracted contact layer image strip includes a plurality of contact rows and a plurality of contact columns. The strip size can also be used in particular embodiments for standardization of extracted features… each contact layer image strip as described herein to extract standard cells) and searching the polygons defined within the ribbon to determine a match between the polygons defined within the ribbon and a cell template of a standard cell library (See Para [0015], i.e. the extracted standard cells may be compared with one or more standard cells stored in the standard cell candidate library and segmented into a combination of the standard cells stored in the standard cell candidate library).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Woodard
into the teaching of McIlrath because it would improve cell boundary detection between
cells (See Para [0011]).
As per claim 9, McIlrath and Woodard discloses all of the features of claim 7 as discloses above wherein McIlrath also discloses wherein the cell template includes a plurality of polygons that define a particular cell type (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
As per claim 10, McIlrath and Woodard disclose all of the features of claim 7 as discloses above wherein McIlrath also discloses generating an as-fabricated netlist based on matching cells between the standard cell library and the layer images (See Para [0013], i.e. a netlist…can be extracted, See Para [0036], i.e. netlist for the integrated circuit can be extracted, See Para [0046]-[0048], See Para [0051]).
As per claim 13, McIlrath discloses:
A non-transitory storage device that includes machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations (See Para [0014], i.e. computer), comprising:
extract polygons associated with one or more layers of a fabricated integrated circuit (IC), based on layer images of the fabricated IC (See Para [0037]-[0038], i.e. geometries of the fabricated material layers are recovered, See Para [0039]-[0040], i.e. transforming the geometric characteristics and/or shapes into set of numbers);
define a tile search area and size of the layer image of the fabricated IC, wherein a tile size and shape are based on a given cell type associated with original circuit design data (See Para [0042], i.e. identifies … likely cell boundaries…nearby geometric that co-appear, See Para [0043], i.e. determines a boundary of the cell).
search the layer images of the fabricated IC to determine a match between polygons associated with the fabricated IC and a cell template information of a standard cell library (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
McIlrath does not teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC: and search the polygons defined within the ribbon to determine a match between the polygons defined within the ribbon and a cell template of a standard cell library.
However, Woodard teach the limitations: wherein the size and shape of the search area is defined as a ribbon between a first voltage rail and a second voltage rail identified in the layer image of the fabricated IC (See Para [0076]-[0079], i.e. V.sub.cc supply lines are detected as described herein and to extract contact layer image strips from the binarized contact layer image. FIG. 16 illustrates a plurality of binarized contact layer SEM image strips 1600. Each extracted contact layer image strip includes a plurality of contact rows and a plurality of contact columns. The strip size can also be used in particular embodiments for standardization of extracted features… each contact layer image strip as described herein to extract standard cells) and search the polygons defined within the ribbon to determine a match between the polygons defined within the ribbon and a cell template of a standard cell library (See Para [0015], i.e. the extracted standard cells may be compared with one or more standard cells stored in the standard cell candidate library and segmented into a combination of the standard cells stored in the standard cell candidate library).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Woodard
into the teaching of McIlrath because it would improve cell boundary detection between
cells (See Para [0011]).
As per claim 15, McIlrath and Woodard discloses all of the features of claim 13 as discloses above wherein McIlrath also discloses wherein the cell template includes a plurality of polygons that define a particular cell type (See Para [0042], i.e. potential cell to be recognized, See Para [0043], i.e. complete the standard cell from the set of co-occurring geometric characteristics, See Para [0044]-[0048], identifying the shapes and polygons within an integrated circuit layout that originated from standard cells, See Para [0049]-[0051], i.e. each standard cell that is a possible match).
As per claim 16, McIlrath and Woodard discloses all of the features of claim 13 as discloses above wherein McIlrath also discloses wherein the machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations, comprising: generate an as-fabricated netlist based on matching cells between the standard cell library and the layer images (See Para [0013], i.e. a netlist…can be extracted, See Para [0036], i.e. netlist for the integrated circuit can be extracted, See Para [0046]-[0048], See Para [0051]).
6. Claim(s) 5, 6, 11, 12, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over McIlrath (U.S. Pub. No. 2013/0024827 A1) in view of Woodard et al. (U.S. Pub. No. 2021/0034805 A1) and further in view of Boucher et al. (U.S. Pub. No. 2005/0278667 A1).
As per claim 5, McIlrath and Woodard disclose all of the features of claim 4 as discloses above.
McIlrath and Woodard do not teach the limitations: comparison circuitry to compare an original design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC.
However, Boucher teach the limitations: comparison circuitry to compare an original design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC (See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], See Para [0034], See Para [0053]-[0055]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Boucher into
the teaching of McIlrath and Woodard because it would allow for reverse engineering a
circuit into a netlist without the need for specialized skill (See Para [0004]).
As per claim 6, McIlrath and Woodard and Boucher discloses all of the features of claim 5 as discloses above wherein Boucher also discloses wherein the one or more validity metrics include erroneous placement of one or more cells, erroneous omission of cell structure, and/or erroneous port placement of one or more cells (See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], i.e. arranged based on port information, See Para [0034]-[0035], i.e. port and power information, See Para [0053]-[0055], i.e. any difference between the two circuits would potentially indicate an error in manufacturing).
As per claim 11, McIlrath and Woodard disclose all of the features of claim 10 as discloses above.
McIlrath and Woodard do not teach the limitations: comparing an original circuit design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC.
However, Boucher teach the limitations: comparing an original circuit design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC. (See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], See Para [0034], See Para [0053]-[0055]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Boucher into
the teaching of McIlrath and Woodard because it would allow for reverse engineering a
circuit into a netlist without the need for specialized skill (See Para [0004]).
As per claim12, McIlrath and Woodard and Boucher discloses all of the features of claim 11 as discloses above wherein Boucher also discloses wherein the one or more validity metrics include erroneous placement of one or more cells, erroneous omission of cell structure, and/or erroneous port placement of one or more cells. (See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], i.e. arranged based on port information, See Para [0034]-[0035], i.e. port and power information, See Para [0053]-[0055], i.e. any difference between the two circuits would potentially indicate an error in manufacturing).
As per claim 17, McIlrath and Woodard disclose all of the features of claim 16 as discloses above.
McIlrath and Woodard do not teach the limitations: compare an original circuit design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC.
However, Boucher teach the limitations: compare an original circuit design netlist with the as-fabricated netlist to determine one or more validity metrics of the fabricated IC. (See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], See Para [0034], See Para [0053]-[0055]).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Boucher into
the teaching of McIlrath and Woodard because it would allow for reverse engineering a
circuit into a netlist without the need for specialized skill (See Para [0004]).
As per claim 18, McIlrath and Woodard and Boucher discloses all of the features of claim 17 as discloses above wherein Boucher also discloses wherein the one or more validity metrics include erroneous placement of one or more cells, erroneous omission of cell structure, and/or erroneous port placement of one or more cells.(See Para [0005], i.e. logic netlist can be compared with a reference netlist to diagnose the integrated circuit, See Para [0021], See Para [0026], i.e. arranged based on port information, See Para [0034]-[0035], i.e. port and power information, See Para [0053]-[0055], i.e. any difference between the two circuits would potentially indicate an error in manufacturing).
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851