DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is responsive to amendment filed on January 02, 2026. Claims 1, 14 and 21 have been amended . No new claims have been added or canceled. Claims 1-25 presented for the examination and remain pending in the application.
The previous non-statutory double patenting rejection has been withdrawn due to Applicant’s claims amendment/Remarks.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. U.S. Pub. No. 2020/0117624 A1, (hereinafter Kumar) in view of Banginwar et al. U.S. Pub. No. 2020/0364158 A1, (hereinafter Banginwar).
Regarding claim 1.
Kumar teaches an apparatus comprising: a processor to execute at least one Trusted Environment (TE) with a TE address space and a non-TE address space, wherein the TE address space is to map memory mapped input/output (MMIO) pages that support TE and non-TE data and the non-TE address space is to map MMIO pages that support only non-TE data (Kumar teaches in Figs. 1 and 2 and further in Para. [0039]-[0040] the processing device includes processors and performs if the I/O device 160 uses command payload to store the interrupt message, the interrupt handle is “untrusted” (i.e., non-TE) since the I/O device 160 receives the interrupt handle directly from the VM. In one embodiment, the interrupt handle is allocated by VMM 130 and given to the VMs 140,141 using a VMM specific method to be used in the command payload…, the handle space is allocated and managed by each Scalable IOV guest driver associated with the VMs 140,141, making the untrusted handle guest driver specific and further Kumar teaches in Para. [0040] the processing device 100 implements an interrupt remapping to ensure those interrupt messages 190 for the I/O devices 160 are translated into trusted interrupts before they are delivered to the VMs 140,141…,the interrupt manager 180 may be implemented as part of the IOMMU 150…), and
selection circuitry to select between the TE address space and the non-TE address space based at least in part on a value of a TE tag for a transaction (Kumar teaches in Para. [0022] the I/O device tags all of an AI's upstream direct memory access (DMA) requests with the assigned ASID. For example, PCI-Express (PCIe) devices can use PCIe ASID TLP (Transaction Layer Packet) prefix to tag (i.e., tag transaction) their upstream DMA requests with the assigned ASID), wherein the TE address space is to map one or more TE Input/Output (IO) devices and the non-TE address space is to map one or more legacy IO devices (Kumar teaches about the selection of interrupt manager 180 may remap the “untrusted” (i.e., non-TE) handle 234 into a “trusted” (i.e., TE) interrupt 285 setup by the VMM. For example, the handle 234 may be “untrusted” because guest driver associated with the VM 140 manages allocation of handle 234…, the interrupt manager 180 may use the ASID 232 to index the ASID table 250 to select or otherwise identify a specific entry 252 as narrated in Para. [0044]-[0045] and further, Kumar teaches in Par. [0113] select an entry in an ASID (i.e., an address space identifier) table based on the ASID associated with the interrupt message; and identifying, in the entry, an address pointer pointing to an interrupt remapping table (IRT) comprising a plurality of interrupt remapping table entries (IRTE), each IRTE is extended to include an ASID field and further, Kumar teaches in Para. [0110] that the ASID (i.e., an address space identifier) receive an interrupt message directed to an application container from an assignable interface (AI) of an input/output (I/O) device…). While Kumar teaches about the trusted and untrusted (i.e., non-trusted) TE address as indicated above, Kumar does not explicitly teach wherein the TE address space is to be managed by a TE security manager and the non-TE address space is to be managed by a virtual machine monitor (VMM).
However, Banginwar teaches wherein the TE address space is to be managed by a TE security manager and the non-TE address space is to be managed by a virtual machine monitor (VMM) (Banginwar teaches in Para. Fig. 1 and Para. [0038] the bottom of FIG. 1 shows a trusted security engine 180 at the level of hardware and firmware. Security engine 180 may be used to assist in secure boot using cryptographic and hash operations, for instance. Security engine 180 may be used to ensure that the system boots to a trusted computing base (TCB). Also, see Para. [0040] and further, Banginwar teaches in Para. [0200] a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application). Therefore, Kumar and Banginwar are analogues arts and they are in the same field of endeavor as they both are directed to providing encryption key ID assigned by the TEE to one or more I/O devices that it trusts, and the I/O devices use the assigned encryption key ID to encrypt a packet that is to be transmitted to the TEE.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using security engine to manage trusted components and virtual machine to manage the untrusted application ([0038] and [0200]) as taught, by Banginwar into the teachings of Kumar invention. Since the method involves enabling an untrusted application and a trusted application to run on top of a single operating system (OS) while preventing the untrusted application from accessing memory. The OS that comprises an untrusted interrupt descriptor table (IDT) with gates that associate interrupt vectors with untrusted interrupt service routines (ISRs). A virtual IDT (VIDT) is created with gates that associate interrupt vectors with trusted ISRs and thus, the virtual machine manager (VMM) manages extended page table (EPT) to protect the memory that is allocated from the memory space that is managed by VMM, thus providing for isolation of guest-accessible physical memory. The run time performance of the TA is improved, since that mitigates constant virtual machine (VM)-exits and VM-entries caused due to page faults. The need for special hardware support and the need for the VMM to provide full or complete virtualization are obviated, which enables the data processing system to run both a secure OS and an unsecure OS. The TA-enter ISR copies all of the general purpose register (GPR) state, including the return instruction pointer (RIP) that was automatically saved by the hardware on int, along with the hardware saved register state, to the trusted ring-0 stack to enhance the security. The TA exit code clears the GPRs, thus protecting the information from leak through registers.
Regarding claim 2.
Kumar teaches wherein the at least one TE comprises a Trusted Execution Environment (TEE), the TE address space comprises a TEE address space, and the non-TE address space comprises a non-TEE address space (Kumar teaches in Para. [0039]-[0040] teaches about the trusted and untrusted environments).
Regarding claims 14 and 21.
Claims 14 and 21 incorporate substantively all the limitation of claim 1 in a non-transitory computer readable media and a method form and are rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Claims 5, 6, 9, 10, 17, 18, 24 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Banginwar further in view of Zmudzinski et al. U.S. Pub. No. 2019/0227827 A1, (hereinafter Zmudzinski).
Regarding claim 5. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach wherein the TE tag is to be generated based at least in part on a value of an attribute for an address of the transaction.
However, Zmudzinski teaches wherein the TE tag is to be generated based at least in part on a value of an attribute for an address of the transaction (Zmudzinski teaches in Para. [0050] and [0058] about the TEE ID and Key ID (i.e., TE tag) and attribute transaction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using TEE ID and Key ID (i.e., TE tag) and attribute transaction ([0050] and [0058]) as taught, by Zmudzinski into the teachings of Kumar in view of Banginwar invention. One would have been motivated to do so in order to the device utilizes a trusted agent to operate under overall control and management of a virtual machine monitor (VMM) while providing assurances to the TEE, such that the device can be configured correctly and operate as configured during trusted I/O in an efficient manner.
Regarding claim 6.
Zmudzinski teaches wherein the attribute is one of: an Address Space Type (AST) attribute of a Host Physical Address (HPA), and an AST attribute of a KEYID associated with an HPA (Zmudzinski teaches in Para. [0050] and [0058] about the TEE ID and key ID associated with the HPA and KEYID. Note that here, the claim lists features in the alternative. While the claim lists a number of optional limitations only one limitation from the list is required and needs to be met by the prior art. However, the prior art of record Zmudzinski addressed at least two of the limitations “HPA and KEYID”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using TEE ID and Key ID (i.e., TE tag) and attribute transaction ([0050] and [0058]) as taught, by Zmudzinski into the teachings of Kumar in view of Banginwar invention. One would have been motivated to do so in order to establish bindings between the TEE and one of I/O devices, such that the TEE trusts and a memory ownership table (MOT) programmed by the TEE when a memory page is allocated to the TEE, where each entry of the DMAT includes a device ID that uniquely identifies an I/O device trusted by the TEE, a TEE ID that uniquely identifies the TEE, and a key ID used to encrypt TEEs physical memory.
Regarding claim 9.
Kumar teaches wherein the value of the TE tag is to be generated by one of: a Memory Management Unit (MMU), an Input-Output MMU (IOMMU), an IO agent, a Peripheral Component Interconnect express (PCIe) circuit, and a Compute Express Link (CXL) root port (Kumar teaches in Para. [0022] the I/O device tags all of an AI's upstream direct memory access (DMA) requests with the assigned ASID. For example, PCI-Express (PCIe) devices can use PCIe ASID TLP (Transaction Layer Packet) prefix to tag (i.e., tag transaction) their upstream DMA requests with the assigned ASID and further, Kumar teaches in Para. [0046] the AI 365 may be mapped to one or more pages (e.g., 4 KB) of memory mapped I/O (MMIO) registers (note that here, the claim lists features in the alternative. While the claim lists a number of optional limitations only one limitation from the list is required and needs to be met by the prior art and thus, the prior art of record Kumar at lease addressed the tag generating limitations of “PCIe and memory mapped I/O (MMIO)”)).
Regarding claim 10.
Kumar teaches wherein the transaction is one of: a Memory Mapped Input/Output (MMIO) transaction, a Direct Memory Access (DMA) transaction, and a Peer-to-Peer (P2P) transaction (Kumar teaches in Para. [0044] the handle is unique in the VM 140. The interrupt manager 180 may remap the “untrusted” handle 234 into a “trusted” interrupt 285 setup by the VMM. For example, the handle 234 may be “untrusted” because guest driver associated with the VM 140 manages allocation of handle 234. In some embodiments, IOMMU 150 may implement a table structure, such as ASID table 250, in memory 210 of the system. Note that here, the claim lists features in the alternative. While the claim lists a number of optional limitations only one limitation from the list is required and needs to be met by the prior art Kumar addressed at least “MMIO”).
Regarding claims 17 and 24.
Claims 17 and 24 incorporate substantively all the limitation of claim 5 in a non-transitory computer readable media and a method form and are rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Regarding claims 18 and 25.
Claims 18 and 25 incorporate substantively all the limitation of claim 6 in a non-transitory computer readable media and a method form and are rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Claims 3, 4, 15, 16, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Banginwar further in view of Ouziel et al. U.S. Pub. No. 2020/0201786 A1, (hereinafter Ouziel).
Regarding claim 3. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach wherein the TE tag is to be generated based at least in part on a value of a field in an address of the transaction.
However, Ouziel teaches wherein the TE tag is to be generated based at least in part on a value of a field in an address of the transaction (Ouziel teaches in Para. [0044]-[0046] the key IDs appended to the physical memory addresses, a memory transaction requested by software, and multi-key, total memory encryption (MK-TME) …, and upon completion of the handshaking and determining the new desired partition of key ID space and further teaches in Para. [0058] a value greater than the enumerated number of maximum supported Key ID bits may result in general protection fault (# GP). Writing a non-zero value to this field may also result in a general protection fault if bit 1 of EAX (TME Enable) is not also set to ‘1,’ as TME is to be enabled to use MK-TME.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using the key ID, a memory transaction and add value to a field ([0044]-[0046]) as taught, by Ouziel into the teachings of Kumar in view of Banginwar invention. One would have been motivated to do so in order to the demands of secure execution of various applications on the processing device executes multiple trust domain to prevent access of applications running inside trust domain to the secure data in the memory pages assigned to trust domain. The circuits or semiconductor devices have higher pipeline throughput and improved performance.
Regarding claim 4.
Zmudzinski further teaches wherein the field is one of: an Address Space Type (AST) field in a Guest Physical Address (GPA) and a Key Identifier (KEYID) field in a Host Physical Address (HPA) (Zmudzinski teaches in Para. [0011]-[0012] it should be appreciated that the same encryption key ID is assigned by the TEE to one or more I/O devices 136 that it trusts, and the I/O devices 136 use the assigned encryption key ID to encrypt a packet that is to be transmitted to the TEE and …, a guest physical address (GPA) to host physical address (HPA) mapping and host physical address (HPA) mapping. Note that here, the claim lists features in the alternative. While the claim lists a number of optional limitations only one limitation from the list is required and needs to be met by the prior art. However, the prior art of record Zmudzinski addressed all of the limitations except “Address Space Type (AST)”).
Regarding claims 15 and 22.
Claims 15 and 22 incorporate substantively all the limitation of claim 3 in a non-transitory computer readable media and a method form and are rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Regarding claims 16 and 23.
Claims 16 and 23 incorporate substantively all the limitation of claim 4 in a non-transitory computer readable media and a method form and are rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Banginwar further in view of Asbe et al. U.S. Pub. No. 2018/0136967 A1, (hereinafter Asbe).
Regarding claim 7. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach wherein a TEE Virtual Machine (TVM) is to generate the transaction.
However, Asbe teaches wherein a TEE Virtual Machine (TVM) is to generate the transaction (Asbe teaches in Para. [0028] memory management unit may convert a virtual address in a secure transaction generated by the trusted execution environment 106 to a physical address and may proceed to transmit the secure memory transaction with the physical address and further teaches in Para. [0062] the rich OS running on the virtual machine 504 may program the stream IDs associated with the security domain of the rich OS (e.g., the stream IDs that may be included in transactions generated at the first master device 518) to a first stage context bank).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using a virtual machine in a trusted execution environment system to generate a transaction ([0028]) as taught, by Asbe into the teachings of Kumar in view of Banginwar invention. One would have been motivated to do so in order to the method enables allowing a non-secure rich operating system (OS) to manage the identifier associated with the security domains, thus removing the need for a hypervisor device to support different virtual machines. The method enables allowing for secure system MMU (SMMU) virtualization without requiring addition of hardware elements. The method enables preventing master devices acting on behalf of the first security domain to gain access to the resources of the second security domain.
Regarding claim 19.
Claim 19 incorporates substantively all the limitation of claim 7 in a non-transitory computer readable media form and is rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Banginwar further in view of Shanbhogue et al. U.S. Pub. No. 2020/0159969 A1, (hereinafter Shanbhogue).
Regarding claim 8. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach wherein a TEE Device Interface (TDI) is to generate the transaction.
However, Shanbhogue teaches wherein a TEE Device Interface (TDI) is to generate the transaction (Shanbhogue teaches Para. [0120] the virtual machine notifies the trusted Device interface can only accept or generate trusted transactions when in the “Run” state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to modify the teachings of using the trusted Device interface in a trusted execution environment system ([0120]) as taught, by Shanbhogue into the teachings of Kumar in view of Banginwar invention. One would have been motivated to do so in order for managing device interfaces in an efficient manner.
Regarding claim 20.
Claim 20 incorporates substantively all the limitation of claim 8 in a non-transitory computer readable media form and is rejected under the same rationale. Furthermore, regarding the claim limitation of a non-transitory computer readable media, the prior art of record Kumar teaches in Para. [0107].
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kumar in view of Banginwar further in view of Agarwal et al. U.S. Pub. No. 2017/0269959 A1, (hereinafter Agarwal).
Regarding claim 11. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach tracking circuitry to track the value of the TE tag for non-posted transactions.
However, Agarwal teaches tracking circuitry to track the value of the TE tag for non-posted transactions (Agrawal teaches in Para. [0024]-[0025] tracking structure of the non-posted transaction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of a system of tracking the non-posted transaction ([0024]-[0025]) as taught, by Agrawal into Kumar in view of Banginwar invention. One would have been motivated to do so in order to the apparatus comprises an encoder that receives a non-posted transaction from a requester and encodes the information, where transmitter sends the non-posted transaction that contains encoded transaction identifier, and thus enables to precisely determine the source of the transaction.
Regarding claim 12.
Kumar in view of Banginwar does not explicitly teach wherein the value of the TE tag is to be modified in response to completion of the non-posted transaction.
However, Agrawal teaches wherein the value of the TE tag is to be modified in response to completion of the non-posted transaction (Agrawal teaches in Para. [0034] since these functions are guaranteed to be non-overlapping. Thus, 8 bits of device (5 bits) and function (3 bits) can be used in a custom manner (i.e., modified) to encode non-posted transactions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of a system of managing the over-lapping of non-posted transaction based on custom manner ([0034]) as taught, by Agrawal into Kumar in view of Banginwar invention. One would have been motivated to do so in order to control the debug and error handling software may more precisely determine the source of the transaction, which can be useful for error isolation and recovery actions (Agrawal. Para. [0037]).
Regarding claim 13. Kumar in view of Banginwar teaches the apparatus of claim 1.
Kumar in view of Banginwar does not explicitly teach generating circuitry to generate a first bit to represent a TE tag for a requester and a second bit to represent a TE tag for a completer.
However, Agrawal teaches generating circuitry to generate a first bit to represent a TE tag for a requester and a second bit to represent a TE tag for a completer (Agrawal teaches in Para. [0031] the 16-bit (i.e., the first bit) requester ID is uniquely assigned to each PCIe function. In turn, the tag field is an 8-bit (i.e., the second bit) field generated by each requester and is unique for all outstanding requests that require a completion for that requester. Also, see Para. [0032] and [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of a system of generating different bits which represent requestor that requires a completion uniquely ([0031]) as taught, by Agrawal into Kumar in view of Banginwar invention. One would have been motivated to do so in order to perform fire-and-forget, a rule codified in a PCIe specification is leveraged, in that receivers/completers return the transaction ID unmodified with completions for non-posted requests (Agrawal. Para. [0031]).
Response to arguments
Completeness and clarity of Examiner’s Action. (Remarks. Page. 6).
Applicant indicated that the examiner should, as a part of the first Office action on the merits, identify any claims which he or she judges, as presently recited, to be allowable and/or should suggest any way in which he or she considers that rejected claims may be amended to make them allowable." As this was not done in the first Office action on the merits, the Applicant respectfully requests suggestions regarding allowability including claim amendment suggestions in any subsequent action. Providing prescribed guidance is in the interest of compact prosecution. (See. MPEP 707.07(d).
In response to the above Applicant’s concern, the Examiner would like to express that the ground of rejection fully and clearly stated in the previous Office Action and the Examiner designated the statutory basis for the previous ground of rejection by relying on the references to reject the recited claims language under section of 35 U.S.C. 103 in the opening sentence of each ground of rejection. Furthermore, before issuing this final Office Action, the Examiner tried to reach out the Applicant’s Attorney “David Nicholson” via telephone number (408) 675-0441 multiple times and left a voice message at least, to discuss, to suggest if any allowable subject matter can be found from originally filed Specification by proposed Examiner amendment. However, the Applicant’s Attorney has not responded to the Examiner’s voice message.
In regard to the Applicant’s arguments with respect to the 103 rejections, the arguments do not apply to the combination of the references being used in the current rejection for amended claims 1, 14 and 21 and their respective dependent claims 2-13, 15-20 and 22-25. Examiner has introduced the new prior arts based on the disclosure of Kumar et al. (U.S. Pub. No. 2020/0117624 A1) in view of Banginwar et al. (U.S. Pub. No. 2020/0364158 A1) to teach the change in scope of the amended claims 1, 14 and 21 and the prior arts of records are still believed to teach all the remaining limitations of the remaining dependent claims as set forth. Therefore, the arguments are moot in view of the new ground of rejection under 103 above.
Double Patenting (Remarks. Page. 6).
With respect to the previous non-statutory double patenting rejection, the rejection has been withdrawn due to Applicant’s claims amendment/Remarks as indicated above under section 3).
Request for the interview. (Remarks. Page. 8).
The Applicant also requested that if the Examiner believes that this application is not in condition for allowance in view of this response, the Applicant requests an examiner interview.
As the Examiner indicated above, the Examiner tried to reach out the Applicant’s Attorney several times but the calls were unsuccessful due to the Applicant’s side failed to respond at least one of the Examiner’s calls.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BERHANU SHITAYEWOLDETSADIK whose telephone number is (571)270-7142. The examiner can normally be reached M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emmanuel Moise can be reached at 5712723865. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BERHANU SHITAYEWOLDETSADIK/Examiner, Art Unit 2455