Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. EXAMINER’S NOTE: The claims have been reviewed and considered under the new guidance pursuant to the 2019 Revised Patent Subject Matter Eligibility Guidance (PEG 2019) issued January 7, 2019.
3. This communication is in response to Applicant’s RCE Amendment filed on 17 September 2025. Claims 2, 4, and 16 were previously canceled. Claims 1, 5-6, 8, and 17-20 have been amended. Claims 1, 3, 5-15, and 17-23 remain pending.
Continued Examination Under 37 CFR 1.114
4. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 17 September 2025 has been entered.
Response to Arguments
5. Applicant’s arguments, see pages 8-12, filed 18 August 2025, with respect to the rejection of claims 1 and 3 under Herbeck et al. (US Patent No. 9,959,124) in view of Nemirovsky et al. (US Patent No. 7,571,270) have been fully considered, but are moot in view of the new grounds of rejection.
A new grounds of rejection is hereby presented in view of Dover (Pub No. 2021/0049111) for teaching newly claim limitations – “storing a system state verification parameter in a system memory and combine the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter and identify a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system”.
6. In light of the Applicant’s arguments, see pages 9-12, the Applicant traverses that Herbeck et al. in view of Dover et al. does not teach, disclose, or suggest “storing system state data associated with the initializing of the computing system in a hardware register having at least one lockable until reset bit, storing a system state verification parameter in a system memory, combining the system state data and the system data verification parameter to generate a combined system state verification parameter, and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value. The Examiner respectfully disagree and asserts that Herbeck et al. discloses storing system state data during the initialization of the system in volatile portion of the system memory, such as SRAM, item 242 and a hardware lockable register, item 260 is write locked preventing writes to the secure region, item 270 and will remain locked until the next system resets as shown in Col. 8, lines 65-66, Col. 9, lines 15-54, and Col. 11, lines 49-55.
According to the Applicant’s specification, para. 0027-0028, the system state verification data is defined as stored in bits of the system memory location may include predetermined values that correspond to the values of the system state data. The system state data may indicate a malicious attack as invalid system state data which includes one bit being set in the life cycle state data, the initialization phase data and not matching an expected value.
Dover et al. discloses a method and system for memory protection based on system state data. Dover et al. discloses storing the system state verification data as values shown as bits of the system memory that correspond to the values that are predetermined from the hardware register to evaluate the access rules. Dover et al. discloses generating a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access as shown in para. 16, 26-29, 35-38, and Figs. 3 and 4.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claim 23 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “sticky until reset bit” in claim 23 is used by the claim to mean “locked or lockable,” while the accepted meaning is “a bit being locked after being set until the next system reset as disclosed in paragraph 0023 of the Applicant’s specification.” The term is indefinite because the specification does not clearly redefine the term. Therefore, the terminology “first sticky until reset bit” and “second sticky until reset bit” lacks consistency with the accepted meaning.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claims 1, 3, 5-8, and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Herbeck et al. (US Patent No. 9,959,124) in view of Nemirovsky et al. (US Patent No. 7,571,270) and in further view of Dover (Pub No. 2021/0049111).
Referring to the rejection of claim 1, Herbeck et al. discloses a system, comprising: (See Herbeck et al., Fig. 2, always-on component, item 160)
a processor; (See Herbeck et al., Fig. 2, processor, item 240)
and a memory storing an application image comprising instructions, that when executed by the processor cause the processor to: store system state data in the hardware register during an initializing of the system. (See Herbeck et al., Fig. 2 and Col. 8, lines 65-66, i.e., memory, item 242 for storing system state data during an initialization of the system, wherein the memory is SRAM. Herbeck et al. further discloses in Col. 10, lines 1-11, i.e., executing stored image patterns to initialize the computing system wherein responsive to detecting the desired pattern, the processor is configured to wake the memory controller to update the memory and/or wake the SOC)
However, Herbeck et al. fail to explicitly disclose a lockable until reset bit.
Nemirovsky et al. discloses a method and system for monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads.
Nemirovsky et al. discloses a hardware register comprising at least on lockable until reset bit. (See Nemirovsky et al., Fig. 2, 3, and 7, and Col. lines 25-44, i.e., lock and sticky-lock bits packed into hardware registers, items 60 and 62 read by resource-lock monitoring software. Lock-Monitor register, item 60 contains lock bits LOCK_A, LOCK_B, LOCK_C, . . . LOCK_N for processors A, B, C, . . . N. The lock bit LOCK_X for processor X in register, item 60 is set when processor X executes a lock instruction, and reset when the lock is granted and received by processor X. Sticky-lock-Monitor register, item 62 contains sticky-lock bits STICKY_LOCK_A, STICKY_LOCK_B, STICKY_LOCK_C, . . . STICKY_LOCK_N for processors A, B, C, . . . N. The sticky-lock bit STICKY_LOCK_X for processor X in register, item 62 is set when processor X executes a sticky-lock instruction, and reset when the clear-sticky signal is generated by the system's lock monitor. While individual lock and sticky-lock bits are set in registers items 60 and 62 as each processor executes a lock instruction, and lock bits in register, item 60 are individually cleared by the lock grant for a particular processor, individual sticky-lock bits are cleared by the clear-sticky signals from the central lock monitor based on the sampled state of sticky-lock bits)
The combination of Herbeck et al. and Nemirovsky et al. fail to explicitly disclose storing a system state verification parameter in a system memory and combine the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter and identify a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system.
Dover discloses an improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data.
Dover discloses storing a system state verification parameter in a system memory; (See Dover, Fig. 4 and para. 27, 37, i.e., storing the system state verification data as values shown as bits of the system memory (i.e., first memory array) that correspond to the values that are predetermined from the hardware register to evaluate the access rules stored in the system memory)
Dover discloses and combine the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter and identify a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system. (See Dover, Fig. 3-4 and para. 16, 26-29, and 35-38, i.e., the processor generates a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access. If the hardware register bit value does not conform to the access rules based on the expected bit value, the memory access is denied and this will prevent unauthorized memory access from malicious attackers)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date the claimed invention was made to combine Herbeck et al.’s secure system for preventing writes to the secure portion of the memory by locking the secure portion of the memory by writing a predetermined value into a lockable register and Nemirovsky et al.’s method and system for monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads modified with Dover’s improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data.
Motivation for such an implementation would enable sticky-lock bits to remain set until sticky-lock bits are cleared by monitoring software at the end of a monitoring period wherein the monitoring software reads the lock and sticky-lock bits and finds a locked processor when a processor's lock bit is still set, but its sticky-lock bit is cleared. (See Nemirovsky et al., Abstract)
Motivation for such an implementation would enable bit values to be used for prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. (See Dover, para. 16 and 28)
Referring to the rejection of claim 3, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein the system state data comprises life cycle state data. (See Herbeck et al., Col. 10, lines 53-67 and Col. 11, lines 1-2, i.e., the system state data comprises the life cycle state data that is set once during the initialization phase by checking the validity using a simple mask operation)
Referring to the rejection of claim 5, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: the processor is to set the first lockable until reset bit of the hardware register after completion of a first phase of the initializing; (See Dover, Fig. 4 and para. 38, i.e., the first bit of the hardware register is set to 001 which is disclosed as the first initialization phase) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and the processor is configured to set a second bit of the hardware register after completion of a second phase of the initializing. (See Dover, Fig. 4 and para. 38, i.e., the second bit of the hardware register is set to 010 which is disclosed as the second initialization phase)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 6, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: the processor is configured to set the first lockable until reset bit of the hardware register responsive to a life cycle state of the system having a first value; (See Dover, Fig. 4 and para. 38, i.e., the first sticky until reset bit of the hardware register is set to 001 which is disclosed as the life cycle state defined as the chip developer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
the processor is configured to set a second lockable until reset bit of the hardware register responsive to the life cycle state having a second value; (See Dover, Fig. 4 and para. 38, i.e., the second sticky until reset bit of the hardware register is set to 010 which is disclosed as the life cycle state defined as the device manufacturer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and the processor is configured to identify a fault condition responsive to more than one bit being set in the hardware register after completion of the initialization of the system. (See Dover, Fig. 3-4 and para. 16, 26-29, 35-38, i.e., identifying a fault condition responsive to the system state data not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 7, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: the hardware register comprises a life cycle state field and an initialization phase field. (See Dover, Fig. 4 and para. 38, i.e., the first bit of the hardware register is set to 001 which is disclosed as the first initialization phase and a life cycle state defined as the chip manufacturer state)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 8, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein the memory comprises:
a non-volatile portion configured to store the application image; (See Herbeck et al., Fig. 2 and Col. 8, lines 65-66, i.e., memory, item 242 for storing system state data during an initialization of the system, wherein the memory is SRAM. Herbeck et al. further discloses in Col. 10, lines 1-11, i.e., executing stored image patterns to initialize the computing system wherein responsive to detecting the desired pattern, the processor is configured to wake the memory controller to update the memory and/or wake the SOC)
a volatile portion configured to store the system state verification parameter: (See Dover, Fig. 4 and para. 27, 37, i.e., storing the system state verification data as values shown as bits of the system memory (i.e., first memory array) that correspond to the values that are predetermined from the hardware register to evaluate the access rules stored in the system memory)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 17, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses a non-transitory computer-readable medium storing instructions that when executed facilitate performance of operations comprising: (See Herbeck et al., Fig. 8, i.e., a non-transitory computer-readable storage medium (CD-ROM, DVD-ROM), item 800)
initializing a computing system comprising a processor; (See Herbeck et al., Fig. 2, Col. 6, lines 35-43 and Col. 9, lines 15-44, i.e., processor, item 240 and lockable register, item 260 having a “write locked” feature configured to store data bits. Once the data has been stored in the lockable register, a write lock register is set to prevent further updates to the contents of the secure region and tampering of important system setting by untrusted software. The lockable register remains locked until the next system reset. Herbeck et al. further discloses in Col. 10, lines 1-11, i.e., executing stored image patterns to initialize the computing system wherein responsive to detecting the desired pattern, the processor is configured to wake the memory controller to update the memory and/or wake the SOC)
storing system state data associated with the initializing of the computing system in a hardware register; (See Herbeck et al., Fig. 2 and Col. 8, lines 65-66, i.e., memory, item 242 for storing system state data during an initialization of the system, wherein the memory is SRAM. Herbeck et al. further discloses in Col. 9, lines 15-49 and Col. 11, lines 49-55, the lockable register is locked until the next system resets)
However, Herbeck et al. fail to explicitly disclose a first sticky until reset bit and a second sticky until reset bit.
Nemirovsky et al. discloses a method and system for monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads.
Nemirovsky et al. discloses a hardware register comprising at least one lockable until reset bit; (See Nemirovsky et al., Fig. 2, 3, and 7, and Col. lines 25-44, i.e., lock and sticky-lock bits packed into hardware registers, items 60 and 62 read by resource-lock monitoring software. Lock-Monitor register, item 60 contains lock bits LOCK_A, LOCK_B, LOCK_C, . . . LOCK_N for processors A, B, C, . . . N. The lock bit LOCK_X for processor X in register, item 60 is set when processor X executes a lock instruction, and reset when the lock is granted and received by processor X. Sticky-lock-Monitor register, item 62 contains sticky-lock bits STICKY_LOCK_A, STICKY_LOCK_B, STICKY_LOCK_C, . . . STICKY_LOCK_N for processors A, B, C, . . . N. The sticky-lock bit STICKY_LOCK_X for processor X in register, item 62 is set when processor X executes a sticky-lock instruction, and reset when the clear-sticky signal is generated by the system's lock monitor. While individual lock and sticky-lock bits are set in registers items 60 and 62 as each processor executes a lock instruction, and lock bits in register, item 60 are individually cleared by the lock grant for a particular processor, individual sticky-lock bits are cleared by the clear-sticky signals from the central lock monitor based on the sampled state of sticky-lock bits)
The combination of Herbeck et al. and Nemirovsky et al. fail to explicitly disclose storing a system state verification parameter in a system memory and combining the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system.
Dover discloses an improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data.
Dover discloses storing a system state verification parameter in a system memory; (See Dover, Fig. 4 and para. 27, 37, i.e., storing the system state verification data as values shown as bits of the system memory (i.e., first memory array) that correspond to the values that are predetermined from the hardware register to evaluate the access rules stored in the system memory)
Dover discloses and combining the system state data in the hardware register and the system state verification parameter to generate a combined system state verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value after completion of the initialization of the system. (See Dover, Fig. 3-4 and para. 16, 26-29, and 35-38, i.e., the processor generates a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access. If the hardware register bit value does not conform to the access rules based on the expected bit value, the memory access is denied and this will prevent unauthorized memory access from malicious attackers)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 18, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: the processor is to set the first lockable until reset bit of the hardware register after completion of a first phase of the initializing; (See Dover, Fig. 4 and para. 38, i.e., the first bit of the hardware register is set to 001 which is disclosed as the first initialization phase) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and the processor is configured to set a second lockable until reset bit of the hardware register after completion of a second phase of the initializing. (See Dover, Fig. 4 and para. 38, i.e., the second bit of the hardware register is set to 010 which is disclosed as the second initialization phase)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 19, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: setting the first lockable until reset bit of the hardware register responsive to a life cycle state of the system having a first value; (See Dover, Fig. 4 and para. 38, i.e., the first sticky until reset bit of the hardware register is set to 001 which is disclosed as the life cycle state defined as the chip developer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
setting a second lockable until reset bit of the hardware register responsive to the life cycle state having a second value; (See Dover, Fig. 4 and para. 38, i.e., the second sticky until reset bit of the hardware register is set to 010 which is disclosed as the life cycle state defined as the device manufacturer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and identifying a fault condition responsive to more than one bit being set in the hardware register after completion of the initialization of the system. (See Dover, Fig. 3-4 and para. 16, 26-29, 35-38, i.e., identifying a fault condition responsive to the system state data not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 20, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses comprising: storing the system state verification parameter in a volatile portion of a system memory: (See Dover, Fig. 4 and para. 27, 37, i.e., storing the system state verification data as values shown as bits of the system memory (i.e., first memory array) that correspond to the values that are predetermined from the hardware register to evaluate the access rules stored in the system memory)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
Referring to the rejection of claim 21, (Herbeck et al. and Nemirovsky et al. modified by Dover) discloses wherein: the system state verification parameter has a value that depends on a value of the system state data. (See Dover, Fig. 3-4 and para. 16, 26-28, and 35-38, i.e., the processor generates a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access. If the hardware register bit value does not conform to the access rules based on the expected bit value, the memory access is denied and this will prevent unauthorized memory access from malicious attackers)
The rationale for combining Herbeck et al. and Nemirovsky et al. in view of Dover is the same as claim 1.
12. Claims 9-15 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Herbeck et al. (US Patent No. 9,959,124) in view of Dover (Pub No. 2021/0049111).
Referring to the rejection of claim 9, (Herbeck et al. modified by Dover) discloses a method, comprising:
executing an application image to initialize a computing system; (See Herbeck et al., Fig. 2, Col. 6, lines 35-43 and Col. 9, lines 15-54, i.e., lockable register, item 260 having a “write locked” feature configured to store data bits. Once the data has been stored in the lockable register, a write lock register is set to prevent further updates to the contents of the secure region and tampering of important system setting by untrusted software. The lockable register remains locked until the next system reset. Herbeck et al. further discloses in Col. 10, lines 1-11, i.e., executing image patterns to initialize the computing system wherein responsive to detecting the desired pattern, the processor is configured to wake the memory controller to update the memory and/or wake the SOC)
storing system state data associated with the initializing of the computing system in a hardware register having at least one lockable until reset bit; (See Herbeck et al., Fig. 2 and Col. 8, lines 65-66, i.e., memory, item 242 for storing system state data during an initialization of the system, wherein the memory is SRAM. Herbeck et al. further discloses in Col. 9, lines 15-49 and Col. 11, lines 49-55, the lockable register is locked until the next system resets)
Herbeck et al. fail to explicitly disclose identifying a fault condition responsive to the system state data not matching an expected value.
Dover discloses an improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data.
Dover discloses storing a system state verification parameter in a system memory. (See Dover, Fig. 4 and para. 27, 37, i.e., storing the system state verification data as values shown as bits of the system memory (i.e., first memory array) that correspond to the values that are predetermined from the hardware register to evaluate the access rules stored in the system memory)
Dover discloses generating a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value. (See Dover, Fig. 3-4 and para. 16, 26-29, and 35-38, i.e., the processor generates a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access. If the hardware register bit value does not conform to the access rules based on the expected bit value, the memory access is denied and this will prevent unauthorized memory access from malicious attackers)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date the claimed invention was made to combine Herbeck et al.’s secure system for preventing writes to the secure portion of the memory by locking the secure portion of the memory by writing a predetermined value into a lockable register modified with Dover’s improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data.
Motivation for such an implementation would enable bit values to be used for prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. (See Dover, para. 16 and 28)
Referring to claim 10, (Herbeck et al. modified by Dover) discloses wherein: the hardware register comprises a lock until reset register; (See Herbeck et al., Col. 9, lines 15-49 and Col. 11, lines 49-55, i.e., the lockable register, item 260 comprises a lock state until the reset is released and the processor can begin execution again) and the method comprises locking the hardware register during the initializing of the system. (See Herbeck et al., Col. 10, lines 1-13 and Col. 17, lines 17-23, i.e., the processor, item 240 can lock the lockable register during the initializing of the boot of a device including the SOC, item 100)
Referring to claim 11, (Herbeck et al. modified by Dover) discloses wherein: storing the system state data in the hardware register comprises storing life cycle state data in the hardware register. (See Herbeck et al., Col. 10, lines 53-67 and Col. 11, lines 1-2, i.e., the system state data comprises the life cycle state data that is set once during the initialization phase by checking the validity using a simple mask operation)
Referring to claim 12, (Herbeck et al. modified by Dover) discloses wherein: storing the system state data in the hardware register comprises storing the system state data in a sticky until reset register. (See Herbeck et al., Col. 9, lines 15-49 and Col. 11, lines 49-55, i.e., the lockable register comprises sticky until reset disclosed as locking the lockable register after being set until the next system reset) *According to the Applicant’s specification, para. 0023, “sticky” is defined as a bit being locked after being set until the next system reset.
Referring to the rejection of claim 13, (Herbeck et al. modified by Dover) discloses wherein: the processor is to set the first sticky until reset bit of the hardware register after completion of a first phase of the initializing; (See Dover, Fig. 4 and para. 38, i.e., the first bit of the hardware register is set to 001 which is disclosed as the first initialization phase) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and the processor is configured to set a second bit of the hardware register after completion of a second phase of the initializing. (See Dover, Fig. 4 and para. 38, i.e., the second bit of the hardware register is set to 010 which is disclosed as the second initialization phase)
The rationale for combining Herbeck et al. in view of Dover is the same as claim 9.
Referring to the rejection of claim 14, (Herbeck et al. modified by Dover) discloses wherein: the processor is configured to set the first sticky until reset bit of the hardware register responsive to a life cycle state of the system having a first value; (See Dover, Fig. 4 and para. 38, i.e., the first sticky until reset bit of the hardware register is set to 001 which is disclosed as the life cycle state defined as the chip developer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
the processor is configured to set the second sticky until reset bit of the hardware register responsive to the life cycle state having a second value; (See Dover, Fig. 4 and para. 38, i.e., the second sticky until reset bit of the hardware register is set to 010 which is disclosed as the life cycle state defined as the device manufacturer state) *According to the Applicant’s specification, para. 0023, “sticky until reset bit” is defined as a bit being locked after being set until the next system reset.
and the processor is configured to identify a fault condition responsive to more than one bit being set in the hardware register after completion of the initialization of the system. (See Dover, Fig. 3-4 and para. 16, 26-29, 35-38, i.e., identifying a fault condition responsive to the system state data not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access)
The rationale for combining Herbeck et al. in view of Dover is the same as claim 9.
Referring to the rejection of claim 15, (Herbeck et al. modified by Dover) discloses wherein: the hardware register comprises a life cycle state field and an initialization phase field. (See Dover, Fig. 4 and para. 38, i.e., the first bit of the hardware register is set to 001 which is disclosed as the first initialization phase and a life cycle state defined as the chip manufacturer state)
The rationale for combining Herbeck et al. in view of Dover is the same as claim 9.
Referring to the rejection of claim 22, (Herbeck et al. modified by Dover) discloses comprising: generating the system state verification parameter depending on a value of the system state data. (See Dover, Fig. 3-4 and para. 16, 26-28, and 35-38, i.e., the processor generates a combined system verification parameter and identifying a fault condition responsive to the combined system state verification parameter not matching an expected value shown as the system state data indicating a malicious attack as invalid, therefore, in order to prevent malicious code from resetting the bits in the hardware registers, the registers are restricted based on the access rules (i.e., bits of the system used to evaluate the access rules defined as system state verification data), wherein fault conditions (i.e., conditional expression) are identified if the system state data does not match a valid expected value. The conditional expressions are signaled if the read/write request is denied for memory access. If the hardware register bit value does not conform to the access rules based on the expected bit value, the memory access is denied and this will prevent unauthorized memory access from malicious attackers)
The rationale for combining Herbeck et al. in view of Dover is the same as claim 9.
13. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Herbeck et al. (US Patent No. 9,959,124) and Dover (Pub No. 2021/0049111) in further view of Nemirovsky et al. (US Patent No. 7,571,270).
Herbeck et al. and Dover discloses the invention as described above in claim 9, however, the combination of Herbeck et al. and Dover fail to explicitly disclose wherein the hardware register comprises a first sticky until reset bit and a second sticky until reset bit; and the method comprises: locking the first sticky until reset bit responsive to the first sticky until reset bit being set and locking the second sticky until reset bit responsive to the second sticky until reset bit being set independent of whether the first sticky until reset bit is locked.
Nemirovsky et al. discloses a method and system for monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads.
Referring to the rejection of claim 23, (Herbeck et al. and Dover modified by Nemirovsky et al.) discloses wherein: the hardware register comprises a first sticky until reset bit and a second sticky until reset bit; and the method comprises: locking the first sticky until reset bit responsive to the first sticky until reset bit being set and locking the second sticky until reset bit responsive to the second sticky until reset bit being set independent of whether the first sticky until reset bit is locked. (See Nemirovsky et al., Fig. 2, 3, and 7, and Col. lines 25-44, i.e., lock and sticky-lock bits packed into registers, items 60 and 62 read by resource-lock monitoring software. Lock-Monitor register, item 60 contains lock bits LOCK_A, LOCK_B, LOCK_C, . . . LOCK_N for processors A, B, C, . . . N. The lock bit LOCK_X for processor X in register, item 60 is set when processor X executes a lock instruction, and reset when the lock is granted and received by processor X. Sticky-lock-Monitor register, item 62 contains sticky-lock bits STICKY_LOCK_A, STICKY_LOCK_B, STICKY_LOCK_C, . . . STICKY_LOCK_N for processors A, B, C, . . . N. The sticky-lock bit STICKY_LOCK_X for processor X in register, item 62 is set when processor X executes a sticky-lock instruction, and reset when the clear-sticky signal is generated by the system's lock monitor. While individual lock and sticky-lock bits are set in registers items 60 and 62 as each processor executes a lock instruction, and lock bits in register, item 60 are individually cleared by the lock grant for a particular processor, individual sticky-lock bits are cleared by the clear-sticky signals from the central lock monitor based on the sampled state of sticky-lock bits)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date the claimed invention was made to combine Herbeck et al.’s secure system for preventing writes to the secure portion of the memory by locking the secure portion of the memory by writing a predetermined value into a lockable register modified with Dover’s improved computer system security by restricting memory access at the memory system to one or more locations based upon the value of the control register which may be reflective of the system state measurement data modified with Nemirovsky et al.’s method and system for monitoring of shared-resource locks in a multi-processor system with locked-resource bits packed into registers to detect starved threads.
Motivation for such an implementation would enable sticky-lock bits to remain set until sticky-lock bits are cleared by monitoring software at the end of a monitoring period wherein the monitoring software reads the lock and sticky-lock bits and finds a locked processor when a processor's lock bit is still set, but its sticky-lock bit is cleared. (See Nemirovsky et al., Abstract)
Conclusion
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/COURTNEY D FIELDS/Examiner, Art Unit 2436 November 22, 2025
/SHEWAYE GELAGAY/Supervisory Patent Examiner, Art Unit 2436