CTFR 17/854,955 CTFR 86604 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This office action is in response to the claim listing filed on January 26 th , 2026. Claims 1-20 are currently pending. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over Sankaran et al. (USPGPUB No. 2020/0401440 A1, hereinafter referred to as Sankaran ) in view of Koufaty et al. (USPGPUB No. 2021/0374087, hereinafter referred to as Koufaty ). Referring to claim 1, Sankaran discloses a system comprising {“DSA architecture” ([0393] or equivalent system “data streaming accelerator (DSA) contains two or more engines 355” (see Fig. 35, [0500], 1 st sentence) as part of “an accelerator includes PCI configuration” (see Fig. 29 [0377], 1 st sentence)} : a peripheral device accessible {“[Peripheral] Interrupts generated by”, see Fig. [0552]} to a virtual machine via direct memory access (DMA) {virtual machine component “VMM” ([0552])} translated by an input/output memory management unit IOMMU {“IOMMU 2810 on the host processor 2802 may operate as the central point of control and coordination for these [DMA] functions”, see Fig. 28 [0373], last two sentences}; and a processing device to run the virtual machine {“populated by the CPU or by privileged (ring 0 or VMM) software on the host”, see Fig. 38 [0512], 2 nd sentence} and a virtual machine manager to manage the virtual machine {claimed “[management] Remapping and Posting hardware as configured by the kernel or VMM software”, see Fig. 39, [0552]} , wherein the processing device comprises the IOMMU {“[processing device] DSA supports the use of either physical or virtual addresses” that comprises the claimed IOMMU “distinction is controlled by the programming of the IOMMU 1710” (see Fig. 39, both citations in [0615])} ; Sankaran does not appear to explicitly disclose wherein the IOMMU is configurable to reserve a subset of resources of the IOMMU to the virtual machine based on a descriptor provided by the virtual machine manager. Furthermore, Koufaty discloses wherein the IOMMU is configurable to reserve a subset of resources of the IOMMU {“allocator and renamer block 1330 includes an allocator to reserve resources”, see Fig. 13, [0097], 1 st sentence} to the virtual machine based {“the transaction message to a destination, such as the IOMMU 116”, see Fig. 7, [0073]} on a descriptor provided by the virtual machine manager {“fine-grained memory isolation (such as per virtual machine or per process) as defined by software (e.g., by a virtual machine manager (VMM)” (see Fig. 1 [0032], 2 nd sentence) in which the isolation specified by descriptor “cache coherency messages, etc. In order to enforce isolation between the tenants… include a [descriptor field] a domain identifier that identifies, e.g., a particular virtual function associated with the message}” (see Fig. 1, [0025], last sentence)} . Sankaran and Koufaty are analogous because they are from the same field of endeavor, virtual machine management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Sankaran and Koufaty before him or her, to modify Sankaran’s “DSA Architecture” (see Fig. 35, [0500]) incorporating Koufaty’s “allocator and renamer block 1330 includes an allocator to reserve resources” and corresponding “IOMMU 116” (see Figs. 7 and 13, [0097], 1 st sentence). The suggestion/motivation for doing so would have been to implement a link (such as a PCIe or CXL link) to support any usages that require tagging of transactions with a sparse set of header fields more efficiently including fine-grained memory isolation while also splitting the tagging of the domain into a separate device identifier allocation message, a regular message can use a smaller tag to identify the relevant domain at the benefit used to expand the device context information associated with a device handle identifier (Koufaty [0032]). Therefore, it would have been obvious to combine Koufaty with Sankaran to obtain the invention as specified in the instant claim(s). As per claim 2, the rejection of claim 1 is incorporated and Sankaran discloses wherein the descriptor comprises a first field to identify the virtual machine {“domain identifier [field] may identify a virtual function, a virtual machine”, see Fig. 7 [0072], last two sentences} to cause the IOMMU to reserve the subset of the resources of the IOMMU to the virtual machine {“device allocation message may indicate, e.g., a DHI to allocate (e.g., an n-bit number”, see Fig. 4 [0053], 2 nd sentence} . As per claim 3, the rejection of claim 2 is incorporated and Koufaty discloses wherein the first field defines a domain identifier of the virtual machine {“one or more domain identifiers (such as a PASID or BDF identifier”, see Fig. 6 [0049], 3 rd sentence} . As per claim 4, the rejection of claim 2 is incorporated and Koufaty discloses wherein the descriptor comprises a second field to identify an application running on the virtual machine {“message processor 404 , which may be implemented as hardware, firmware, [an application running] software, and/or any suitable combination thereof”, see Figs. 4 and 5 [0052], 1 st sentence} to cause the IOMMU to reserve the subset of the resources of the IOMMU {“where allocator and renamer block 1330 also reserves other resources, such as reorder buffers to track instruction results”, see Fig. 13 [0097], 2 nd sentence} to the application running on the virtual machine {“[application] Requester ID PASID (RID PASID), which may be defined by Intel® VT-d, in place of the PASID to perform a Secure ATS check”, see Fig. 4 or 5, [0056], last two sentences} . As per claim 5, the rejection of claim 4 is incorporated and Koufaty discloses wherein the second field defines a process address space identifier (PASID) of the application {“processor address space identifier (PASID)”, see Fig. [0053], 2 nd sentence} . As per claim 6, the rejection of claim 1 is incorporated and Sankaran discloses wherein the descriptor comprises a field to define a requested level of priority {“be shared [requested] WQs with different priorities”, see Fig. 36 [0503], 2 nd sentence} to cause the IOMMU to reserve the subset of the resources of the IOMMU to the virtual machine according to the requested level {“priorities of WQs are relative to other WQs in the same group (e.g., there is no meaning to the priority level of a WQ that is in a group by itself)”, see Fig. 37 [0510], 3 rd sentence} . As per claim 7, the rejection of claim 1 is incorporated and Sankaran discloses wherein the IOMMU is configurable to stop reserving the subset of the resources of the IOMMU {“priorities of WQs are relative to other WQs in the same group (e.g., there is no meaning to the priority level of a WQ that is in a group by itself)”, see Fig. 37 [0510], 3 rd sentence} to the virtual machine based on a second descriptor provided by the virtual machine manager {“descriptor processing unit 3530 uses the Device TLB 1722 and IOMMU 1710 for source and destination address translations”, see Fig. 37 [0509], 2 nd sentence} . As per claim 8, the rejection of claim 7 is incorporated and Sankaran discloses wherein the second descriptor comprises a field that specifies that the second descriptor {“completion record 3900 is for a descriptor that was submitted as part of a batch”, see Fig. 39 [0533]} is a stop priority descriptor {“operation stopped before completion for some reason other than a fault”, see Fig. 39 [0534], last two sentences} to the IOMMU to cause the IOMMU to stop reserving {“field may also be used when the operation stopped before completion for some reason other than a fault”, see Fig. 39 [0534], last two sentences} the subset of the resources of the IOMMU to the virtual machine {“operation stops and [subset resource] the page fault is reported to software”, see Figs. 108a-b after [0447], Table B, last three sentences} . As per claim 9, the rejection of claim 7 is incorporated and Sankaran discloses wherein the second descriptor comprises a field to define a requested level of priority {“be shared [requested] WQs with different priorities”, see Fig. 36 [0503], 2 nd sentence} , set to a lowest level of priority {“the SWQ could be based on capacity, QoS/occupancy or any other policies”, see Fig. 34, [0779] last two sentences} , and to cause the IOMMU to stop reserving the subset of the resources of the IOMMU to the virtual machine {“operation stops and [subset resource] the page fault is reported to software”, see Fig. 108a-b, after [0447], Table B, last three sentences} . As per claim 10, the rejection of claim 1 is incorporated and Koufaty discloses wherein the subset of the resources of the IOMMU comprises cache resources of the IOMMU {“ message may be part of a coherent protocol such as CXL.cache or a non-coherent protocol such as CXL input/output (CXL.io).”, see Fig. 7 [0069], 2 nd sentence} . As per claim 11, the rejection of claim 1 is incorporated and Sankaran discloses wherein the peripheral device comprises at least one of a scalable input/output virtualization (SIOV) device {“Dispatch for Scalable Offload Usages”, [0711], [0712]} and a single-root input/output virtualization (SR-IOV) device {“support I/O virtualization (such as Single Root I/O Virtualization (SR-IOV)”, [0714] last sentence} . Referring to claim 12, Sankaran discloses an article of manufacture comprising one or more tangible, non-transitory machine- readable media comprising instructions that, when executed by a processing device, cause the processing device to {“populated by the [processing device] CPU or by privileged (ring 0 or VMM) software on the host”, see Fig. 38 [0512], 2 nd sentence} : and issue a priority descriptor {“command descriptor specifies the target device specific command 5801 ”, see Fig. 60, [0811], 1 st sentence} to an input/output memory management unit (IOMMU) {“descriptor processing unit 3530 uses the Device TLB 1722 and IOMMU 1710 for source and destination address translations”, see Fig. 37 [0509], 2 nd sentence} to cause the IOMMU to carry out a quality of service (QoS) policy {“swq qos considerations”, [0780], [0781]} that prioritizes the first software over second software {“be shared [requested] WQs with different priorities”, see Fig. 36 [0503], 2 nd sentence} . Sankaran does not appear to explicitly disclose determine that first software interfacing with a peripheral device is running a critical workload. Furthermore, Koufaty discloses determine that first software interfacing with a peripheral device is running a critical workload {“[critical workload] security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted”, see Fig. 4, [0056]}. Sankaran and Koufaty are analogous because they are from the same field of endeavor, virtual machine management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Sankaran and Koufaty before him or her, to modify Sankaran’s “DSA Architecture” (see Fig. 35, [0500]) incorporating Koufaty’s “allocator and renamer block 1330 includes an allocator to reserve resources” and corresponding “IOMMU 116” (see Figs. 7 and 13, [0097], 1 st sentence). The suggestion/motivation for doing so would have been to implement a link (such as a PCIe or CXL link) to support any usages that require tagging of transactions with a sparse set of header fields more efficiently including fine-grained memory isolation while also splitting the tagging of the domain into a separate device identifier allocation message, a regular message can use a smaller tag to identify the relevant domain at the benefit used to expand the device context information associated with a device handle identifier (Koufaty [0032]). Therefore, it would have been obvious to combine Koufaty with Sankaran to obtain the invention as specified in the instant claim(s). As per claim 13, the rejection of claim 12 is incorporated and Koufaty discloses wherein the instructions to determine that the first software is running a critical workload comprise instructions that {“[critical workload] security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted”, see Fig. 4, [0056]} , when executed by the processing device, cause the processing device to receive a user request {“all requests associated with the domain would be treated as untrusted”, see Fig. 4 [0056], last sentence} to prioritize the first software over other software {“deallocation manager 508 may receive a message to deallocate one or more or all of the device handles, such as from software operating on another component of the computing system 100 ”, see Fig. 5, [0063], last two sentences} also interfacing with the peripheral device {“the table 600 may be partitioned and each partition assigned to a unique connected device”, see Fig. 4 [0050], last sentence} . As per claim 14, the rejection of claim 12 is incorporated and Sankaran discloses wherein: the first software comprises a virtual machine running on the processing device {“while virtual machine monitor (VMM) software”, [0728], last sentence} ; and the instructions to determine that the first software is running the critical workload comprise instructions that {“ orthogonal to any QoS applied by the device hardware on how QoS is applied to share the execution resources of the device when processing work requests submitted by different producers”, [0781]} , when executed by the processing device, cause the processing device to determine that the first software is running the critical workload when the virtual machine is undergoing migration {“dynamically migrate a thread between different types of processing elements of the heterogeneous multiprocessors”, see Fig. 1, [0153] such as “When there is no support, typically a no operation (nop) is executed at 12405 which does not change the context associated with the thread. Because there is no change in the execution mode, instructions that follow an unsupported ABEGIN execute as normal at 12407” (see Fig. 19, 124, [0300])} . As per claim 15, the rejection of claim 12 is incorporated and Sankaran discloses wherein: the first software comprises a non-virtualized application running on the processing device {“Emulation may be used if scheduling or migration is not possible or advantageous”, see Fig. 1, [0156], last sentence} ; Koufaty discloses and the instructions to determine that the first software is running the critical workload comprise instructions that, when executed by the processing device, cause the processing device to determine, using an operating system of the processing device {“defined by software (e.g., by a virtual machine manager (VMM), hypervisor, or an operating system”, see Fig. 1 [0032], 1 st sentence} , that the first software is running the critical workload {“[critical workload] security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted”, see Fig. 4, [0056]} . As per claim 16, the rejection of claim 12 is incorporated and Sankaran discloses wherein the priority descriptor comprises: a type field encoding a start of prioritization to the IOMMU {“Address Translation Service (ATS) and Page Request Service (PRS) PCI Express capabilities,” that includes ending in DSA, see Fig. 28 [0616], 1 st sentence} ; and one or more fields identifying the first software {“be shared [requested] WQs with different priorities”, see Fig. 36 [0503], 2 nd sentence} . As per claim 17, the rejection of claim 16 is incorporated and Koufaty discloses wherein the one or more fields identifying the first software comprise: a domain identifier field corresponding to the first software {“one or more domain identifiers (such as a PASID or BDF identifier”, see Fig. 6 [0049], 3 rd sentence} ; and a process address space identifier (PASID) {“processor address space identifier (PASID)”, see Fig. [0053], 2 nd sentence} corresponding to the critical workload {“[critical workload] security validation of the access using Secure ATS will use this BDF identifier and PASID to determine if the access is permitted”, see Fig. 4, [0056]} . As per claim 18, the rejection of claim 12 is incorporated and Sankaran discloses wherein the priority descriptor comprises a priority level field to indicate a level of quality of service (QoS) policy {“the SWQ could be based on capacity, QoS/occupancy or any other policies”, see Fig. [0779] last two sentences} to implement in the IOMMU {“[IOMMU] operation stops and [subset resource] the page fault is reported to software”, see Fig. after [0447], Table B, last three sentences} . Referring to claim 19, Sankaran discloses an input/output memory management unit IOMMU) to provide address translation {“address translation is enabled in the IOMMU 2810,”, see Fig. 28 [0391], 2 nd sentence} to enable software to interact with a peripheral device {“ATS must be enabled in the [peripheral] device to obtain acceptable system performance”, see Fig. 28 [0391], 2 nd sentence} , wherein the input/output memory management unit IOMMU); Sankaran does not appear to explicitly disclose caching circuitry to cache data corresponding to address translation relating to the peripheral device; and a capability register to identify that the input/output memory management unit IOMMU is configurable to reserve a subset of resources of the caching circuitry for specified software. However, Koufaty discloses caching circuitry to cache data {“support protocols such as coherent caches that operate in the physical address domain”, [0027]} corresponding to address translation relating to the peripheral device {“A Secure ATS service on the IOMMU 116 ”, see Fig. 1 [0027]} ; and a capability register {“ new capability to support use of DHIs using, for example, a Designated Vendor-Specific Extended Capability DVSEC [register]” , see Fig. 11 [0077], last sentence} to identify that the input/output memory management unit IOMMU is configurable to reserve a subset of resources {“allocator and renamer block 1330 includes an allocator to reserve resources”, see Fig. 13, [0097], 1 st sentence} of the caching circuitry for specified software {“ message may be part of a coherent protocol such as CXL.cache or a non-coherent protocol such as CXL input/output (CXL.io).”, see Fig. 7 [0069], 2 nd sentence} . Sankaran and Koufaty are analogous because they are from the same field of endeavor, virtual machine management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Sankaran and Koufaty before him or her, to modify Sankaran’s “DSA Architecture” (see Fig. 35, [0500]) incorporating Koufaty’s “allocator and renamer block 1330 includes an allocator to reserve resources” and corresponding “IOMMU 116” (see Figs. 7 and 13, [0097], 1 st sentence). The suggestion/motivation for doing so would have been to implement a link (such as a PCIe or CXL link) to support any usages that require tagging of transactions with a sparse set of header fields more efficiently including fine-grained memory isolation while also splitting the tagging of the domain into a separate device identifier allocation message, a regular message can use a smaller tag to identify the relevant domain at the benefit used to expand the device context information associated with a device handle identifier (Koufaty [0032]). Therefore, it would have been obvious to combine Koufaty with Sankaran to obtain the invention as specified in the instant claim(s). As per claim 20, the rejection of claim 19 is incorporated and Sankaran discloses wherein the caching circuitry comprises at least one of an input/output translation lookaside buffer IOTLB) {“using an accelerator device TLB and standard PCIe address translation services”, see Fig. 28 [0376], 2 nd sentence} , a context cache {“client is in a [cache] coherent state that can be [context] resumed later”, see Fig. 28, [0571]} , a process address space identifier (PASID) cache {“The [cache] Drain PASID command”, [0376], 3 rd sentence} , or a paging cache {“host memory cache 2834 for locally caching pages stored in the host memory 2860 ”, see Fig. 28 [0374]}. Response to Arguments Applicant’s arguments filed on 01/26/2026 have been considered but deemed moot in view of the following explanation: Applicant alleges that the references Sankaran and Koufaty does not appear to disclose “a processing device to run the virtual machine and a virtual machine manager to manage the virtual machine, wherein the processing device comprises the IOMMU, wherein the IOMMU is configurable to reserve a subset of resources of the IOMMU to the virtual machine based on a descriptor provided by the virtual machine manager” (Remarks page 6, last full paragraph to page 7, 2 nd sentence) . The Examiner will elaborate on the claim interpretation and later draw parallels to the references, particularly Koufaty. Claim 1 recites an IOMMU broad functionality to be “configurable to reserve”, however such reservation is an allocation means/algorithm/steps that are not further elaborated as to a table/correlation/length of time between the virtual machine manager (VMM) and respective “IOMMU resource”. Accordingly to discrete mathematics, claim 1’s subset of “null” or “zero” is inclusive to mapping a resource to a VMM, however does not further elaborate what kind of resources such as hardware/software/memory in any claims related to claim 1. In addition, IOMMU defines a caching circuitry in another independent claim 19, with a capability register to reserve resources, the sole dependent claim 20 as essentially a Markush claim further defines these resources as IOTLB, context cache, PASID cache, OR a paging cache. Sankaran maps to all three group members, however Koufaty needs only indicate at least one member, “paging cache” to address claim 20 as well as meet Applicant allegations surrounding IOMMU comprising at least one resource. In other words, in one claim set has a IOMMU allocating (undefined) resources to a VMM, and the other claim set 19 and 20 IOMMU simply reserves types of resources but not to a VMM (or any entity for that matter) outside of “specified software”. In the specification recites “reserve”/”reserving” or permutated ad nauseum, Figure 12 best illustrating “IOMMU 310” with the claim 20 elements “PASID 354”, “PAGING 366” (PGPUB [0104]). The Examiner should point out that the combination of references as well as the instant specification share common assignee Intel, thus the Counsel arguments run the risk of discrediting their own disclosed concepts. Turning to Koufaty Figure 1, “IOMMU 116” purpose/functionality “performs address translation from GPA, GPA or IOVA to HPA to allow the offload device access to system memory 110” ([0026], last sentence) 110”. Although not illustrated in Koufaty Figure 1, to perform such address translation “A Secure ATS service on the IOMMU 116 can enforce isolation of the physical addresses that a device can access using a physical-indexed table that contains permissions for each page 110”, the IOMMU 116 comprising the hardware resource subset “physical-indexed table” that serves the claim 1 reservation to the VMM “The [IOMMU physical-indexed] table can be set up on a per-domain basis (e.g., for each virtual machine in a virtual environment…” (both citations in [0027]). Per the motivation contention in this section, Sankaran ATS service ([0616], 1 st two sentences) the older reference gains benefit to Koufaty newer functionality “Secure ATS” in an environment that includes IOMMU, virtual machines, and PCIE (Peripheral Component Interface Express). The motivation respectfully maintained as present recited above. Applicant alleges that the references Sankaran and Koufaty does not appear to disclose roughly the totality of claim 12 on the basis that the Office Action cites command descriptor for the priority lacking the necessary relationship tying to the SWQ QOS as well as the terminology used in Koufaty does not teach “a critical workload” (Remarks page 7 last sentence through page 8, between claim 12 and claim 19 recitations) . Again, reiterating on claim interpretation here, claim 12 determining step of running a critical workload bares no assertion to the priority descriptor referring to the first software. Second issue, the term “critical workload” is not defined in the independent claim 12, only by dependent claim 15 includes further instructions indicating to an operating system that the first software running the critical workload. Claim 14 presents an example where a critical workload is running when the virtual machine is undergoing migration but this migration bares no impact on where/what/which element is executing a second software. In other words, per the claim set independent claim 12 is not further elaborated on what constitutes as a “critical workload”. Turning to the instant specification recites the term “critical workload” ad nauseum, one example being “specific application running on the VM 304 has been selected based on a critical business priority and a level of desired prioritization” (PGPUB [0125]). Claim 15 recites workload instructions in instant specification PGPUB [0148], however those appear in the “Example Embodiments” section and does not have a corresponding Figure/illustration to show how the operating system would made aware of such “critical workload” as long as it occurs during migration. A migration that Sankaran already cited in their respective claim(s), another example “emulator is used to execute the [critical workload] code until it exits AEND after migration when the ABEGIN/AEND code is interrupted and migrated to a machine that does not have the same accelerator type” (Sankaran [0324]). For these reasons the current ground of rejection(s) is respectfully maintained. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C. B./ Examiner, Art Unit 2184 /HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184 Application/Control Number: 17/854,955 Page 2 Art Unit: 2184 Application/Control Number: 17/854,955 Page 3 Art Unit: 2184 Application/Control Number: 17/854,955 Page 4 Art Unit: 2184 Application/Control Number: 17/854,955 Page 5 Art Unit: 2184 Application/Control Number: 17/854,955 Page 6 Art Unit: 2184 Application/Control Number: 17/854,955 Page 7 Art Unit: 2184 Application/Control Number: 17/854,955 Page 8 Art Unit: 2184 Application/Control Number: 17/854,955 Page 9 Art Unit: 2184 Application/Control Number: 17/854,955 Page 10 Art Unit: 2184 Application/Control Number: 17/854,955 Page 11 Art Unit: 2184 Application/Control Number: 17/854,955 Page 12 Art Unit: 2184 Application/Control Number: 17/854,955 Page 13 Art Unit: 2184 Application/Control Number: 17/854,955 Page 14 Art Unit: 2184 Application/Control Number: 17/854,955 Page 15 Art Unit: 2184 Application/Control Number: 17/854,955 Page 16 Art Unit: 2184 Application/Control Number: 17/854,955 Page 17 Art Unit: 2184 Application/Control Number: 17/854,955 Page 18 Art Unit: 2184 Application/Control Number: 17/854,955 Page 19 Art Unit: 2184
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