DETAILED ACTION
Claims 1, 4-10, 13-19 and 22-27 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, 11, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over WO No. 2021102252 A1 Nijasure et al. in view U.S. Pub. No. 201/20169930 A1 to Carter.
As to claim 1, Nijasure teaches an apparatus comprising:
at least one memory (RAM);
machine readable instructions (computer readable storage medium); and
at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to (CPU 101):
identify a first trigger frequency associated with a first application thread (Program/Program Thread 103);
identify a second trigger frequency associated with a second application thread (Program/Program Thread 104), the second trigger frequency different from the first trigger frequency (clock frequency for program/thread 104) (“…It will be appreciated that the CPU 101 executes the programs 103 and 104 concurrently. Thus, in some embodiments, the CPU 101 provides different commands, associated with different ones of the programs 103 and 104 to the GPU 102 in a time-multiplexed fashion for execution. To illustrate, in some embodiments, the CPU 101 provides the command 105 to the GPU 102 for execution on behalf of program 103, followed by command 107 for execution on behalf of program 104, followed by another command (not shown) for execution on behalf of program 103. As described further herein, in some cases the different programs, and therefore the different commands, have different specified processing requirements such as different required clock frequencies, in order for the programs to meet specified quality or other requirements, such as a specified display frame rate. The GPU 102 identifies the different processing requirements by analyzing workloads generated based on the commands, and adjusts processing parameters such as a clock frequency based on the identified processing requirements. The GPU 102 thereby adjusts the processing parameters dynamically, based on a combination of processing demands and specified processing requirements, rather than based on fixed processing parameter values…The CPU 101 is generally configured to execute multiple programs, and corresponding program threads concurrently. As used herein, a program thread refers to either of an individual program (e.g., an operating system, an application program, and the like) or an individual thread of a multithreaded program. In the depicted example, the CPU 101 concurrently executes two program threads, designated program 103 and program 104. However, it will be appreciated that the techniques described with respect to FIG. 1 are, in other embodiments, implemented at a processing system concurrently executing N programs, where N is an integer greater than 1. Thus, in some embodiments, the CPU 101 implements a virtualized computing environment by concurrently executing multiple virtual machines, wherein programs 103 and 104 correspond to programs executed by different virtual machines. For example, in some embodiments program 103 is an operating system associated with one virtual machine, and program 104 is an operating system associated with a different virtual machine executing at the processing system. It is assumed for purposes of description that each of the programs 103 and 104 have different processing specifications, such as different specified processing speeds, power consumption specifications, and the like. For example, in some embodiments the program 103 is a “legacy” program that is specified to execute at a relatively low frequency in order to provide backward compatibility for other programs or hardware components of the processing system, while the program 104 is a newer program that is specified to execute at a relatively high frequency in order to meet performance targets. As described further herein, the GPU 102 is able to adjust specified parameters, and in particular a clock frequency of the GPU 102, so that each of the programs 103 and 104 complies with its processing specifications…”);
determine a third trigger frequency (adjust/Clock Frequency Adjustment Module (CFAM) 108) based on the first and second trigger frequencies (“…As described further herein, the GPU 102 is able to adjust specified parameters, and in particular a clock frequency of the GPU 102, so that each of the programs 103 and 104 complies with its processing specifications…To illustrate, the overall use of the resources of the GPU 102 based on a received command, or set of commands, is referred to herein as a workload (e.g., workloads 116 and 117). A heavier or higher workload uses more of the resources of the GPU 102, while a lighter or lower workload uses fewer resources of the GPU 102. Thus, the workload generated by a particular one of the programs 103 and 104 is based on the commands generated by the program. Further, the workload generated by a program is generally correlated with the processing specifications for that program. Thus, for example, a program having a relatively high execution frequency (that is, a program that is expected or specified to execute quickly) generally generates heavier workloads (that is, workloads that require more resources for execution). In contrast, a program having a relatively low specified execution frequency generates lighter workloads (that is, workloads that require more resources for execution). To accommodate concurrently executing programs having different specified execution frequencies, the GPU 102 includes a clock frequency adjustment module (CFAM) 108. The CFAM 108 monitors parameters indicative of the current workload of the GPU 102 and thereby, in effect, detects which of the programs 103 and 104 is presently being executed at the GPU 102 and provides control signaling to the clock control module 110 to set the frequency of the clock signal CK to the specified clock frequency for the detected program. Examples of the parameters monitored by CFAM 108 include, in some embodiments, the number of wavefronts scheduled by the scheduler 106 at the compute units 115 in a specified amount of time, the number of draw commands received by the GPU 102 in a specified amount of time, the type of draw or dispatch command, a hint provided by a compiler, and the like, or any combination thereof. If the monitored parameters exceed a workload threshold, the CFAM 108 increases the frequency of the CK signal to a higher specified frequency F2. In response to the monitored parameters falling below the workload threshold for a specified amount of time, the CFAM 108 reduces the clock frequency of the CK signal to a lower specified frequency Fi. In some embodiments, the higher and lower specified frequencies F2 and Fi are indicated by the programs 103 and 104 during initialization of the corresponding program, via a command provided by each program to the GPU 102, and the like. Further, in some embodiments, the workload threshold and the frequencies Fi and F2 are programmable values, allowing a programmer to tune performance of the executing programs to a desired level…”).
adjust clock circuitry based on the first and second trigger frequencies (frequencies of concurrent executing programs 103 and 104) to provide a third trigger frequency (designated frequency/ ramping the clock from a second frequency to the first frequency: NOTE: ramping the clock implies adjusting the gradually (third frequency) rather than straight to F2 or F1) and
adjusting to synchronize the first trigger frequency and the second trigger frequency to the third trigger frequency (synchronize operations/ designated frequency/ramping the clock from a second frequency to the first frequency: NOTE: ramping the clock implies adjusting the gradually (third frequency) rather than straight to F2 or F1) (“…To synchronize operations at the compute units 115 (as well as other modules) the GPU 102 employs a clock control module 110 to generate a clock signal CK and provides the CK signal to each of the compute units 115. In some embodiments, the clock control module 110 includes one more control loops, such as frequency locked loop (FLL) to lock the frequency of the clock signal CK to a designated frequency, wherein the designated frequency is adjustable via control signaling as described further herein. In particular, the GPU 102 sets the control signaling for the clock control module 110 to set the frequency of the clock signal CK based on the processing demands placed on the GPU 102 by the programs 103 and 104 so that each program complies with its processing specifications…the plurality of program threads are concurrently executed at a central processing unit (CPU); and in response to identifying the first program thread, adjusting a clock of the GPU to a first frequency associated with the first program thread. In one aspect, identifying the first program thread includes identifying the first program thread in response to the first workload exceeding a first workload threshold. In another aspect, the method includes identifying a second program thread of the plurality of program threads based on a first workload to be executed at the GPU; and in response to identifying the second program thread, adjusting the clock of the GPU to a second frequency associated with the second program thread. In yet another aspect, adjusting the clock includes ramping the clock from a second frequency to the first frequency…”).
Nijasure is silent with reference to the first trigger frequency corresponding to an audio capture rate, the audio application thread to process first requests that occur at the first trigger frequency corresponding to the audio capture rate, the first requests associated with processing audio data,
the second trigger frequency corresponding to of a video frame rate, the video application thread to process second requests that occur at the second trigger frequency corresponding to the video frame rate, the second requests associated with processing video data and
cause the first requests that occur at the first trigger frequency and the second requests that occur at the second trigger frequency to be aligned based on the third trigger frequency.
Carter teaches the first trigger frequency corresponding to an audio (audio) capture rate (48 kHz), the audio application thread to process first requests (signal) that occur at the first trigger frequency corresponding to the audio capture rate, the first requests associated with processing audio data (audio) (“…In system 100, clock frequencies, 60 Hz and 48 kHz, are independently derived and are used for video and audio generation, respectively. Each of the frequencies is derived from respective crystal clocks. For example, the 48 kHz audio signal is derived from a crystal clock within SB 102. Similarly, the 60 Hz video signal is derived from a crystal clock within display chip/GPU 104. A peripheral component interface express (PCIe) bus 106 provides an interface between SB 102 and display chip/GPU 104 and facilitates synchronization of timing information…” paragraphs 0021, Step 602),
the second trigger frequency corresponding to of a video (video) frame rate (60 Hz), the video application thread to process second requests that occur at the second trigger frequency corresponding to the video frame rate, the second requests associated with processing video data (video) (“…In system 100, clock frequencies, 60 Hz and 48 kHz, are independently derived and are used for video and audio generation, respectively. Each of the frequencies is derived from respective crystal clocks. For example, the 48 kHz audio signal is derived from a crystal clock within SB 102. Similarly, the 60 Hz video signal is derived from a crystal clock within display chip/GPU 104. A peripheral component interface express (PCIe) bus 106 provides an interface between SB 102 and display chip/GPU 104 and facilitates synchronization of timing information…” paragraphs 0021, Step 602) and
cause the first requests (audio and video clock signals) that occur at the first trigger frequency and the second requests (audio and video clock signals) that occur at the second trigger frequency to be aligned based on the third trigger frequency (“…Embodiments of the present invention meet the above-identified needs by providing a method for synchronizing audio and video clock signals in a system. The method includes comparing, within a comparison module, a system video signal with the determined mathematical relationship to produce an adjustment signal. A system video reference signal is updated with the adjustment signal to produce an updated intermediate signal…” paragraph 0009, Step 608).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure with the teaching of Carter because the teaching of Carter would improve the system of Nijasure by providing a method for synchronizing audio and video clock signals by comparing the audio and video clock signal to produce an updated/adjusted intermediate signal (Carter paragraph 0009).
As to claims 10 and 19, see the rejection of claim 1 above.
As to claims 11 and 20, see the rejection of claim 2 above.
Claims 4, 13 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over WO No. 2021102252 A1 Nijasure et al. in view U.S. Pub. No. 201/20169930 A1 to Carter as applied to claims 1, 10 and 19 above, and further in view of U.S. Pub. No. 2013/0254417 A1 to Nicholls.
As to claim 4, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein at least one of the first trigger frequency or the second trigger frequency is associated with an application setting, the application setting including at least one of measured preview latency, targeted preview latency, measured audio/video sync, or targeted audio/video sync.
Nicholls teaches wherein at least one of the first trigger frequency or the second trigger frequency is associated with an application setting, the application setting including at least one of measured preview latency, targeted preview latency, measured audio/video sync, or targeted audio/video sync (“… If the application does not use an API to render frames, then modify the APIs cannot be used to capture frames of rendered data. Alternatively, the server agent can make calls for screen shots of the rendered frames from the operating system. The screen shots contain a buffer of the rendered frame. These calls can be made at a frame rate to keep the audio and video synced…” paragraph 0066).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Nicholls because the teaching of Nicholls would improve the system of Nijasure and Carter by providing a technique for aligning the sound with the visuals to create a cohesive and professional-looking video.
As to claims 13 and 22, see the rejection of claim 4 above.
Claims 5-7, 14-16 and 23-25 and are rejected under 35 U.S.C. 103 as being unpatentable over WO No. 2021102252 A1 Nijasure et al. in view U.S. Pub. No. 201/20169930 A1 to Carter as applied to claims 1, 10 and 19 above, and further in view of WO No. 2013081602 A1 to Apodaca.
As to claim 5, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein the processor circuitry is to determine the third trigger frequency based on a minimum of the first trigger frequency and the second trigger frequency.
Apodaca teaches wherein the processor circuitry is to determine the third trigger frequency based on a minimum of the first trigger frequency and the second trigger frequency (the minimum frame rate) (“…The logic flow 300 may put the CPU thread associated with the application 130 generating the frames into a sleep state while the time differential is greater than zero (0) at block 350. For example, because the time differential is greater than zero (0) milliseconds the system 100 may be able to reduce its workload by reducing the frame rate to the minimum frame rate supported by the application 130. This may be done by putting the CPU thread generating frames 155 for application 130 into a sleep state for the time differential calculated at block 340. Referring to the example, the CPU thread may generate a frame 155 in 13.33 milliseconds and make a call to the graphics driver 140 to present the frame 155. Under normal conditions, the CPU thread would remain in an active state and continue working and move on to generating a next frame. However, by putting the CPU thread into a sleep state for the time differential of 6.67 milliseconds, the CPU 110 and need not work to generate frames 155 during those 6.67 milliseconds. So long as the time differential remains positive, the CPU thread will kept in a sleep state. Once the time differential has expired to zero, the graphics driver 140 may then present the frame to the display 160 at block 355. The net result is that the CPU thread in this example may be put into a sleep state for 50% of the time to force the current frame rate of 75 FPS down to the minimum frame rate of 50 FPS thereby conserving power and extending the life of the battery 180. The numbers used in the example are illustrative and may be different for different systems 100 or applications 130. The embodiments are not limited in this context….” paragraph 0031).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Apodaca because the teaching of Apodaca would improve the system of Nijasure and Carter by providing a technique for allowing for optimal frame rate display.
As to claim 6, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein the processor circuitry is to determine the third trigger frequency based on a maximum of the first trigger frequency and the second trigger frequency.
Apodaca teaches the processor circuitry is to determine the third trigger frequency based on a maximum of the first trigger frequency and the second trigger frequency (a maximum frame execution rate of 75 FPS) (“…The graphics driver 140 may be called by the application 130 to present a frame 155. The time between successive calls to resent a frame 155 is termed the frame rate and may be expressed in milliseconds. Under normal operating conditions, each application 130 will execute according to the settings specified within the given application 105. For example, an application 130 may have a minimum frame execution rate of 50 FPS which corresponds to a frame rate execution time of 20 milliseconds per frame. The same application 130 may have a maximum frame execution rate of 75 FPS which corresponds to a frame rate execution time of…” paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Apodaca because the teaching of Apodaca would improve the system of Nijasure and Carter by providing a technique for allowing for optimal frame rate display.
As to claim 7, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein the processor circuitry is to determine the third trigger frequency based on an average of the first trigger frequency and the second trigger frequency.
Apodaca teaches wherein the processor circuitry is to determine the third trigger frequency based on an average of the first trigger frequency and the second trigger frequency (“…The logic flow 500 may determine a reduced frame rate execution time as function of remaining battery power 180 at block 540. For example, the reduced frame rate execution time may be determined based on a percentage of the current frame rate calculated at block 535. If the current frame rate is 75 FPS and the minimum frame rate is 50 FPS, then the application may support a frame rate between 50 and 75 FPS. Since the system 100 is operating on battery power 180, a reduction in the frame rate may conserve power. For instance, a 20% reduction of the current frame rate would reduce the frame rate to 60 FPS. Sixty (60) FPS corresponds to one frame every 16.67 milliseconds…” paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Apodaca because the teaching of Apodaca would improve the system of Nijasure and Carter by providing a technique for allowing for optimal frame rate display.
As to claims 14 and 23, see the rejection of claim 5 above.
As to claims 15 and 24, see the rejection of claim 6 above.
As to claims 16 and 25, see the rejection of claim 7 above.
Claims 8, 9, 17, 18, 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over WO No. 2021102252 A1 Nijasure et al. in view U.S. Pub. No. 201/20169930 A1 to Carter as applied to claims 1, 10 and 19 above, and further in view of WO No. 2015104953 A1 to Urano.
As to claim 8, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein the processor circuitry is to delay at least one of the first requests or the second requests to cause the first requests and the second requests to be aligned based on the third trigger frequency.
Urano teaches wherein the processor circuitry is to delay at least one of the first requests or the second requests to cause the first requests and the second requests to be aligned based on the third trigger frequency (stop command) (“…When occurrence of an event registered in the event correspondence table 611 is detected, the image request issuing unit 603 is determined by the frame rate determining unit 602 for the camera 10 corresponding to the notified camera ID of the camera 10. An image request 106 is issued according to the frame rate. That is, the timing at which the image request 106 is issued is adjusted according to the detected event. For example, when the notified frame rate is “10 fps”, the image request issuing unit 603 issues up to 10 image requests 106 per second. When receiving the notification of the frame rate from the frame rate determining unit 602, the image request issuing unit 603 starts the timer 610, and receives an image request 106 from the Web server 12 according to the notified frame rate until a stop command is received from the timer 610. Issue. The timer 610 issues a stop command to the image request issuing unit 603 after a predetermined time has elapsed since activation. Note that the image request issuing unit 603 may perform control so that the frame rate of the real-time image data 101 captured by the camera 10 selected by the administrator is set to the highest…”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Urano because the teaching of Urano would improve the system of Nijasure and Carter by providing a technique for managing how and when image requests are processed.
As to claim 9, Nijasure as modified by Carter teaches the apparatus of claim 1, however it is silent with reference to wherein the processor circuitry is to generate a notification, the notification to identify an adjustment of at least one of the first trigger frequency or the second trigger frequency.
Urano teaches wherein the processor circuitry is to generate a notification, the notification to identify an adjustment of at least one of the first trigger frequency or the second trigger frequency (receiving the notification of the frame rate) (“…When occurrence of an event registered in the event correspondence table 611 is detected, the image request issuing unit 603 is determined by the frame rate determining unit 602 for the camera 10 corresponding to the notified camera ID of the camera 10. An image request 106 is issued according to the frame rate. That is, the timing at which the image request 106 is issued is adjusted according to the detected event. For example, when the notified frame rate is “10 fps”, the image request issuing unit 603 issues up to 10 image requests 106 per second. When receiving the notification of the frame rate from the frame rate determining unit 602, the image request issuing unit 603 starts the timer 610, and receives an image request 106 from the Web server 12 according to the notified frame rate until a stop command is received from the timer 610. Issue. The timer 610 issues a stop command to the image request issuing unit 603 after a predetermined time has elapsed since activation. Note that the image request issuing unit 603 may perform control so that the frame rate of the real-time image data 101 captured by the camera 10 selected by the administrator is set to the highest…”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Nijasure and Carter with the teaching of Urano because the teaching of Urano would improve the system of Nijasure and Carter by providing a technique for managing how and when image requests are processed.
As to claims 17 and 26, see the rejection of claim 8 above.
As to claims 18 and 27, see the rejection of claim 9 above.
Response to Arguments
Applicant’s arguments with respect to claims 1, 4-10, 13-19 and 22-27 have been considered but are moot because the new ground of rejection relies on additional reference not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHARLES E ANYA/Primary Examiner, Art Unit 2194