DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Action is non-final and is in response to the claims filed June 30 th , 2022. Claims 1- 20 are pending, of which claims 1-2, 12-16, and 1 7 -20 are rejected. Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 1 2/31/2019 . Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/28/2023, 01/30/2023, 04/04/2023, 05/24/2023, 10/29/2023, 12/25/2023, 12/10/2024 is in compliance with the provisions of 37 CFR 1.97. It has been placed in the application file, and the information referred to therein has been considered as to the merits. Drawings The drawings are objected to because none of the figures show the computation mode switching circuit as claimed in Claim 12. Although Fig. 14 shows a line labeled as “Mode switching”, the figure does not actually show any switching element or the means by which computation mode switching circuit is set so that the floating-point number decomposition circuit and the exponent adjustment circuit are invalid. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended”. If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. In addition to Replacement Sheets containing the corrected drawing figure(s), applicant is required to submit a marked-up copy of each Replacement Sheet including annotations indicating the changes made to the previous version. The marked-up copy must be clearly labeled as “Annotated Sheets” and must be presented in the amendment or remarks section that explains the change(s) to the drawings. See 37 CFR 1.121(d)(1). Failure to timely submit the proposed drawing and marked-up copy will result in the abandonment of the application. Claim Objections Claim 18 is objected to because of the following informalities: On lines 1-2 “first-precision intermediate result” should be “first-precision intermediate computation result” One lines 4-5 “first-precision intermediate result” should be “first-precision intermediate computation result”. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-6, 8-9, 11, 13 -20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Regarding claim 1 , at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Claim language recites floating-number decomposition into a plurality of lower precision values and carrying out operations through the use of combinations of the lower precision values. Below are the limitations of claim 1 that recite an abstract idea under mathematical concepts: decompose each input to-be-computed first-precision floating-point number into at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number being lower than a first precision of the first-precision floating-point number; a combination comprising two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; perform a multiplication operation on the second-precision floating-point numbers in each combination; and perform an operation to obtain a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include: An arithmetic logic unit a processor a floating-point number decomposition circuit a second-precision multiplier receive a combination comprising two second-precision floating-point numbers output an intermediate computation result corresponding to each combination . These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer , as to the arithmetic logic unit and the processor . Furthermore , the limitations a floating-point number decomposition circuit, and a second precision multiplier merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application. There are insignificant extra-solution activit i es that must be made of note as shown below: receive a combination comprising two second-precision floating-point numbers ( data gathering falling under insignificant extra-solution activity ) output an intermediate computation result corresponding to each combination (outputting of data or a result is well-known in the art) . At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea. In regards to the insignificant extra-solution activity found in this limitation “ receive a combination comprising two second-precision floating-point numbers ”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well ‐ understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i . Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE , Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “ output an intermediate computation result ”, this action describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer ( Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, edited by Peter J Ashenden , Elsevier Science & Technology, 2007 , hereinafter “Patterson” : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 1 is not eligible. Regarding claim 2, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea Below are the limitations of claim 2 that recite an abstract idea under mathematical concepts: wherein the operation is a summation operation. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 1 . At Step 2B, the re are no further additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 2 does not amount to significantly more than the abstract idea. Claim 2 is not eligible. Regarding claim 3, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea Below are the limitations of claim 3 , in addition to those recited in claim 1, that recite an abstract idea under mathematical concepts: adjust, based on the exponent bias value corresponding to the second-precision floating-point number in each input combination, an exponent of the intermediate computation result corresponding to each input combination. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, further additional elements not reciting mathematical equations and mathematical calculations thereof include: A n exponent adjustment circuit output, to the exponent adjustment circuit, an exponent bias value corresponding to each second-precision floating-point number output, to the exponent adjustment circuit, the intermediate computation result corresponding to each combination; and output an adjusted intermediate computation result to the accumulator. The additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. For these reasons, the additional element s, whether alone or in combination , do es not integrate the abstract idea into a practical application . There are insignificant extra-solution activit ies that must be made of note as shown below: output, to the exponent adjustment circuit, an exponent bias value corresponding to each second-precision floating-point number (outputting of data or a result is well-known in the art ) output, to the exponent adjustment circuit, the intermediate computation result corresponding to each combination; and (outputting of data or a result is well-known in the art ) output an adjusted intermediate computation result to the accumulator. (outputting of data or a result is well-known in the art ) At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 3 does not amount to significantly more than the abstract idea. In regards to the insignificant extra-solution activity found in this limitation “output, to the exponent adjustment circuit, an exponent bias value corresponding to each second-precision floating-point number ”, this action describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “output, to the exponent adjustment circuit, the intermediate computation result corresponding to each combination ”, this action describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer ( Patterson Pg . 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “output an adjusted intermediate computation result to the accumulator ”, this action describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 3 is not eligible. Regarding claim 4, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea Below are the limitations of claim 4 in addition to those recited in claim 3 that recite an abstract idea under mathematical concepts: add the exponent bias value corresponding to the second-precision floating-point number in each input combination and the exponent of the intermediate computation result corresponding to each input combination. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements beyond those recited in claims 3 and 1, upon which claim 4 depends . At Step 2B, the re are no further additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 4 does not amount to significantly more than the abstract idea. Claim 4 is not eligible. Regarding claim 5, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea Below are the limitations of claim 5 that recite an abstract idea under mathematical concepts: wherein the intermediate computation result is a first-precision intermediate computation result, and the computation result is a first-precision computation result. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements beyond those recited in claims 3 and 1, upon which claim 5 depends . At Step 2B, the re are no further additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 5 does not amount to significantly more than the abstract idea. Claim 5 is not eligible. Regarding claim 6, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea Below are the limitations of claim 6 that recite an abstract idea under mathematical concepts: wherein the first-precision floating-point number is a single-precision floating-point number, the second-precision floating-point number is a half - precision floating-point number, the first-precision intermediate computation result is a single - precision intermediate computation result, the first-precision computation result is a single - precision computation result, and the second-precision multiplier is a half-precision multiplier; or the first-precision floating-point number is a double-precision floating-point number, t he second-precision floating-point number is a single-precision floating-point number, the first - precision intermediate computation result is a double-precision intermediate computation result, the first-precision computation result is a double-precision computation result . All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, further additional elements not reciting mathematical equations and mathematical calculations thereof include: the second-precision multiplier is a half-precision multiplier and the second-precision multiplier is a single-precision multiplier The additional elements are recited at a high level of generality to merely generically recite computing components which flow directly from the function performed . For these reasons, the additional element s, whether alone or in combination, do not integrate the abstract idea into a practical application . At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than gener ically recite computing components . For these reasons, claim 6 does not amount to significantly more than the abstract idea. Claim 6 is not eligible. Regarding claim 13, at Step 1, the claim is directed to a statutory category of invention ( method ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites a floating-number decomposition into a plurality of lower precision values and carrying out operations through the use of combinations of the lower precision values. Below are the limitations of claim 13 that recite an abstract idea under mathematical concepts: decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating - point number is lower than a first precision of the first-precision floating-point number; determining various combinations comprising two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, further additional elements not reciting mathematical equations and mathematical calculations thereof include: o btaining a plurality of to-be-computed first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination. There are insignificant extra-solution activit i es that must be made of note as shown below: obtaining a plurality of to-be-computed first-precision floating-point numbers ( data gathering falling under insignificant extra-solution activity ) inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination ( inputting of data or a result is well-known in the art) . At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 3 does not amount to significantly more than the abstract idea. In regards to the insignificant extra-solution activity found in this limitation “ obtaining a plurality of to-be-computed first-precision floating-point numbers ”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well ‐ understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i . Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE , Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “ inputting the second-precision floating-point numbers ”, this action describes data in putting that is recited at a high level of generality. As is known in the art, in putting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 1 3 is not eligible. Regarding claim 14, at Step 1, the claim is directed to a statutory category of invention (m ethod ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Below are the limitations of claim 14 that further recite an abstract idea under mathematical concepts: determining an exponent bias value corresponding to each second-precision floating-point number; and the determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination comprises: adjusting, based on the exponent bias value corresponding to the second-precision floating-point number in each combination, an exponent of the intermediate computation result corresponding to each combination, to obtain an adjusted intermediate computation result; and performing a summation operation on the adjusted intermediate computation results corresponding to all the combinations to obtain the computation result for the plurality of first-precision floating-point numbers. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements. At Step 2B, the re are no further additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 1 4 does not amount to significantly more than the abstract idea. Claim 1 4 is not eligible. Regarding claim 15, at Step 1, the claim is directed to a statutory category of invention ( method ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Below are the limitations of claim 15 that further recite an abstract idea under mathematical concepts: based on the exponent bias value corresponding to the second-precision floating-point number in each combination, an exponent of the intermediate computation result corresponding to each combination, to obtain an adjusted intermediate computation result adding the exponent of the intermediate computation result corresponding to each combination of second-precision floating-point numbers and the exponent bias value corresponding to the second-precision floating-point number in each combination, to obtain the adjusted intermediate computation result. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements . At Step 2B, the re are no further additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 1 5 does not amount to significantly more than the abstract idea. In regards to the insignificant extra-solution activity found in this limitation “ based on the exponent bias value corresponding to the second-precision floating-point number in each combination, an exponent of the intermediate computation result corresponding to each combination, to obtain an adjusted intermediate computation result ”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well ‐ understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i . Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE , Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 1 5 is not eligible. Regarding claim 16, a t Step 1, the claim is directed to a statutory category of invention ( method ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Below are the limitations of claim 1 6 that further recite an abstract idea under mathematical concepts: wherein the intermediate computation result is a first - precision intermediate computation result, and the computation result is a first-precision computation result. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no further additional elements. At Step 2B, the re are no additional elements that amount to significantly more than the recited judicial exception. For these reasons, claim 1 6 does not amount to significantly more than the abstract idea. Claim 1 6 is not eligible. Regarding claim 17, at Step 1, the claim is directed to a statutory category of invention (m ethod ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Below are the limitations of claim 17 that further recite an abstract idea under mathematical concepts: performing format conversion on each first-precision intermediate computation result to obtain a third-precision intermediate computation result corresponding to each combination, wherein precision of the third-precision intermediate computation result is higher than precision of the first-precision intermediate computation result; the adjusting, based on the exponent bias value corresponding to the second-precision floating-point number in each combination, an exponent of the intermediate computation result corresponding to each combination, to obtain an adjusted intermediate computation result comp ri ses: adjusting, based on the exponent bias value corresponding to the second-precision floating - point number in each combination, an exponent of the third-precision intermediate computation result corresponding to each combination, to obtain an adjusted third-precision intermediate computation result; and the performing the summation operation on the adjusted intermediate computation results corresponding to all the combinations to obtain the computation result for the plurality of first - precision floating-point numbers comprises: performing the summation operation on the adjusted third-precision intermediate computation results corresponding to all the combinations to obtain a third-precision computation result for the plurality of first-precision floating-point numbers. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, further additional elements not reciting mathematical equations and mathematical calculations thereof include: the inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination inputting the second-precision floating-point numbers in each combination into the second-precision multiplier to obtain a first-precision intermediate computation result corresponding to each combination, There are insignificant extra-solution activit ies that must be made of note as shown below: the inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination ( inputting of data or a result is well-known in the art ) inputting the second-precision floating-point numbers in each combination into the second-precision multiplier to obtain a first-precision intermediate computation result corresponding to each combination, ( inputting of data or a result is well-known in the art ) At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception In regards to the insignificant extra-solution activity found in this limitation “ the inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination ”, this action describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “ inputting the second-precision floating-point numbers in each combination into the second-precision multiplier to obtain a first-precision intermediate computation result corresponding to each combination ”, this action describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 1 7 is not eligible. Regarding claim 18, at Step 1, the claim is directed to a statutory category of invention (m ethod ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Below are the limitations of claim 18 that recite an abstract idea under mathematical concepts: the performing the format conversion on the each first-precision intermediate result to obtain the third-precision intermediate computation result corresponding to each combination comprises: performing zero padding processing on an exponent and a mantissa of each first-precision intermediate result to obtain the third-precision intermediate computation result corresponding to each combination of second-precision floating-point numbers. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, there are no additional elements. At Step 2B, the re are no additional elements , either alone or in combination, that amount to significantly more than the recited judicial exception. For these reasons, claim 1 8 does not amount to significantly more than the abstract idea. Claim 1 8 is not eligible. Regarding claim 19, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites floating-number decomposition into a plurality of lower precision values and carrying out operations through the use of combinations of the lower precision values. Below are the limitations of claim 19 that recite an abstract idea under mathematical concepts: decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second - precision floating-point number being lower than a first precision of the first-precision floating-point number; determining various combinations comprising two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination. All limitations as indicated describe “mathematical concepts”. At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include: An electronic device A memory at least one processor obtaining a plurality of to-be-computed first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination . These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application. There are insignificant extra-solution activit ies that must be made of note as shown below: obtaining a plurality of to-be-computed first-precision floating-point numbers ( data gathering falling under insignificant extra-solution activity ) ; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination ( outputting of data or a result is well-known in the art ) . At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 9 does not amount to significantly more than the abstract idea. In regards to the insignificant extra-solution activity found in this limitation “ obtaining a plurality of to-be-computed first-precision floating-point numbers ”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well ‐ understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i . Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE , Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. In regards to the insignificant extra-solution activity found in this limitation “ inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination ”, this action describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer ( Patterson : Pg. 15 Section 1.3 Lines 2-4) . This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more. Claim 1 9 is not eligible. Regarding claim 20, at Step 1, the claim is directed to a statutory category of invention (m achine ). At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea . Claim 20, dependent upon claim 19, does not integrate the limitations of claim 19 i.e., abstract idea into a practical application in any way. At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include: An arithmetic logic unit These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system , more specifically the technological environment of an arithmetic logic unit . For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application. At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 20 does not amount to significantly more than the abstract idea. Claim 20 is not eligible. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim s 14 -15, and 17-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 14 recites the limitation “ a computation result ” on line 6 . It is unclear if this mention of “a computation result” is the same as the computation result as recited in claim 13. Appropriate correction is required. For examination purposes the computation result of claim 14 will be construed to be the computation result of claim 14. Because claims 15 and 17-18 depend upon claim 14, claims 15 and 17-18 are also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-2, 13, 16, and 19-20 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Henry et al. (US 2019/0042244 A1), included in the IDS filed 01/30/2023 (hereinafter “Henry”). Regarding claim 1, Henry teaches: An arithmetic logic unit in a processor, the arithmetic logic unit comprising: a floating-point number decomposition circuit configured to (Henry: Abstract processor with decoding circuitry for decomposition of floating-point operands) : decompose each input to-be-computed first-precision floating-point number into at least two second-precision floating-point numbers (Henry: Abstract, operands being decomposed into plurality of lower precision values; Fig. 4 shows operands A and B being decomposed into a plurality of lower precision operands) , a second precision of the second precision floating-point number being lower than a first precision of the first-precision floating-point number (Henry: Fig. 4 A and B operands go from first precision 32 to second precision 16 bits, which is lower than 32 bits) ; a second-precision multiplier configured to (Henry: m ultiplication of second precision values as shown in Fig. 4 Element 422, 424, 426, 428; ¶ 0064 discusses multiplier accumulator circuits, where the 16 bit combinations are multiplied using the multipliers of these MAC circuits, and then result is reconstructed at the accumulator with result of first precision , which is also shown in Fig. 4 with multiplication and summation of combinations to result in first precision) : receive a combination comprising two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers (Henry: Fig. 4 shows different combinations of the lower precision decomposed operands 422 424 426 428 ) ; perform a multiplication operation on the second-precision floating-point numbers in each combination (Henry: Fig. 4 shows different combinations of the lower precision decomposed operands 422 424 426 428 with multiplications on each of the combinations ) ; and output an intermediate computation result corresponding to each combination (Henry: outputting values from operations of 422 424 426 428 ) ; and an accumulator configured to (Henry: accumulation of values occurs through summation operation of all combinations, resulting in first precision computation result Fig. 4 element 432 and further discussed in ¶ 0094 ) : perform an operation to obtain a computation result for the plurality of to-be - computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination (Henry: accumulation of values occurs through summation operation of all combinations, resulting in first precision computation result Fig. 4 element 432 and further discussed in ¶ 0094, resulting in computation result ) . Regarding claim 2, Henry teaches: The arithmetic logic unit according to claim 1, wherein the operation is a summation operation (Henry: at Fig. 4 element 432 reconstructing of end result (accumulator) occurs through a summation operation as discussed in ¶ 0094) . Claim 13 recites the method practiced by the apparatus of claim 1 and is therefore rejected for the same reasons therein. Regarding claim 16, Henry teaches: The method according to claim 13, wherein the intermediate computation result is a first-precision intermediate computation result, and the computation result is a first-precision computation result (Henry: ¶ 0094 multiplication operations of 422-428 i.e., intermediate computation result can already be in the first precision, end computation result is in the first precision FP32) . Claim 19 recites an electronic device with a memory storing instructions to be executed by a processor, the instructions are for the method practiced by the apparatus of claim 1, and is therefore rejected for the same reasons therein. Henry additionally teaches a memory in communication with at least one processor in order to execute instructions for the disclosed algorithm (Henry: ¶ 0150 - ¶ 0151). Regarding claim 20, Henry teaches : The electronic device of claim 19, wherein the processor comprises an arithmetic logic unit (Henry: ¶ 0145 processor may be a general purpose processor, and as is known in the art all genera l purpose processors have an ALU with logic gates for arithmetic operations and computations in general ) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Clai m 12 is rejected under 35 U.S.C. 103 as being unpatentable over Henry further in view of Fleming, Jr. et al. (US 2019/0303263 A1) (hereinafter “Fleming”). While Henry teaches the arithmetic logic unit according to claim 1 as well as a second precision multiplier (Henry: m ultiplication of second precision values as shown in Fig. 4 Element 422, 424, 426, 428; ¶ 0064 discusses multiplier accumulator circuits, where the 16 bit combinations are multiplied using the multipliers of these MAC circuits, and then result is reconstructed at the accumulator with result of first precision , which is also shown in Fig. 4 with multiplication and summation of combinations to result in first precision ) and groups of to-be-computed-precision floating point numbers (Henry: Fig. 4 shows different combinations i.e., groups of the lower precision decomposed operands 422 424 426 428 ) , and performing multiplication on each group of second-precision floating point numbers (Henry: Fig. 4 shows different combinations of the lower precision decomposed operands 422 424 426 428 with multiplications on each of the combinations ) , as well as inputting an intermediate computation result for each group to an accumulator and a summation by an accumulator carried out on all the groups outputting a computation result (Henry: accumulations of values of all combinations i.e., groups through a summation operation results in a first precision computation result as shown in Fig. 4 element 432 and discussed in ¶ 0094) , Henry does not explicitly teach a computation mode switching circuit for invalidating circuits when set to a second-precision mode. However, Fleming teaches sections of circuitry that disabled when they are unused due to a lower precision of operands i.e., mode of operation is already at a second or lower precision (Fleming: ¶ 0289). It would be obvious to combine the deactivating of circuits based on precisions of operands as taught by Fleming with the arithmetic logic unit as taught by Henry as both teachings are directed towards carrying out of operations on lower precision operands. One with ordinary skill in the art would be motivated to combine the teachings because this would allow the reduction in energy consumption (Fleming: ¶ 0289). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Henry further in view of Langhammer (US 2018/0321909 A1) included in the IDS filed 01/28/2023 (hereinafter “Langhammer”). Regarding claim 14, Henry teaches: The method according to claim 13, after the decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, further comp risin g: the determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination (Henry: Fig. 4 shows different combinations of the lower precision decomposed operands 422, 424, 426, 428, each of the combinations are multiplied to obtain intermediate computation results) comprises: performing a summation operation on the intermediate computation results corresponding to all the combinations to obtain the computation result for the plurality of first - precision floating-point numbers (Henry: accumulation of values occurs through summation operation of all combinations, resulting in first precision computation result Fig. 4 element 432 and further discussed in ¶ 0094, with output as computation result in first precision) . Henry does not explicitly teach: determining an exponent bias value corresponding to each second-precision floating-point number; and adjusting, based on the exponent bias value corresponding to the second-precision floating - point number in each combination, an exponent of the intermediate computation result corresponding to each combination, to obtain an adjusted intermediate computation result . However, Langhammer teaches exponent handling circuitry that adjust respective exponents of floating-point operands based on an adjustable bias based on the precisions of the operands (Langhammer: Claim 13). It would be obvious to combine the adjusting by an exponent bias based on precisions as taught by Langhammer with the method as taught by Henry as both teachings are directed towards operations on lower precision operands. One with ordinary skill in the art would be motivated to combine the teachi