Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 34-37 and 40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hayashi et al. (US PG. Pub. 2013/0279134).
Regarding claim 34 – Hayashi teaches a system (fig. 2A-2C) comprising: a printed circuit board (PCB) (fig. 2B, 100 [paragraph 0026] Hayashi states, “printed wiring board 100”) including signal lines (135 & 136 [0053] Hayashi states, “signal wirings 135 and 136”) for a common interconnect link (see figs. 2A-2B), the lines including: a plurality of signal traces (111 & 112 [paragraph 0034] Hayashi states, “a first signal wiring pattern 111 and a second signal wiring pattern 112”); and a plurality of heterogeneous pad stacks (figure 2B shows the pads of 135 being different than the pads of 136) coupled to the plurality of traces (111 & 112), wherein the plurality of heterogeneous pad stacks each include different pad configurations ([paragraph 0041] Hayashi states, “The pad 141 is a conductor that surrounds the via 131 and the width (diameter) thereof is larger than the wiring widths of the first to fourth signal wiring patterns 111 to 114”) to provide different signal phase velocities (The structure shown by Hayashi will have the function as claimed).
Additionally please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “to provide different signal phase velocities“ which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997).
Regarding claim 35 - Hayashi teaches the system of claim 34, wherein the different pad configurations (figs. 2A-2C, see pads with 135 & 136) result from differently spaced apart pad dimensions (pad 141 within 135 is differently spaced than the pads on top and bottom of 136).
Regarding claim 36 – Hayashi teaches the system of claim 34, wherein the different pad configurations (figs. 2A-2C, see pads with 135 & 136) result from different pad area dimensions (pad area dimensions of pad 141 is different than that of the pads shown outer surface).
Regarding claim 37 – Hayashi teaches the system of claim 34, wherein the pads (figs. 2A-2C, pads shown on upper and lower surface and pad 141) have a circular shape (figure 2A shows the pads being in a circular shape), a square shape, a rectangular shape, a sawtooth shape, or combinations thereof.
Regarding claim 40 – Hayashi teaches the system of claim 34, wherein the heterogeneous pad stacks (figure 2B shows the pads of 135 being different than the pads of 136) comprise vias (132 & 131) including a through-hole via (figure 2B shows the vias 131 & 132 passing through the substrate 105) or a partial through-hole via.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-24, 26-27, 29, 30 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dsilva et al. (US Patent 11324119) in view of Hayashi et al.
Regarding claim 21 – Dsilva teaches an interconnect (fig. 2A-2C & fig. 7A-7C) comprising: a plurality of links (see links connected to vias 22A, 230A, 230B, 220B), wherein a first set of links (230A & 230B [column 4 line 33] Dsilva states, “two VIA barrels 230A and 230B”) from the plurality of links includes a plurality of pad stacks (270A-270H [column 4 lines 25-26] Dsilva states, “pads 270A, 270B, 270C, 270D, 270E, 270F, 270G, and 270H”), the first set of links (230A & 230B) to communicate signals ([column 3 & 1 lines 19-20 & 32] Dsilva states, “differential VIA includes VIA barrels 230A and 230B…The signal carried on the differential VIA”) and a second set of links (220A & 220B) from the plurality of links to provide a return path ([column 3 lines 34-35] Dsilva states, “ground connections 220A-220B”).
Dsilva fails to teach wherein a first set of links from the plurality of links includes a plurality of heterogeneous pad stacks; wherein two or more of the heterogeneous pad stacks comprise pads with differently sized diameters to provide a heterogenous phase delay amongst the plurality of links in the interconnect.
Hayashi teaches an interconnect (figs. 2A-2C) wherein a first set of links (135 & 136 [paragraph 0038] Hayashi states, “first signal wiring 135…second signal wiring 136”) from the plurality of links includes a plurality of heterogeneous pad stacks (figure 2B shows the pads of link 135 being different than the pads of link 136); wherein two or more of the heterogeneous pad stacks (see pad stacks within link 135 & 136) comprise pads (see smaller diameter pads in link 136 than the pad 141 in link 135) with differently sized diameters ([paragraph 0041] Hayashi states, “The pad 141 is a conductor that surrounds the via 131 and the width (diameter) thereof is larger than the wiring widths of the first to fourth signal wiring patterns 111 to 114”) to provide a heterogenous phase delay amongst the plurality of links in the interconnect (The claimed structure will have the function as claimed).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a first set of links having a pad stack and a second set of links providing a return path as taught by Dsilva with the plurality of heterogenous pad stacks having pads with different sizes as taught by Hayashi because Hayashi states, “the first pad includes the opposed portion which is opposed to the second electrode pad, and thus, capacitive coupling between the signal wiring including the first via and the signal wiring including the second via can be increased. Thus, a noise component due to inductive coupling and a noise component due to the capacitive coupling can be cancelled, out with each other, and, as a result, crosstalk noise caused between the signal wirings can be reduced.” [paragraph 0011].
Additionally please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “to provide a heterogenous phase delay amongst the plurality of links in the interconnect“ which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997)
Regarding claim 22 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the pads (Hayashi; figs. 2A-2C, see pads connected to links 135 & 136) of the two or more pad stacks are dispersed non-uniformly along an associated via (figure 2B shows the pad 141 of link 135 being non-uniform to that of pads of link 136).
Regarding claim 23 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the pads (Dsilva; fig. 2, 270A-270H) of the two or more pad stacks are dispersed uniformly along an associated via (figure 2 shows the pads 27A, 270C, 270E and 270G being aligned with that of pads 270B, 270D, 270F and 270H).
Regarding claim 24 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the pads (Hayashi; figs. 2A-2C, pads shown on upper and lower surface and pad 141) have a circular shape (figure 2A shows the pads being in a circular shape), a square shape, a rectangular shape, a sawtooth shape, or combinations thereof.
Regarding claim 26 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the pads (Dsilva; fig. 2, 270C, 270D, 270E & 270F) are dispersed within one or more layers of a multi-layer Printed Circuit Board (PCB) at one or more transition points between two adjoining layers of the multi-layer PCB (figure 2 shows the pads being within the multi-layer PCB between insulation layers and appears to meet the claimed limitation).
Regarding claim 27 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the heterogeneous pad stacks (Hayashi; figs. 2A-2C, pads shown on upper and lower surface and pad 141) comprise a through-hole via (see through-hole via shown in figure 2B-2C) or a partial through-hole via.
Regarding claim 29 – Dsilva in view of Hayashi teach the interconnect of claim 27, wherein the through-hole via (Dsilva; fig. 2, 230A, 230B) is plated with a conductive material ([column 1 lines 21-23] Dsilva states, “The holes may be plated with a conductive material (e.g., copper) that electrically connects the pads”).
Regarding claim 30 – Dsilva in view of Hayashi teach the interconnect of claim 29, wherein the conductive material is one of copper ([column 1 lines 21-23] Dsilva states, “The holes may be plated with a conductive material (e.g., copper) that electrically connects the pads”), nickel, and aluminum.
Regarding claim 33 – Dsilva in view of Hayashi teach the interconnect of claim 21, wherein the return path (Dsilva; fig. 2, return path shown within ground connections 220A-220B) comprises a path to ground ([column 3 lines 15-16] Dsilva states, “ground connections 220A and 220B”).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dsilva et al. in view of Hayashi et al. as applied to claim 21 above and further in view of Brown et al. (US PG. Pub. 2016/0135288).
Regarding claim 25 – Dsilva in view of Hayashi teaches the interconnect of claim 21, but fails to teach wherein the pads have differing thicknesses.
Brown teaches wherein the pads (fig. 3, 328 & 326 [paragraph 0029] Brown states, “anchor pads 326 and 328”) have differing thicknesses ([paragraphs 0023 & 0032] Brown states, “This technique can minimally involve one additional pad above the target layer, but could also include multiple pads of lesser thickness or even be targeted to layers of greater thickness…the layer on which the anchor pad(s) is added may be selectively biased to layers that have greater copper weight (thickness)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a first set of links with heterogeneous pad stacks and a second set of links that provide a return path as taught by Dsilva in view of Hayashi with the pads having a differing thickness as taught by Brown because Brown states, “These pads share the expansion stresses that would normally be born solely by the signal pad, thereby greatly decreasing the likelihood that shear stresses would exceed shear strength of the connection between an internal signal pad and a PTH via barrel” [paragraph 0023].
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dsilva et al. in view of Hayashi et al. as applied to claim 27, further in view of Gisin et al. (US PG. Pub. 2004/0176938).
Regarding claim 28 – Dsilva in view of Hayashi teach the interconnect of claim 27, but fails to explicitly teach wherein partial through-hole via comprises a blind via or buried via.
Gisin teaches an interconnect (fig. 1) having a partial through-hole via (14 or 16 [paragraph 0026] Gisin states, “Blind and buried vias 14”) comprises a blind via (14) or buried via (16).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a through-hole via as taught by Dsilva in view of Hayashi with the partial through-hole via comprises a blind or buried via as taught by Gisin because blind and buried vias increase circuit density and take up less board real-estate than a through via.
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dsilva et al. in view of Hayashi et al. as applied to claim 21 above, and further in view of Fu (US Patent 10561017).
Regarding claim 31 – Dsilva in view of Hayashi teach the interconnect of claim 21, further comprising a PCB (Dsilva; fig. 2 [column 3 lines 5-7] Dsilva states, “The multi-layer circuit may be a silicon die package, a printed circuit board (PCB), or another multi-layer circuit”) to mechanically couple the plurality of links (figure 2 shows the plurality of links within the PCB).
Dsilva in view of Hayashi fail to teach wherein the PCB is to be surface finished with Hot Air Solder Leveling (HASL) finish, lead free HASL finish, or Electroless Nickel Immersion Gold (ENIG) finish.
Fu teaches wherein a PCB (fig. 10 [title] Fu states, “circuit board”) is to be surface finished with Hot Air Solder Leveling (HASL) finish, lead free HASL finish, or Electroless Nickel Immersion Gold (ENIG) finish (column 4 lines 40-44] Fu states, “the surface treating layer 70 is formed on the exposed of the portion of the first wiring layer 20 and the exposed portion of the outermost second wiring layer 45 by Electroless Nickel Immersion Gold (ENIG)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board that mechanically couples to the links as taught by Dsilva in view of Hayashi with the PCB is surface finished with electroless Nickel Immersion Gold as taught by Fu because ENIG is known to have excellent solder-ability, corrosion resistance, and advantageous in fine-pitch circuitry.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dsilva et al. in view of Hayashi et al. as applied to claim 21 above and further in view of Audet et al. (US PG. Pub. 2007/0023913)
Regarding claim 32 – Dsilva in view of Hayashi teach the interconnect of claim 21, but fails to teach wherein the different pad diameters are within 20% to 30% in diameter of one another.
Audet teaches a pad stack (fig. 1) having pads (10 & 15 [paragraph 0014] Audet states, “circular FP cap 10 comprises a diameter of at least 300 .mu.m…via lands 15 comprises a substantially circular shape having a diameter of at least 400 .mu.m”) with different sized diameters wherein the different pad diameters are within 20% to 30% in diameter of one another (pad 10 selected to be 350um, the pad 15 being over 400um is considered to be 20-30% larger than that of pad 10).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a two heterogeneous pad stacks with pads having different diameters as taught by Dsilva with the different pad diameters being within 20-30% in diameter of one another as taught by Audet because Audet states, “As an unexpected result, it was experimentally determined that increasing the size of the via land 15 reduces the deformation, therefore imparting mechanical robustness and reducing the impact of mechanical handling on via stack 20 fails…It is also determined that increasing the diameter of the via lands 15 in the middle of the via stack 20 offers a greater improvement than increasing the RFP land 10” [paragraph 0019]. Having the pad sizing within the claimed range will improve the structural strength of the heterogeneous pad stack.
Claim(s) 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi et al. as applied to claim 34 above and further in view of Brown et al.
Regarding claim 38 –Hayashi teaches the system of claim 34, but fails to teach wherein the different pad configurations result from pads with different thicknesses.
Brown teaches wherein the different pad configurations (fig. 3, 328 & 326 [paragraph 0029] Brown states, “anchor pads 326 and 328”) result from pads with different thicknesses ([paragraphs 0023 & 0032] Brown states, “This technique can minimally involve one additional pad above the target layer, but could also include multiple pads of lesser thickness or even be targeted to layers of greater thickness…the layer on which the anchor pad(s) is added may be selectively biased to layers that have greater copper weight (thickness)”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify different pad configurations as taught by Hayashi with the different pad configurations comprises having differing thickness as taught by Brown because Brown states, “These pads share the expansion stresses that would normally be born solely by the signal pad, thereby greatly decreasing the likelihood that shear stresses would exceed shear strength of the connection between an internal signal pad and a PTH via barrel” [paragraph 0023].
Claim(s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi et al. in view of Dsilva et al.
Regarding claim 39 – Hayashi teaches the system of claim 34, wherein the PCB comprises a multi-layer PCB ([paragraph 0032] Hayashi states, “The printed wiring board 100 of the semiconductor package 300 is a multilayer printed wiring board”).
Hayashi fails to explicitly teach wherein the pads are dispersed within one or more layers of the multi-layer PCB at one or more transition points between two adjoining layers of the multi-layer PCB.
Dsilva teaches wherein the pads (fig. 2, 270C, 270D, 270E & 270F [column 3 lines 21-22] Dsilva states, “pads 270A, 270B, 270C, 270D, 270E, 270F, 270G, and 270H”) are dispersed within one or more layers of the multi-layer PCB (see inner pads 270C, 270D, 270E & 270F) at one or more transition points between two adjoining layers of the multi-layer PCB (figure 2 shows the inner pads being located at positions between insulation layers and appears to meet the claimed limitation).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multi-layer PCB having pads therein as taught by Hayashi with the pads being located at transition points between two adjoining layers of the multi-layer PCB as taught by Dsilva because this allows the pads/layers to be stacked in an additive manner that can have fast processing and is commonly done when forming multilayer PCBs.
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ben Artsi et al. (US PG. Pub. 2024/0008180) discloses a printed circuit board via structure with reduced insertion loss distortion.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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