CTNF 17/855,680 CTNF 86959 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/26/2026 has been entered. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 34-35, 37-38 and 40 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Brown et al. (US PG. Pub. 2016/0135288) Regarding claim 34 – Brown teaches a system (fig. 3) comprising: a printed circuit board (PCB) (300 [paragraph 0027] Brown states, “multilayer PCB 300”) including signal lines (signal lines connected to signal vias 308 & 320 [paragraph 0027 & 0029] Brown states, “signal pad 308…signal pad 322”) for a common interconnect link, the lines including: a plurality of signal traces (see signal trace connected to pads 308 & 322 on upper surface of PCB 300); and a plurality of heterogeneous pad stacks (left pad stack 304 & middle pad stack 316) coupled to the plurality of traces (see fig. 3), wherein the plurality of heterogeneous pad stacks (304 & 316) include different pad configurations (one dummy pad 314 of 304 and two dummy pads 326 & 328 of 316) to provide different signal phase velocities (structure shown in figure 3 will have this property/function), the different pad configurations including first pad stacks (304) with a first non-zero number of dummy pads (314 [paragraph 0028] Brown states, “Anchor pad 314 is an (electrically) non-functional pad”) and second pad stacks (326 & 328 [paragraph 0029] Brown states, “anchor pads 326 and 328”) with a second non-zero number of dummy pads, the first and second non-zero numbers being different (figure 3 shows the first pad stack 304 having one dummy pad 314 and the second pad stack 316 having two dummy pads 326 & 328). Additionally please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “ to provide different signal phase velocities “ which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Regarding claim 35 - Brown teaches the system of claim 34, wherein the different pad configurations (fig. 3, see pads 314, 326 & 328) result from differently spaced apart pad dimensions (pad 328 is shown to be “differently spaced” than the pad 314). Regarding claim 37 – Brown teaches the system of claim 34, wherein the dummy pads (fig. 3, 314, 326 & 328) have a circular shape (figure 3 shows the pads being in a circular shape), a square shape, a rectangular shape, a sawtooth shape, or combinations thereof. Regarding claim 38 –Brown teaches the system of claim 34, but fails to teach wherein the different pad configurations result from dummy pads (fig. 3, 314, 326 & 328) with different thicknesses ([paragraphs 0023 & 0032] Brown states, “This technique can minimally involve one additional pad above the target layer, but could also include multiple pads of lesser thickness or even be targeted to layers of greater thickness…the layer on which the anchor pad(s) is added may be selectively biased to layers that have greater copper weight (thickness)”). Regarding claim 40 – Brown teaches the system of claim 34, wherein the heterogeneous pad stacks (figure 3 shows the pads of 326 & 328 being different than the pads of 314) comprise vias (304 & 316 [paragraph 0027 & 0029] Brown states, “PTH via 304…PTH via 316”) including a through-hole via (306 & 318 [paragraph 0028] Brown states, “conductive barrel 306 of via 304”) or a partial through-hole via . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 21-22, 24, 25, 27, 29, 30 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Kushta (US PG. Pub. 2010/0282503) . Regarding claim 21 – Brown teaches an interconnect (fig. 3) comprising: a plurality of links (see three links 304, 316 & 330) coupled to a multi-layer printed circuit board (PCB) (300 [paragraph 0027] Brown states, “multilayer PCB 300”), wherein a first set of links (304 & 316) from the plurality of links includes a plurality of heterogeneous pad stacks (figure 3 shows the first pad stack 304 having one dummy pad 314 and the second pad stack 316 having two dummy pads 326 & 328), the first set of links (304 & 316) to communicate signals ([paragraph 0028 & 0029] Brown states, “signal pad 308…signal pad 322”); and wherein two or more of the heterogeneous pad stacks comprise different non-zero numbers of dummy pads (314 and 326/328 [paragraph 0028 & 0029] Brown states, “Anchor pad 314 is an (electrically) non-functional pad…anchor pads 326 and 328”) to provide a heterogenous phase delay amongst the plurality of links in the interconnect (structure shown in figure 3 will have this property/function). Brown fails to teach a second set of links from the plurality of links to provide a return path. Kushta teaches a second set of links (figs. 1A-1C, 102) from the plurality of links to provide a return path ([paragraph 0019] Kushta states, “signal via 101 is surrounded by ground vias 102”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a first set of links including a plurality of heterogeneous pad stack as taught by Brown with the inclusion of a second set of links that provide a return path as taught by Kushta because Kushta states, “the number of ground vias and the positions of them as well as the form and dimensions of the clearance hole 103 are important parameters to control the characteristic impedance in the signal via interconnection, in such a way to reduce a return loss from the signal via interconnection, as result from the whole interconnection disposed in the multi-layer substrate that leads to improving its electrical performance” [paragraph 0020]. Additionally please note that the claims are directed to apparatus which must be distinguished from the prior art in term of structure rather function [MPEP 2144]. Hence, the functional limitations “ to provide a heterogenous phase delay amongst the plurality of links in the interconnect “ which are narrative in form have not been given any patentable weight. In order to be given patentable weight, a functional recitation must be supported by recitation in the claim of sufficient structure to warrant the presence of the functional language. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Regarding claim 22 – Brown in view of Kushta teach The interconnect of claim 21, wherein dummy pads (Brown; fig. 3, 314, 326/328) of the two or more pad stacks (304 & 316) that have two or more dummy pads (326 & 328) are dispersed non-uniformly along an associated via (318; figure 3 shows the dummy pads 326 & 328 being located on the lower part of the via 318 and are considered “non-uniformly” in relation to the via). Regarding claim 24 – Brown in view of Kushta teach the system of claim 21, wherein the dummy pads (fig. 3, 314, 326 & 328) have a circular shape (figure 3 shows the pads being in a circular shape), a square shape, a rectangular shape, a sawtooth shape, or combinations thereof. Regarding claim 25 – Brown in view of Kushta teach the interconnect of claim 21, but wherein the dummy pads (Brown; fig. 3, 328 & 326 [paragraph 0029] Brown states, “anchor pads 326 and 328”) have differing thicknesses ([paragraphs 0023 & 0032] Brown states, “This technique can minimally involve one additional pad above the target layer, but could also include multiple pads of lesser thickness or even be targeted to layers of greater thickness…the layer on which the anchor pad(s) is added may be selectively biased to layers that have greater copper weight (thickness)”). Regarding claim 27 – Brown in view of Kushta teach the system of claim 21, wherein the heterogeneous pad stacks (Brown; figure 3 shows the pads of 326 & 328 being different than the pads of 314) comprise a through-hole via (304 & 316 [paragraph 0027 & 0029] Brown states, “PTH via 304…PTH via 316”) or a partial through-hole via. Regarding claim 29 – Brown in view of Kushta teach the interconnect of claim 27, wherein the through-hole via (Brown; fig. 3, 304 & 316) is plated with a conductive material ([paragraph 0027 & 0029] Brown states, “PTH via 304…PTH via 316”). Regarding claim 30 – Brown in view of Kushta teach the interconnect of claim 29, wherein the conductive material is one of copper, nickel, and aluminum. Official Notice is taken that copper is a conventional or well-known feature for forming conductive through holes. Therefore, it would have been obvious to a person having ordinary skill in the art to use copper on the through holes of Brown because copper is known to be highly conductive, corrosion resistant and excellent thermal properties and commonly used in this fashion. Regarding claim 33 – Brown in view of Kushta teach the interconnect of claim 21, wherein the return path (Kushta; return path including ground vias 102) comprises a path to ground ([paragraph 0019] Kushta states, “signal via 101 is surrounded by ground vias 102”) . 07-22-aia AIA Claim (s) 23 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Kushta as applied to claim 21 above, and further in view of Noujeim et al. (US PG. Pub. 2023/0319985) . Regarding claim 23 – Brown in view of Kushta teach the interconnect of claim 21, wherein dummy pads (Brown; fig. 3, 314 & 326/328) of the two or more pad stacks (304 & 316) but fail to teach having two or more dummy pads are dispersed uniformly along an associated via. Noujeim teaches have two or more dummy pads (fig. 5, 504c, 506b, 504b & 506a [paragraph 0042] Noujeim states, “loading pads 504a-c…loading pads 506a-b”) are dispersed uniformly along an associated via (502 [paragraph 0042] Noujeim states, “signal via 502”; figure 5 shows the dummy pads being located uniformly along the via 502). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multi-layer PCB having two heterogenous pad stacks with different amounts of dummy pads thereon as taught by Brown in view of Kushta wherein the dummy pads are dispersed uniformly along an associated via as taught by Noujeim because Noujeim states, “uch loading pads formed with the vias may facilitate impedance continuity so as to reduce likelihood of signal distortion during transmission…the loading pads formed around the signal vias, or optionally some ground vias, may reduce impedance discontinuity and thus reduce the likelihood of signal distortion” [paragraph 0004 & 0046]. Regarding claim 26 – Brown in view of Kushta teach the interconnect of claim 21, wherein the PCB comprises a multi-layer PCB (Brown; fig. 3, 300 [paragraph 0027] Brown states, “multilayer PCB 300”) and the pads being dummy pads (314, 326 & 328). Brown in view of Kushta fail to explicitly teach wherein the dummy pads are dispersed within one or more layers of the multi-layer PCB at one or more transition points between two adjoining layers of the multi-layer PCB. Noujeim teaches wherein the dummy pads (fig. 1, 165 [paragraph 0023] Noujeim states, “loading pads 165a-d”) are dispersed within one or more layers of the multi-layer PCB (see multi-layer PCB 100 shown in figure 1) at one or more transition points between two adjoining layers of the multi-layer PCB (figure 2 shows the inner pads being located at positions between insulation layers and appears to meet the claimed limitation). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multi-layer PCB having pads therein as taught by Brown in view of Kushta with the pads being located at transition points between two adjoining layers of the multi-layer PCB as taught by Noujeim because this allows the pads/layers to be stacked in an additive manner that can have fast processing and is commonly done when forming multilayer PCBs . 07-21-aia AIA Claim (s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Kushta as applied to claim 27, further in view of Gisin et al. (US PG. Pub. 2004/0176938) . Regarding claim 28 – Brown in view of Kushta teach the interconnect of claim 27, but fails to explicitly teach wherein partial through-hole via comprises a blind via or buried via. Gisin teaches an interconnect (fig. 1) having a partial through-hole via (14 or 16 [paragraph 0026] Gisin states, “Blind and buried vias 14”) comprises a blind via (14) or buried via (16). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a through-hole via as taught by Brown in view of Kushta with the partial through-hole via comprises a blind or buried via as taught by Gisin because blind and buried vias increase circuit density and take up less board real-estate than a through via . 07-22-aia AIA Claim (s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Kushta as applied to claim 21 above, and further in view of Fu (US Patent 10561017) . Regarding claim 31 – Brown in view of Kushta teach the interconnect of claim 21, but fails to teach wherein the PCB is to be surface finished with Hot Air Solder Leveling (HASL) finish, lead free HASL finish, or Electroless Nickel Immersion Gold (ENIG) finish. Fu teaches wherein a PCB (fig. 10 [title] Fu states, “circuit board”) is to be surface finished with Hot Air Solder Leveling (HASL) finish, lead free HASL finish, or Electroless Nickel Immersion Gold (ENIG) finish (column 4 lines 40-44] Fu states, “the surface treating layer 70 is formed on the exposed of the portion of the first wiring layer 20 and the exposed portion of the outermost second wiring layer 45 by Electroless Nickel Immersion Gold (ENIG)”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit board that mechanically couples to the links as taught by Brown in view of Kushta with the PCB is surface finished with electroless Nickel Immersion Gold as taught by Fu because ENIG is known to have excellent solder-ability, corrosion resistance, and advantageous in fine-pitch circuitry . 07-22-aia AIA Claim (s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Kushta as applied to claim 21 above and further in view of Audet et al. (US PG. Pub. 2007/0023913) Regarding claim 32 – Brown in view of Kushta teach the interconnect of claim 21, but fails to teach wherein the dummy pads include different pad diameters within 20% to 30% in diameter of one another. Audet teaches a pad stack (fig. 1) having pads (10 & 15 [paragraph 0014] Audet states, “circular FP cap 10 comprises a diameter of at least 300 .mu.m…via lands 15 comprises a substantially circular shape having a diameter of at least 400 .mu.m”) with different sized diameters wherein the different pad diameters are within 20% to 30% in diameter of one another (pad 10 selected to be 350um, the pad 15 being over 400um is considered to be 20-30% larger than that of pad 10). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the interconnect having a two heterogeneous pad stacks with dummy pads as taught by Brown in view of Kushta with the different pad diameters being within 20-30% in diameter of one another as taught by Audet because Audet states, “As an unexpected result, it was experimentally determined that increasing the size of the via land 15 reduces the deformation, therefore imparting mechanical robustness and reducing the impact of mechanical handling on via stack 20 fails…It is also determined that increasing the diameter of the via lands 15 in the middle of the via stack 20 offers a greater improvement than increasing the RFP land 10” [paragraph 0019]. Having the pad sizing within the claimed range will improve the structural strength of the heterogeneous pad stack . 07-21-aia AIA Claim (s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. applied to claim 34, and further in view of Kushta . Regarding claim 36 – Brown teaches the system of claim 34, but fails to teach wherein the different pad configurations result from different pad area dimensions. Kushta teaches different pad configurations (fig. 1A-1D, pad configurations of dummy pad 108) result from different pad area dimensions ([paragraph 0024] Kushta states, “The form and dimensions of the dummy pad 108 can be obtained as providing the characteristic impedance of the transmission line segment within a predetermined value”). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the system having a plurality of heterogenous pad stacks with differing numbers of dummy pads as taught by Brown with the different pad configurations resulting from different pad area dimensions as taught by Kushta because Kushta states, “The form and dimensions of the dummy pad 108 can be obtained as providing the characteristic impedance of the transmission line segment within a predetermined value” [paragraph 0024] . 07-21-aia AIA Claim (s) 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brown et al. in view of Noujeim et al . Regarding claim 39 – Brown teaches the system of claim 34, wherein the PCB comprises a multi-layer PCB (Brown; fig. 3, 300 [paragraph 0027] Brown states, “multilayer PCB 300”) and the pads being dummy pads (314, 326 & 328). Brown fails to explicitly teach wherein the dummy pads are dispersed within one or more layers of the multi-layer PCB at one or more transition points between two adjoining layers of the multi-layer PCB. Noujeim teaches wherein the dummy pads (fig. 1, 165 [paragraph 0023] Noujeim states, “loading pads 165a-d”) are dispersed within one or more layers of the multi-layer PCB (see multi-layer PCB 100 shown in figure 1) at one or more transition points between two adjoining layers of the multi-layer PCB (figure 2 shows the inner pads being located at positions between insulation layers and appears to meet the claimed limitation). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multi-layer PCB having pads therein as taught by Brown in view of Kushta with the pads being located at transition points between two adjoining layers of the multi-layer PCB as taught by Noujeim because this allows the pads/layers to be stacked in an additive manner that can have fast processing and is commonly done when forming multilayer PCBs . Response to Arguments Applicant’s arguments with respect to claim(s) 21-40 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Becker et al. (US PG. Pub. 2018/0228019) discloses method for impedance compensation in printed circuit board Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/Primary Examiner, Art Unit 2847 Application/Control Number: 17/855,680 Page 2 Art Unit: 2847 Application/Control Number: 17/855,680 Page 3 Art Unit: 2847
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