DETAILED ACTION
The Examiner acknowledges the applicant's submission of the amendment dated 11/13/2025.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252) and Das et al (US 9,691,505).
Regarding Claim 1, Kurihara teaches an apparatus, comprising:
a processor (memory error detection device 1 of Fig. 1, “the memory error determination device 1 itself is constituted as one processor unit,” Paragraph 0016) comprising:
a central processing unit having a plurality of processor cores (processor 16 of Fig. 1, which “includes, for example, one or a plurality of microprocessor units (MPUs)) [cores]”, Paragraph 0024);
a memory controller to read from and write to memory to which the processor is configured to be coupled (memory controller 11 reads and writes to memory 2, coupled to the processor as shown on Fig. 1, Paragraph 0018),
an embedded controller (interrupt controller 14, which “may execute the memory error determination processing,” Paragraph 0021, performed by “the error detection unit 22, the error position specification unit 23, and the determination unit 24,” Paragraph 0025); and,
a local memory coupled to the embedded controller (internal memory 13), and to store the read data error information in the local memory (internal memory 13 stores “data generated during the memory error determination processing,” Paragraph 0020).
However, the cited prior art does not explicitly teach:
register space to store read data error information;
the embedded controller to read the read data error information and store the read data error information in the local memory.
Fletcher teaches register space to store read data error information (“a status register 240…to identify a failed address [read error information],” Paragraph 0011);
a controller (event handler 250 of Fig. 2) to read the read data error information and store the read data error information in a local memory (data is read from the status register and stored in table 260/local memory, “An event handler 250 receives the PCE and the failed address from the status register 240 of the processor 210,” and “A table 260 [local memory] lists the failed address from which the memory error was detected.” Paragraph 0011).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the register space to quickly store information regarding a failed memory access, and to have the embedded controller and internal memory of the cited prior art perform the reading and storing of data error information as taught by Fletcher, in order to track failed addresses.
Further, the cited prior art does not explicitly teach the memory controller comprising error correction coding (ECC) circuitry to correct errors in data read from the memory.
Das teaches a memory controller comprising error correction coding (ECC) circuitry to correct errors in data read from the memory (“memory controller includes ECC manager 124 to manage error checking and correction in memory accesses of system 102,” C5 L4-19).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the ECC of Das in the cited prior art in order to more reliably read data.
Regarding Claim 3, the cited prior art teaches the apparatus of claim 1 wherein the embedded controller is able to read the read data error information in response to an interrupt generated from the read data error information (“the interrupt controller 14 executes the interrupt processing upon detection of an error that occurs in the memory 2,” interrupt processing including reading error information, Paragraph 0021 of Kurihara).
Regarding Claim 4, the cited prior art teaches the apparatus of claim 1 wherein the embedded controller is able to periodically read the read data error information (data is read periodically when an error is received via the interrupt of Paragraph 0021 of Kuriahara).
Claims 2, 5, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252), Das et al (US 9,691,505), and Elyasi et al (US 2022/0066683).
Regarding Claim 2, the cited prior art teaches the apparatus of claim 1, but does not explicitly teach wherein the embedded controller is able to store timestamps of consecutive ones of the read data errors in the local memory.
Elyasi teaches to store timestamps of consecutive ones of the read data errors in the local memory (see consecutive timestamps of Fig. 5 of Elyasi, Paragraph 0109).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 5, the cited prior art teaches the apparatus of claim 1 but does not explicitly teach wherein the read data error information comprises a timestamp of a read data error.
Elyasi teaches wherein the read data error information comprises a timestamp of a read data error (see timestamps of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 7, the cited prior art teaches the apparatus of claim 1, but does not explicitly teach wherein the embedded controller is to store a temperature associated with a read data error in the local memory.
Elyasi teaches to store a temperature associated with a read data error in the local memory (see temperature of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the temperature of Elyasi in the cited prior art in order to aid in error diagnosis.
Claims 8, 14, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252).
Regarding Claim 8, Kurihara teaches a machine readable storage medium containing program code that when processed by an embedded controller (interrupt controller 14, which “may execute the memory error determination processing,” Paragraph 0021, performed by “the error detection unit 22, the error position specification unit 23, and the determination unit 24,” Paragraph 0025) on a processor (memory error detection device 1 of Fig. 1, “the memory error determination device 1 itself is constituted as one processor unit,” Paragraph 0016) including a CPU having a plurality of processor cores (processor 16 of Fig. 1, which “includes, for example, one or a plurality of microprocessor units (MPUs)) [cores]”, Paragraph 0024), a memory controller to access memory coupled to the processor (memory controller 11 reads and writes to memory 2, coupled to the processor as shown on Fig. 1, Paragraph 0018), a and local memory (internal memory 13 of Fig. 1) causes the embedded controller to perform a method, comprising:
receiving an interrupt, the interrupt generated in response to a memory read error (“the interrupt controller 14 executes the interrupt processing upon detection of an error that occurs in the memory [read error],” Paragraph 0021, the interrupt received from the communication interface 15, Paragraph 0022);
writing the memory read error information in the local memory on the processor (internal memory 13 stores “data generated during the memory error determination processing,” Paragraph 0020).
However, the cited prior art does not teach a register space, reading memory read error information from the register space; and writing the memory read error information in the local memory on the processor.
Fletcher teaches a register space, reading memory read error information from the register space (“a status register 240…to identify a failed address [read error information],” Paragraph 0011); and writing the memory read error information in a local memory on the processor (data is read from the status register and stored in table 260/local memory, “An event handler 250 receives the PCE and the failed address from the status register 240 of the processor 210,” and “A table 260 [local memory] lists the failed address from which the memory error was detected.” Paragraph 0011).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the register space to quickly store information regarding a failed memory access, and to have the embedded controller and internal memory of the cited prior art perform the reading and storing of data error information as taught by Fletcher, in order to track failed addresses.
Regarding Claim 14, Kurihara teaches a computing system, comprising:
a memory module (memory 2 of Fig. 1); and
a processor (memory error detection device 1 of Fig. 1, “the memory error determination device 1 itself is constituted as one processor unit,” Paragraph 0016) comprising,
a plurality of processing cores (processor 16 of Fig. 1, which “includes, for example, one or a plurality of microprocessor units (MPUs)) [cores]”, Paragraph 0024), a memory controller (memory controller 11), an embedded controller (interrupt controller 14, which “may execute the memory error determination processing,” Paragraph 0021, performed by “the error detection unit 22, the error position specification unit 23, and the determination unit 24,” Paragraph 0025) and a local memory (internal memory 13 of Fig. 1), the memory controller coupled to the memory module (shown on Fig. 1), the memory controller to read from and write to the memory module (memory controller 11 reads and writes to memory 2, coupled to the processor as shown on Fig. 1, Paragraph 0018), and to store the read data error information in the local memory (internal memory 13 stores “data generated during the memory error determination processing,” Paragraph 0020).
However, the cited prior art does not teach a register space to store read data error information, or the embedded controller to read the read data error information and store the read data error information in the local memory.
Fletcher teaches a register space to store read data error information (“a status register 240…to identify a failed address [read data error information],” Paragraph 0011), and a controller (event handler 250 of Fig. 2) to read the read data error information and store the read data error information in the local memory (data is read from the status register and stored in table 260/local memory, “An event handler 250 receives the PCE and the failed address from the status register 240 of the processor 210,” and “A table 260 [local memory] lists the failed address from which the memory error was detected.” Paragraph 0011).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the register space to quickly store information regarding a failed memory access, and to have the embedded controller and internal memory of the cited prior art perform the reading and storing of data error information as taught by Fletcher, in order to track failed addresses.
Regarding Claim 16, the cited prior art teaches the computing system of claim 14 wherein the embedded controller is able to read the read data error information in response to an interrupt generated from the read data error information (“the interrupt controller 14 executes the interrupt processing upon detection of an error that occurs in the memory 2,” interrupt processing including reading error information, Paragraph 0021 of Kurihara).
Regarding Claim 17, the cited prior art teaches the computing system of claim 14 wherein the embedded controller is able to periodically read the read data error information (data is read periodically when an error is received via the interrupt of Paragraph 0021 of Kuriahara).
Claims 9, 11, 12, 15, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252) and Elyasi et al (US 2022/0066683).
Regarding Claim 9, the cited prior art teaches the machine readable storage medium of claim 8 but does not explicitly teach wherein the method further comprises the embedded controller writing a temperature associated with the memory read error in the memory.
Elyasi teaches to store a temperature associated with a read data error in the local memory (see temperature of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the temperature of Elyasi in the cited prior art in order to aid in error diagnosis.
Regarding Claim 11, the cited prior art teaches the machine readable storage medium of claim 8 but does not explicitly teach wherein the memory read error information comprises a timestamp of the memory read error.
Elyasi teaches to store timestamps of consecutive ones of the read data errors in the local memory (see consecutive timestamps of Fig. 5 of Elyasi, Paragraph 0109).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 12, the cited prior art teaches the machine readable storage medium of claim 11 but does not explicitly teach wherein the method further comprises writing a timestamp of a next memory read error in the memory.
Elyasi teaches writing a timestamp of a next memory read error in a memory
(see consecutive timestamps of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 15, the cited prior art teaches the computing system of claim 14 but does not explicitly teach wherein the embedded controller is able to store timestamps of consecutive ones of the read data errors in the local memory.
Elyasi teaches to store timestamps of consecutive ones of the read data errors in the local memory (see consecutive timestamps of Fig. 5 of Elyasi, Paragraph 0109).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 18, the cited prior art teaches the computing system of claim 14 but does not explicitly teach wherein the read data error information comprises a timestamp of a read data error.
Elyasi teaches wherein the read data error information comprises a timestamp of a read data error (see timestamps of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the timestamps of Elyasi in the cited prior art in order to track when errors occurred.
Regarding Claim 20, the cited prior art teaches the computing system of claim 14 but does not explicitly teach wherein the embedded controller is to store a temperature associated with a read data error in the local memory.
Elyasi teaches to store a temperature associated with a read data error in the local memory (see temperature of Fig. 5 of Elyasi).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the temperature of Elyasi in the cited prior art in order to aid in error diagnosis.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252) and Kelly et al (US 10,025,649).
Regarding Claim 13, the cited prior art teaches the machine readable storage medium of claim 8 but does not explicitly teach wherein the method further comprises the embedded controller causing the memory read error information to be transferred from the memory of the processor to a second memory that is external from the processor.
Kelly teaches causing memory read error information to be transferred from the memory of a processor to a second memory that is external from the processor (Fig. 2E, C11 L29-47).
It would have been obvious to a person having ordinary skill in the art to have implemented the transferring of Kelly using the memory and embedded controller of the cited prior art in order to aid in error diagnosis.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252), Das et al (US 9,691,505), and Liu et al (US 2023/0195381).
Regarding Claim 6, the cited prior art teaches the apparatus of claim 1 but does not explicitly teach wherein the embedded controller is to store a voltage associated with a read data error in the local memory.
Liu teaches to store a voltage associated with a read data error in the local memory (Paragraph 0061).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the voltage logging of Liu in the cited prior art in order to aid in error diagnosis.
Claims 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kurihara et al (US 2021/0103492) in view of Fletcher et al (US 2019/0034252) and Liu et al (US 2023/0195381).
Regarding Claim 10, the cited prior art teaches the machine readable storage medium of claim 8 but does not explicitly teach wherein the method further comprises the embedded controller writing a voltage associated with the memory read error in the memory.
Liu teaches to store a voltage associated with a read data error in the local memory (Paragraph 0061).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the voltage logging of Liu in the cited prior art in order to aid in error diagnosis.
Regarding Claim 19, the cited prior art teaches the computing system of claim 14 but does not explicitly teach wherein the embedded controller is to store a voltage associated with a read data error in the local memory.
Liu teaches to store a voltage associated with a read data error in the local memory (Paragraph 0061).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the voltage logging of Liu in the cited prior art in order to aid in error diagnosis.
ARGUMENTS CONCERNING NON-PRIOR ART REJECTIONS/OBJECTIONS
Rejections - USC 112
Applicant's arguments/amendments with respect to claims 1-20 have been considered and have overcome the Examiner’s prior rejections and thus are withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Regarding Claim 1:
Applicant’s argument ton page 10 of the submitted remarks that the cited prior art does not teach a processor with multiple processor cores in addition to a memory controller, register space, an embedded controller, and a local memory as recited in claim 1 has been considered and is persuasive. Thus, the prior rejection has been withdrawn. However, a new rejection has been made as noted above.
Applicant’s argument on Page 11 of the submitted remarks that a read/write control section is not a memory controller has been considered but is moot in view of the new grounds of rejection.
Applicant’s argument on page 11 of the submitted remarks that there is no memory coupled to error log management section 33 has been considered but is moot in view of the new grounds of rejection.
Applicant’s argument on page 12 of the submitted remarks that “the Examiner does not provide any explanation to how Minamimoto would be modified by Elyasi or otherwise how Minamimoto would be combined with Elyasi to obtain an invention including the claim elements asserted to be obvious in view of the combination” has been considered but is moot in view of the new grounds of rejection.
Applicant’s argument on pages 14-20 of the submitted remarks that there is no motivation to combine the cited prior art, and that there would be no reasonable expectation of success, has been considered but is moot in view of the new grounds of rejection.
Regarding Claim 8:
Applicant’s argument ton page 21 of the submitted remarks that the cited prior art does not teach a processor with multiple processor cores in addition to a memory controller, register space, an embedded controller, and a local memory as recited in claim 8 has been considered and is persuasive. Thus, the prior rejection has been withdrawn. However, a new rejection has been made as noted above.
Applicant’s argument on page 21 of the submitted remarks that the cited prior art fails to teach an interrupt has been considered but is moot in view of the new grounds of rejection.
Applicant’s argument on page 22 of the submitted remarks that the error log management section of the cited prior art is not an embedded controller has been considered but is moot in view of the new grounds of rejection.
Applicant’s argument on page 22 of the submitted remarks that there is no motivation to combine the cited prior art, and that there would be no reasonable expectation of success, has been considered but is moot in view of the new grounds of rejection.
Regarding Claim 14:
Applicant’s argument ton page 24 of the submitted remarks that the cited prior art does not teach a processor with multiple processor cores in addition to a memory controller, register space, an embedded controller, and a local memory as recited in claim 14 has been considered and is persuasive. Thus, the prior rejection has been withdrawn. However, a new rejection has been made as noted above. The examiner maintains the scope of claim 14 has changed, as in the prior claims submitted 6/30/2022, the plurality of processing cores, memory controller, register, embedded controller, and local memory may be interpreted as part of the computing system in the broadest reasonable interpretation.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135