DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Accordingly, claims 1-20 are pending in this application. Claims 1, 5, 6, 11, 12, 14-16, 18 and 20 are currently amended; claims 2, 4, 9, 10 and 19 are previously presented; claims 3, 7, 8, 13 and 17 are original.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/24/2026 and 06/17/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites “wherein routing the plurality of products is performed …”. A wherein clause is normally used to further limit an element that is previously introduced. However, the claim does not recite any step of routing the plurality of products. The step routing the plurality of products is deleted in claim 16 from which the claim depends. Therefore, there is insufficient antecedent basis for this limitation in the claim. For purposes of examination, this is interpreted as “further comprising routing the plurality of products, wherein routing the plurality of products is performed by …” instead.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (NPL – “A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration”), hereinafter Weng, in view of Ahmad et al. (NPL – “How Can We Be So Dense? The Benefits of Using Highly Sparse Representations”), hereinafter Ahmad, and Dally et al. (US 20180046916 A1), hereinafter Dally.
Regarding claim 1, Weng teaches an accelerator for performing operations on tensors, the accelerator comprising:
a plurality of first computation circuits configured to perform first computations between values in a dense tensor derived from a plurality of sparse tensors and values in an activation tensor to generate a plurality of products, wherein the values in the dense tensor are associated with tensor identifiers to identify the sparse tensors where the values originated (Weng Figs. 3-5, section II.A, II.B, III.A and III.B; plurality of first computation circuits – multipliers; first computations – multiplications; values in a process tensor – values of the sparse kernels; values in an activation tensor – values of the input tensor; plurality of products – products; tensor identifiers – tensor labels);
(Weng Figs. 4-5 and page 5 section III.A; the labels are carried over to the products because the accumulators know which specific subsets of values to accumulate; the products are divided into four subsets in the HCSS and into two subsets in the FCSS);
a plurality of second computation circuits (Weng Figs. 4-5 and section III.A and III.B “products are first accumulated along the input channel, and then the generated partial sums are accumulated spatially for final outputs of three types of convolution (dense, FCSS and HCSS). In the input-channel accumulation, the products are labeled (from 0 to 8) according to their positions in the 3×3 kernel and the corresponding input channel, and the products with the same label are accumulated to generate partial sums. In the spatial accumulation, the partial sums are accumulated by the combining relation to generate convolution results for dense, FCSS and HCSS kernels”; plurality of second computation circuits – corresponding input-channel accumulators and spatial accumulators group for accumulating the products with the same label along the input channels and products belonging to the FCSS or HCSS; second computation – accumulation; output value – convolution output; plurality of output values – convolution outputs); and
an activation circuit coupled to the plurality of second computation circuits, (Weng Fig. 5 and section III.B “Finally, the convolution outputs are sent to ReLU unit (ReLU) and Quantizer (Q) for post-processing”; activation circuit – ReLU).
Weng does not explicitly teach a routing circuit coupled to the plurality of first computation circuits, the routing circuit configured to carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers; a plurality of second computation circuits coupled to the routing circuit; and the activation circuit configured to select a subset of the output values to retain and set remaining ones of the plurality of output values as zero.
However, on the same field of endeavor, Ahmad discloses an activation function configured to select a subset of the output values to retain and set remaining ones of the plurality of output values as zero (Ahmad page 5 left col top “Second, only the top-k active units within each layer are maintained in yl, and the rest set to zero. This k-winners step is non-linear and can be thought of as a substitute for the ReLU function. Instead of a threshold of 0, the threshold here is adaptive and corresponds to the k’th largest activation (Makhzani & Frey, 2013)”; page 6 section 3.2 “In order to implement sparse CNN layers, the k-winners layer is applied to the output of the max-pooling layer instead of ReLU (just as in our non-convolutional layers)”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng using Ahmad and configure the activation circuit to implement a k-winners layer (function) instead of the ReLU in order to implement sparse CNN layers because sparse representations are naturally more robust to noise and interference from random inputs (Ahmad abstract, introduction right col middle, and section 3.2).
Therefore, the combination of Weng as modified in view of Ahmad teaches an activation circuit coupled to the plurality of second computation circuits, the activation circuit configured to select a subset of the output values to retain and set remaining ones of the plurality of output values as zero.
Weng as modified in view of Ahmad does not explicitly teach a routing circuit coupled to the plurality of first computation circuits, the routing circuit configured to carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers; a plurality of second computation circuits coupled to the routing circuit.
However, on the same field of endeavor, Dally discloses a routing circuit coupled to a plurality of first computation circuits, i.e., an array of multipliers and to a plurality of second computation circuits, i.e., an accumulator array comprising an array of adders and buffers, wherein the routing circuit is configured to route a plurality of products generated by the multiplier array to corresponding accumulator unit of the accumulator array (Dally Figs. 3A and 3C routing circuit – crossbar 335; paragraph [0070] “The FxI arbitrated crossbar 335 routes FxI products to an array of A accumulator units based on the output positions associated with each product. The positions may be translated to form an address. A particular product is transmitted to the one accumulator unit in the accumulator array 340 that is configured to compute the output activation for the position associated with the product”; paragraph [0087] “The F*I arbitrated crossbar 335 transmits the products to the associated accumulator in the accumulator array 340 based on the product positions”; paragraph [0090] “The products are routed to adders within the accumulator array 340, where each product is routed to a particular adder selected by the linear address associated with the product”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng in view of Ahmad using Dally and configure the convolution engine to include routing circuitry downstream of the multipliers and upstream of the accumulators in order to correctly route the products to the corresponding accumulators such that the products with the same labels are accumulated then partial sums belonging to the corresponding HCSS or FCSS are accumulated to generate the convolution results (Dally paragraph [0070] and Weng page 2 section III.A).
Therefore, the combination of Weng as modified in view of Ahmad and Dally teaches a routing circuit coupled to the plurality of first computation circuits, the routing circuit configured to carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers; a plurality of second computation circuits coupled to the routing circuit.
Regarding claim 2, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 1 as stated above.
Weng does not explicitly teach wherein the activation circuit is further configured to boost one or more output values of the plurality of output values before selecting the subset of the output values to retain.
However, on the same field of endeavor, Ahmad discloses boosting one or more output values of the plurality of output values before selecting the subset of the output values to retain (Ahmad page 5 section 3.1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng using Ahmad and configure the activation circuit boost one or more output values of the plurality of output values before the activation selection such that units which have not been active recently have a disproportionately higher impact and are more likely to win, whereas overly active units are de-emphasized because it is desirable for every unit to be equally active in order to maximize the robustness of the representation (Ahmad page 5 section 3.1).
Therefore, the combination of Weng as modified in view of Ahmad and Dally teaches wherein the activation circuit is further configured to boost one or more output values of the plurality of output values before selecting the subset of the output values to retain.
Regarding claim 3, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 2 as stated above. Further, Weng as modified in view of Ahmad and Dally teaches wherein the one or more output values that are boosted correspond to one or more nodes that are set to zero in a previous cycle of operation (Ahmad page 5 section 3.1).
Regarding claim 4, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 1 as stated above. Further, Weng as modified in view of Ahmad and Dally teaches wherein a number of the subset of output values to retain is fixed (Ahmad page 1 introduction right col bottom “In addition the output of each layer is constrained such that only the k most active units are allowed to be non-zero”; fixed number of output values – k; page 5 left col top; page 6 section 3.2).
Regarding claim 5, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 1 as stated above. Further, Weng as modified in view of Ahmad and Dally teaches wherein the dense tensor is a complementary dense tensor including values from non-overlapping locations of the plurality of sparse tensors (Weng Fig. 3 and page 2 section II.B “The reconfigurability can be realized by the combining relation among dense, FCSS and HCSS kernels. As shown in Fig. 3a, a dense kernel can be obtained by combining two different FCSS kernels, and a FCSS kernel can also be obtained by combining two corresponding HCSS kernels”; plurality of sparse process tensors - FCSS or HCSS; each sparse tensor has a unique label 00-03 for HCSS and 00-01 for FCSS in addition to the labels 0-8 indicating the element position in each kernel and all the kernel values are non-overlapping except the center value).
Regarding claim 6, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 1 as stated above. Further, Weng as modified in view of Ahmad and Dally teaches further comprising: a plurality of adder trees coupled to the routing circuit, each of the adder trees configured to accumulate a subset of the products corresponding to a same tensor identifier (Weng Fig. 5; plurality of adder trees – spatial accumulator).
Regarding claim 7, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 6 as stated above. Further, Weng as modified in view of Ahmad and Dally teaches wherein the routing circuit comprises an arbiter circuit that controls routing of a product of the plurality of products to one of the adder trees (Dally Fig. 3C and paragraph [0094] “The arbiter 365 generates a grant vector gr[*] [i] (selecting the winning i for the j accumulator unit 368). Across all the accumulator units 368, if bit gr[i][j] of the PxI grant matrix is true, it implies that input i has been granted access to the j accumulator unit 368 for the next cycle. The grant signals are used both to control the multiplexer 366, to select the winning product and address from the multiplexer inputs and providing an indication back to the FIFO 362-so the winning product is dequeued from the FIFO 362 at the end of the processing cycle”; arbiter circuit – arbiter 365).
Regarding claims 11-17, they are directed to a method practiced by the accelerator of claims 1-7 respectively. All steps performed by the method of claims 11-17 would be practiced by the accelerator of claims 1-7 respectively. Claims 1-7 analysis applies equally to claims 11-17 respectively.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Weng in view of Ahmad and Dally as applied to claim 6 above, and further in view of Pai et al. (US 20200193234 A1), hereinafter Pai.
Regarding claim 8, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 6 as stated above.
Weng as modified in view of Ahmad and Dally does not explicitly teach wherein the activation circuit comprises a histogram memory that is configured to build a histogram that represents a distribution of the plurality of output values.
However, on the same field of endeavor, Pai discloses a histogram memory that is configured to build a histogram that represents a distribution of input data (Pai paragraph [0043] histogram memory – component storing the histograms).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng in view of Ahmad and Dally and generalize the teaching of Pai by configuring the activation circuit to include a histogram memory to capture and store a histogram that represents a distribution of the plurality of output values that are input to the activation circuit in order to determine the range of the plurality of output values which can be used to determine the k’th largest output values that are selected as the winners (Ahmad page 5 left col top paragraph).
Therefore, the combination of Weng as modified in view of Ahmad, Dally and Pai teaches wherein the activation circuit comprises a histogram memory that is configured to build a histogram that represents a distribution of the plurality of output values.
Regarding claim 18, it is directed to a method practiced by the accelerator of claim 8. All steps performed by the method of claim 18 would be practiced by the accelerator of claim 8. Claim 8 analysis applies equally to claim 18.
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Weng in view of Ahmad and Dally as applied to claim 6 above, and further in view of Rose (US 12086566 B2).
Regarding claim 9, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 6 as stated above.
Weng does not explicitly teach wherein the activation circuit comprises a sorting circuit configured to select the values to retain from serial bursts of the output values.
However, on the same field of endeavor, Rose discloses a sorting circuit configured to select, find and sort a number of input values above a threshold value (Rose Fig. 10, claim 8 and col 4 lines 25-45; sorting circuit – hardware implementing Fig. 10). Further, Rose discloses that sorting steps are performed in series (Rose col 6 lines 33-43, col 28 lines 42-57 and col 29 line 65 to col 30 line 3).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng in view of Ahmad and Dally and generalize the teaching of Rose by configuring the activation circuit to include one iteration of sorting circuitry for finding and selecting the k-winner output values serially over multiple cycles in order to reduce the hardware area for implementing the sorting circuit (Rose col 6 lines 33-43).
Therefore, the combination of Weng as modified in view of Ahmad, Dally and Rose teaches wherein the activation circuit comprises a sorting circuit configured to select the values to retain from serial bursts of the output values.
Regarding claim 10, Weng as modified in view of Ahmad and Dally teaches all the limitations of claim 6 as stated above.
Weng does not explicitly teach wherein the activation circuit comprises a sorting circuit configured to select the values to retain from the plurality of output values in parallel.
However, on the same field of endeavor, Rose discloses a sorting circuit configured to select, find and sort a number of input values above a threshold value (Rose Fig. 10, claim 8 and col 4 lines 25-45; sorting circuit – hardware implementing Fig. 10). Further, Rose discloses that sorting steps are performed in parallel (Rose col 28 lines 54-57 and col 29 line 65 to col 30 line 3).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Weng in view of Ahmad and Dally and generalize the teaching of Rose by configuring the activation circuit to include sorting circuitry for finding and selecting the k-winner output values in parallel in order to increase performance of the sorting circuitry (Rose col 6 lines 43-46).
Therefore, the combination of Weng as modified in view of Ahmad, Dally and Rose teaches wherein the activation circuit comprises a sorting circuit configured to select the values to retain from the plurality of output values in parallel.
Regarding claims 19-20, they are directed to a method practiced by the accelerator of claims 9-10 respectively. All steps performed by the method of claims 19-20 would be practiced by the accelerator of claims 9-10 respectively. Claims 9-10 analysis applies equally to claims 19-20 respectively.
Response to Arguments
Applicant's arguments filed 03/23/2026, see remarks page 8-10 with respect to the 35 U.S.C. 103 rejection of claims 1-20 have been fully considered but they are not persuasive.
Applicant argues the following:
1.) Applicant argues that Weng fails to teach the feature of “a plurality of first computation circuits configured to perform first computations between values in a dense tensor derived from a plurality of sparse tensors and values in an activation tensor ... wherein the values in the dense tensor are associated with tensor identifiers to identify the sparse tensors where the values originated” because Fig. 3 of Weng merely discloses how the dense, FCSS, and HCSS kernels are related but does not describe combining multiple independent sparse tensors into a single dense tensor. Further, the products label indicate spatial position within the 3x3 kernel grid, not which sparse tensor the value originated from.
Examiner respectfully disagrees. Weng section II.B discloses “As shown in Fig. 3a, a dense kernel can be obtained by combining two different FCSS kernels, and a FCSS kernel can also be obtained by combining two corresponding HCSS kernels.” Therefore, the dense kernel is comprised of two FCSS kernels combined into a single dense kernel. Accordingly, the dense/FCSS kernels can also be comprised of four/two HCSS kernels combined into a single dense kernel. Further as shown in Fig. 3, the kernels are labeled as 00-04 for HCSS and 00-01 for FCSS which identifies the values in the 3x3 dense kernel which HCSS or FCSS kernel the values are from. Therefore, Weng fairly teaches the claimed features of “a plurality of first computation circuits configured to perform first computations between values in a dense tensor derived from a plurality of sparse tensors and values in an activation tensor to generate a plurality of products, wherein the values in the dense tensor are associated with tensor identifiers to identify the sparse tensors where the values originated”.
2.) Dally fails to disclose “a routing circuit coupled to the plurality of first computation circuits, the routing circuit configured to carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers” because the crossbar 355 of Dally routes products from the FxI multiplier array 325 to an array of accumulator units 340 based on output position coordinates computed by a destination calculation unit 330. Therefore, Dally's crossbar 335 does not carry over any identifier from the input weights to the output products.
Examiner respectfully disagrees. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicant is arguing Dally individually rather than the combination of Weng and Dally. The features of “carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers” are disclosed in Weng in at least Figs. 4-5 and page 5 section III.A and Dally is being used to disclose a routing circuitry that can be used for routing the products from the multipliers to the correct adders/accumulators such that the products having the same combining relation (i.e., products belonging to the same weight kernel 00-04 for HCSS and 00-01 for FCSS are correctly routed to the corresponding adders/accumulators. Therefore, the combination of Weng and Dally fairly teaches the claimed features of “a routing circuit coupled to the plurality of first computation circuits, the routing circuit configured to carry over the tensor identifiers of the values in the dense tensor to the plurality of products, and divide the plurality of products into subsets based on the tensor identifiers”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mei at al. (US 20220309124 A1) discloses merging two or more sparse tensors into a dense tensor and generating metadata for identifying the original position of non-zero elements in the sparse tensor. Mei is cited in the IDS submitted on 03/24/2026.
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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