DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2021/0066279).
Claim 1, Yu discloses an integrated circuit system in a package (Figs. 14D-14E) comprising:
a first programmable logic fabric die comprising programmable logic circuitry (see P[0031]… logic die LD1 may be … a field programmable gate array (FPGA)…); and
a plurality of chiplets (logic die LD2 and memory die MD) comprising disaggregated field programmable gate array (FPGA) circuitry (see P[0031]… second logic dies LD2 may be respectively a central processing unit (CPU) die, a graphics processing unit (CPU) die, a general processing unit (GPU) die, an artificial intelligence (AI) engine die, a Transceiver (TRX) die, or the like…), wherein the plurality of chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement (see P[0027]… 3D packaging or 3DIC devices…).
Claim 4, Yu discloses the integrated circuit system of claim 1, wherein the plurality of chiplets each comprise one or more FPGA memory, FPGA digital signal processor (DSP) blocks (see P[0031]…second logic dies LD2 may be respectively ….a general processing unit (GPU) die…), FPGA input/output (IO) circuitry, or an FPGA hard processor system (see P[0031… second logic dies LD2 may be respectively a central processing unit (CPU) die…).
Claim 7, Yu discloses the integrated circuit system of claim 1, comprising an additional chiplet (Memories MD, Figs. 14D-14E) connected to the first programmable logic fabric die in the three-dimensional arrangement, wherein the additional chiplet comprises circuitry (memory) other than disaggregated FPGA circuitry.
Claim(s) 1, 3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 2020/0328181).
Claim 1, Liu discloses an integrated circuit system in a package (Figs. 4A-4C, 7A-7B, 13C) comprising:
a first programmable logic fabric die comprising programmable logic circuitry (PLD, Figs. 4A-4B); and
a plurality of chiplets (NAND MEMORY and DRAM, Figs. 4A-4B) comprising disaggregated field programmable gate array (FPGA) circuitry, wherein the plurality of chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement (see Figs. 7A-7B).
Claim 3, Liu discloses the integrated circuit system of claim 1, wherein the first programmable logic fabric die (501, Fig. 5A) only includes programmable logic blocks (logic blocks 504), programmable routing circuitry (inherent element, see P[0065]… FPGAs include an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the programmable logic blocks to be connected in different configurations to implement different logic functions…), and die-to-die input/output (IO) circuitry (I/O blocks 518).
Claim(s) 1, 3-4, 7-8, 10, 13-14, 15, and 19-22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pal et al. (US 2022/0014202).
Claim 1, Pal discloses an integrated circuit system in a package (Fig. 15) comprising:
a first programmable logic fabric die comprising programmable logic circuitry (Programmable Base 518, Fig. 15 and see P[0109]… The programmable fabric base die 518 may be an FPGA-like fabric…); and
a plurality of chiplets (chiplets 516, 522, and 520, Fig. 15 and P[0109]… chiplets may include a CPU chiplet 516, a dual acceleration (DL) chiplet 520, a Graphics Processing Unit (GPU) chiplet 522…) comprising disaggregated field programmable gate array (FPGA) circuitry, wherein the plurality of chiplets are connected to the first programmable logic fabric die in a three-dimensional arrangement (see P[0110]…3-D stacked…).
Claim 3, Pal discloses the integrated circuit system of claim 1, wherein the first programmable logic fabric die only includes programmable logic blocks (see P[0110]… fewer programmable logic components and dense computational engines…), programmable routing circuitry (P[00110]… router resource components…), and die-to-die input/output (IO) circuitry (inherent element for transmitting output signals to the chiplets and external to the package).
Claim 4, Pal discloses the integrated circuit system of claim 1, wherein the plurality of chiplets each comprise one or more of disaggregated FPGA circuitry comprising FPGA memory, FPGA digital signal processor (DSP) blocks (GPU 522, Fig. 15), FPGA input/output (IO) circuitry, or an FPGA hard processor system (CPU-516, Fig. 15).
Claim 7, Pal discloses the integrated circuit system of claim 1, comprising an additional chiplet (FPGA 524, Fig. 15) connected to the first programmable logic fabric die in the three- dimensional arrangement, wherein the additional chiplet comprises circuitry (FPGA) other than disaggregated FPGA circuitry.
Claim 8, Pal discloses the integrated circuit system of claim 1, comprising a substrate (inherent element of a system in a package) upon which the first programmable logic fabric die (Programmable Base 518, Fig. 15) is disposed, wherein the plurality of chiplets (chiplets 516, 520, 522, Fig. 15) are disposed above the first programmable logic fabric die in the three-dimensional arrangement.
Claim 10, Pal discloses the integrated circuit system of claim 1, comprising a second programmable logic fabric die (FPGA 524, Fig. 15).
Claim 13, Pal discloses the integrated circuit system of claim 10, wherein the first programmable logic fabric die (Programmable Base 518, Fig. 15) and the second programmable logic fabric die (FPGA 524, Fig. 15) are of different sizes.
Claim 14, Pal discloses One or more tangible, non-transitory, machine-readable media comprising instructions that, when executed by a processor, cause the processor to perform the following operations (see Fig. 8 and see P[0072]):
analyze a user design to be programmed into programmable logic fabric circuitry of a custom integrated circuit system to determine resources of the custom integrated circuit system used by the user design (implicit for defining the system of Fig. 15 and P[0072]);
select a plurality of chiplets (chiplets 516, 520, 522, 524 and 518, Fig. 15) that includes a first chiplet comprising the programmable logic fabric circuitry (Programmable Base 518, Fig. 15 and see P[0110]… programmable fabric base die 518 may be an FPGA-like fabric….) and a second chiplet (CPU 516 or GPU 522, Fig. 15) and a third chiplet (DL 520, Fig. 15) respectively comprising circuitry to support the programmable logic fabric circuitry, wherein the plurality of chiplets collectively comprise comprises the resources of the custom integrated circuit system used by the user design (see P[0072], [0109]-[0111] and Fig. 15); and
generate a custom integrated circuit system design comprising the selected plurality of chiplets (see P[0072] and Fig. 15).
Claim 15, Pal discloses the one or more tangible, non-transitory, machine-readable media of claim 14, wherein the instructions to generate the design of the custom integrated circuit system design comprise instructions to position the selected plurality of chiplets relative to one another (see Fig. 15, the chiplets are arranged relative to one another).
Claim 19, Pal discloses a method comprising:
receiving a custom integrated circuit system design (see Fig. 8 and P[0072]) comprising:
a plurality of chiplets (chiplets 516-524, Fig. 15) that include includes a first chiplet comprising programmable logic fabric circuitry (Programmable Base 518, Fig. 15) and a second chiplet (CPU 516 or GPU 522, Fig. 15) and a third chiplet (DL 520, Fig. 15) respectively comprising circuitry to support the programmable logic fabric circuitry; and
assembling, based on the custom integrated circuit system design (see Fig. 8 and P[0072]), an integrated circuit system using the first chiplet, second chiplet, and third chiplet at least in part by connecting the second chiplet and the third chiplet to the first chiplet in a three-dimensional arrangement (Fig. 15 and see P[0109]… 3-D arrangement…).
Claim 20, Pal discloses the method of claim 19, wherein the second chiplet and the third chiplet comprise at least one of: additional programmable logic fabric circuitry (FPGA 524), digital signal processing (DSP) circuitry (GPU 522), IO circuitry, memory circuitry, hard processor system (HPS) circuitry (CPU 516), transceiver circuitry, encryption or decryption circuitry, a device controller, a voltage regulator, an artificial intelligence (Al) engine, or a network on chip (NOC).
Claim 21, Pal discloses the method of claim 19, wherein generating the custom integrated circuit system design comprises selecting the plurality of chiplets (see Fig. 15) based on resources used by a user design (see Fig. 8 and P[0072]).
Claim 22, Pal discloses the method of claim 21, wherein generating the custom integrated circuit system design comprises positioning the selected plurality of chiplets relative to one another (Fig. 15 shows positioning the selected plurality of chiplets relative to one another).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (US 2022/0014202) in view of Liu et al. (US 2020/0328181).
Pal discloses the claimed invention except that a substrate upon which at least one of the plurality of chiplets is disposed, wherein the first programmable logic fabric die is disposed above the at least one of the plurality of chiplets disposed on the substrate instead of a substrate upon which the first programmable logic fabric die is disposed, wherein the plurality of chiplets are disposed above the first programmable logic fabric die. Liu discloses the first programmable logic fabric die is disposed above or below the at least one of the plurality of chiplets is an equivalent structure (see Figs. 7A and 7B) known in the art. Therefore, because these two arrangements were art-recognized equivalents before the effective filing date of the claimed invention was made, one of ordinary skill in the art would have found it obvious to substitute wherein the first programmable logic fabric die is disposed above the at least one of the plurality of chiplets disposed on the substrate for wherein the plurality of chiplets are disposed above the first programmable logic fabric die.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (US 2022/0014202) in view of Cheah et al. (US 2021/0193616).
Pal discloses the claimed invention except the system comprising a bridge, wherein the first programmable logic fabric die and the second programmable logic fabric die are in a 2.5D arrangement with respect to one another and in communication with one another via the bridge.
In the same field of endeavor, Cheah discloses a system comprises a plurality of chiplets having a field programmable gate array (FGPA), a central processing unit (CPU), a graphic processing unit (GPU), or/and memory die configured in a 2.5D arrangement with respect to one another (see Figs. 1A, 2, and P[0020]) and further teaches the advantage of connecting a plurality of dies with bridges (see P[0012]-[0014]).
It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to rearrange a plurality of chiplets in the system of Pal in a 2.5D arrangement with respect to one another, as taught by Cheah, the bridge component can be used to couple multiple semiconductor dies on a package, such as vertically stacked semiconductor dies, while conserving space (e.g., an x-y footprint) in the package. Additionally, passive components, such as decoupling capacitors, can be mounted on the bridge component in die gaps, instead of on the package or circuit board surface and further allow for improved system power integrity performance by reduced loop inductance between power delivery decoupling components and silicon devices.
Claim(s) 12, 16-18, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pal et al. (US 2022/0014202).
Claim 12, Pal discloses the claimed invention except for wherein the first programmable logic fabric die and the second programmable logic fabric die are connected to one another in an additional three-dimensional arrangement. It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention was made provide an additional three-dimensional arrangement as shown in Fig. 15 with another Programmable Base 518 as a second programmable logic fabric die, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art.
Claims 16-18, Pal discloses the claimed invention except for wherein to position the selected plurality of chiplets relative to one another based on a spatial positioning, thermal and/or bandwidth constraint. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention was made to position the selected plurality of chiplets relative to one another based on a spatial positioning, thermal and/or bandwidth constraint since it was known in the art that the physical positioning based on spatial, thermal and bandwidth requirements are standard physical design procedure in designing of the integrated circuit system, in order to optimum the system performance and limit power consumption of the system.
Claim 23 is rejected as above claims 16-18 since the elements and limitations are similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jang et al. (US 2023/0086202) and Faisal et al. (US 2022/0200611) is a plurality of chiplets connected in three-dimensional arrangement having a programmable logic die, compute die, and memory die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH Q TRAN whose telephone number is (571)272-1813. The examiner can normally be reached M-F: 9AM - 5PM.
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/ANH Q TRAN/Primary Examiner, Art Unit 2844 1/15/26