Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 19-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 10, 2025.
Remarks
The Office has cited particular columns, line numbers, paragraph numbers, references, or figures in the references applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses to fully consider the reference in entirety, as potentially teaching all or part of the claimed invention. See MPEP § 2141.02 and § 2123.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-9, and 11-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chaware et al. (US 2017/0110407 A1, hereinafter referred to as Chaware).
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Regarding claim 1, Chaware discloses an integrated circuit system (Figs. 1, 2, 4-6) comprising:
a first die (1st die, see annotated Figs. 1, 5 above) on a substrate (104);
a second die (2nd die, see annotated Figs. 1, 5 above) on the substrate; and
a programmable routing bridge (1st bridge 106, see annotated Figs. 1, 5 above; “The body 290 of the interconnect die 106 includes a plurality of conductive layers 210 and dielectric layers 212 which are fabricated to form an interconnect circuit 214 within the die 106.”, para 0032; “the interconnect circuit 214 may include solid state circuitry, such as one or more of a memory and/or logic device.”, para 0033; “The programmable pad 202 to pad 202 configuration of the interconnect circuit 214 enables a truly programmable selection of the interconnect routing between dice 102 connected by the interconnect die 106, which greatly increases the functional capability and design flexibility of the IC package 100.”, para 0056) embedded in the substrate, wherein the programmable routing bridge (1st bridge 106, see annotated Figs. 1, 5 above) is mounted (“The IC dice 102 are mounted to the interconnect die 106,”, para 0026) to the first die (1st die, see annotated Figs. 1, 5 above) and the second die (2nd die, see annotated Figs. 1, 5 above), and wherein the programmable routing bridge (1st bridge 106, see annotated Figs. 1, 5 above) is configurable to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between selectable points of the first die and selectable points of the second die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred from a certain location of a first memory device of the 1st die to a certain location of a second memory device of the 2nd die).
Regarding claim 2, Chaware discloses the integrated circuit system of claim 1, wherein the programmable routing bridge comprises a microbump array (108, para 0027) to communicatively couple to a first interface of the first die and a second interface of the second die (interface is inherent for the first die and the second die. See “The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026.).
Regarding claim 4, Chaware discloses the integrated circuit system of claim 1, comprising a third die (3rd die, see annotated Fig. 5 above) on the substrate, wherein the programmable routing bridge (106) is mounted to the third die, and wherein the programmable routing bridge is configurable to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between selectable points of the third die to selectable points of the first die or selectable points of the second die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred from a certain location of a third memory device of the 3rd die to a certain location of a second memory device of the 2nd die).
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Regarding claim 5, Chaware discloses the integrated circuit system of claim 4, wherein the first die (1st die, see annotated Fig. 4 above), the second die (2nd die, see annotated Fig. 4 above), and the third die (3rd die, see annotated Fig. 4 above) are disposed in a 3x1 or 1x3 arrangement (see annotated Fig. 4 above) on the substrate, and wherein the integrated circuit system comprises: another programmable routing bridge (2nd bridge, see annotated Fig. 4 above) embedded in the substrate, wherein the other programmable routing bridge is mounted to the second die (2nd die, see annotated Fig. 4 above) and the third die (3rd die, see annotated Fig. 4 above), and wherein the other programmable routing bridge (2nd bridge, see annotated Fig. 4 above) is configurable to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between selectable points of the second die and selectable points of the third die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred between a certain location of a second memory device of the 2nd die and a certain location of a third memory device of the 3rd die).
Regarding claim 6, Chaware discloses the integrated circuit system of claim 4, comprising a fourth die (4th die, see annotated Fig. 5 above) on the substrate, wherein the first die, the second die, the third die, and the fourth die are disposed in a 2x2 arrangement (see annotated Fig. 5 above) on the substrate, and wherein the programmable routing bridge (106) is configurable to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between selectable points of the first die, selectable points of the second die, selectable points of the third die, and selectable points of the fourth die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred between a certain location of a first memory device of the 1st die, a certain location of a second memory device of the 2nd die, a certain location of a third memory device of the 3rd die, and a certain location of a fourth memory device of the 4th die).
Regarding claim 7, Chaware discloses the integrated circuit system of claim 6, wherein the programmable routing bridge is communicatively coupled to a first interface of the first die, a second interface of the second die, a third interface of the third die, and a fourth interface of the fourth die (interface is inherent for the first, second, third and fourth die. See “The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026.).
Regarding claim 8, Chaware discloses the integrated circuit system of claim 7, wherein the first interface of the first die is in one quadrant of the first die, the second interface of the second die is in one quadrant of the second die, the third interface of the third die is in one quadrant of the third die, and the fourth interface of the fourth die is in one quadrant of the fourth die (see Fig. 5; paragraphs 0026, 0043).
Regarding claim 9, Chaware discloses the integrated circuit system of claim 7, wherein the first die, the second die, the third die, and the fourth die are identical (see Fig. 5; paragraphs 0026, 0043).
Regarding claim 11, Chaware discloses the integrated circuit system of claim 1, wherein at least one of the first die or the second die comprises field programmable gate array circuitry (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA)”, para 0026).
Regarding claim 12, Chaware discloses the integrated circuit system of claim 1, wherein at least one of the first die or the second die comprises a processor (“The IC dice 102 may be.… processors”, para 0026.).
Regarding claim 13, Chaware discloses an integrated circuit system (Figs. 1, 2, 4-6) comprising:
a first die (1st die, see annotated Figd. 1, 5 above) on a substrate (104);
a second die (2nd die, see annotated Figs. 1, 5 above) on the substrate; and
a programmable routing bridge (1st bridge 106, see annotated Fig. 1 above; “The body 290 of the interconnect die 106 includes a plurality of conductive layers 210 and dielectric layers 212 which are fabricated to form an interconnect circuit 214 within the die 106.”, para 0032; “the interconnect circuit 214 may include solid state circuitry, such as one or more of a memory and/or logic device.”, para 0033; “The programmable pad 202 to pad 202 configuration of the interconnect circuit 214 enables a truly programmable selection of the interconnect routing between dice 102 connected by the interconnect die 106, which greatly increases the functional capability and design flexibility of the IC package 100.”, para 0056) embedded in the substrate, wherein the programmable routing bridge (1st bridge 106, see annotated Figs. 1, 5 above) is mounted (“The IC dice 102 are mounted to the interconnect die 106,”, para 0026) to the first die (1st die, see annotated Figs. 1, 5 above) and the second die (2nd die, see annotated Figs. 1, 5 above), and wherein the programmable routing bridge (1st bridge 106, see annotated Figs. 1, 5 above) is via-configured (see Fig. 2) to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between defined points of the first die and defined points of the second die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred from a certain location of a first memory device of the 1st die to a certain location of a second memory device of the 2nd die).
Regarding claim 14, Chaware discloses the integrated circuit system of claim 13, comprising a third die (3rd die, see annotated Fig. 5 above) and a fourth die (4th die, see annotated Fig. 5 above) mounted to the programmable routing bridge (106), and wherein the programmable routing bridge is configured to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between defined points of the third die and defined points of the fourth die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred between a certain location of a third memory device of the 3rd die, and a certain location of a fourth memory device of the 4th die).
Claim 15 is essentially the same in scope as apparatus claim 1 and is rejected similarly.
Regarding claim 16, Chaware discloses the one or more processors to generate the configuration data according to a first mapping function (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) that defines a first set of die- to-die pathways between the first die and the second die.
Regarding claim 17, Chaware discloses wherein the one or more processors to also generate the configuration data according to a second mapping function (“Signals may be exchanged between the IC dice 102 through both the interconnect dice 106 and the package substrate 104”, para 0029) different from the first mapping function that defines a second set of die- to-die pathways between the first die and the second die; and
the instructions to transfer the configuration data comprise instructions that, when executed, cause the one or more processors to transfer the configuration data to the integrated circuit system to cause the programmable routing bridge to become configured to transfer data between the first die and the second die according to the first mapping function (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) or the second mapping function (“Signals may be exchanged between the IC dice 102 through both the interconnect dice 106 and the package substrate 104”, para 0029).
Regarding claim 18, Chaware discloses the one or more processors to generate the configuration data based on a system design corresponding to a configuration of programmable logic circuitry of the first die or the second die (intended since “the IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures”, para 0026, and in order for the programmable logic circuitry such as FPGA to work properly, configuration data has to be generated by the system); and to cause the programmable logic circuitry of the first die or the second die to be configured with the system design (intended since “the IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures”, para 0026, and in order for the programmable logic circuitry such as FPGA to work properly, configuration data has to be generated by the system).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaware in view of Teh et al. (US 10,886,218 B2, hereinafter referred to as Teh).
Regarding claim 3, Chaware discloses all the features and limitations as discussed above but does not explicitly disclose wherein the first interface and the second interface comprise advanced interface bus (AIB) circuitry, universal interface bus (UIB) circuitry, or advanced extensible interface (AXI) circuitry to transfer data to and receive data from the microbump array of the programmable routing bridge.
Teh discloses a direct fabric die-to-fabric die interconnect (e.g., an Advanced Interface Bus-Direct (AIB-D)) interface to enable fabric dies to communicate one another (col. 2, ll. 65+).
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features of Teh into the device of Chaware to enable fabric dies to communicate one another as taught by Teh.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaware in view of Collins et al. (US 2019/0206798 A1, hereinafter referred to as Collins).
Regarding claim 10, Chaware discloses all the features and limitations as discussed above and further comprising: a third die (3rd die, see annotated Fig. 5 above) on the substrate; a fourth die (4th die, see annotated Fig. 5 above) on the substrate; wherein the programmable routing bridge (106) is mounted to the first die, the second die, the third die, and the fourth die (see Fig. 5), and wherein the programmable routing bridge (106) is configurable to transfer data (“signals may be exchanged between the IC dice 102 directly through one of the interconnect dice 106”, para 0029) between selectable points of the first die, selectable points of the second die, selectable points of the third die, and selectable points of the fourth die (“The IC dice 102 may be programmable logic devices, such as field programmable gate arrays (FPGA), memory devices, optical devices, processors or other IC logic structures.”, para 0026. Therefore, e.g. data can be transferred between a certain location of a first memory device of the 1st die, a certain location of a second memory device of the 2nd die, a certain location of a third memory device of the 3rd die, and a certain location of a fourth memory device of the 4th die).
Chaware further discloses that “FIG. 4-6 are but a few possible implementations of IC packages which may utilize interconnect dice 106 to provide communication at least between two dice 102 of the IC package. Other configurations are contemplated.”, para 0045; but Chaware does not explicitly disclose another programmable routing bridge embedded in the substrate is mounted to the third die, the fourth die, a fifth die, and a sixth die, and wherein the programmable routing bridge is configurable to transfer data between selectable points of the third die, selectable points of the fourth die, selectable points of the fifth die, and selectable points of the sixth die.
Collins disclose a first die (110D, Fig. 3) on a substrate (140); a second die (110A) on the substrate; a third die (110B) on the substrate; a fourth die (110E) on the substrate; a fifth die (110F) on the substrate; a sixth die (110C) on the substrate; routing bridge (120A); and another routing bridge (120B), wherein the routing bridge (120A) is mounted to the first die, the second die, the third die, and the fourth die (see Fig. 3); and wherein the another routing bridge (120B) is mounted to the third die, the fourth die, a fifth die, and a sixth die.
Therefore, it would have been obvious to a person having ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the features of Collins into the device of Chaware to incorporate more bridges to interconnect more dice and to adapt a variety of semiconductor die shapes, sizes, and configurations as taught by Collins (para 0063).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cunningham et al. (US 2009/0089466 A1) discloses proximity communication package for processor, cache and memory. Manusharow et al. (US 2014/0264791 A1) discloses direct external interconnect for embedded interconnect bridge package.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL D CHANG whose telephone number is (571)272-1801. The examiner can normally be reached M-F 8-5 EST.
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/DANIEL D CHANG/Primary Examiner, Art Unit 2844