DETAILED ACTION
Claims 1 – 17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 lines 8-11 and 18-19 recites the limitation “the programmable logic circuitry” lacking of antecedent basis. It should be “the FPGA programmable logic circuitry” to be consistent with prior limitation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Waldrop (US Publication 20200057688 A1) and in view of Bourgeault (US Publication 20210216098 A1).
Regarding claim 1, Waldrop discloses an integrated circuit comprising:
programmable logic circuitry configurable to include:
a first path to perform first operations on data taking a first amount of time [Fig. 4, i.e. data path 0 (76)] [Fig. 4] [0021-0029];
a second path to perform second operations on the data taking a second amount of time [Fig. 4, i.e. data path output from output register 0 (96)] [Fig. 4] [0021-0029]; and
hardened logic circuitry comprising:
one or more input registers [input register 0 (70)] to receive the data from the first path of the programmable logic circuitry [receiving input data 0 (76)] [Fig. 4] [0021-0029];
one or more output registers [output register 0 (96)] to output the data to the second path of the programmable logic circuitry [outputting data 103 to the combinational logic 51] [Fig. 4] [0021-0029];
first hardened logic circuitry [error calculation circuit 0] to perform third operations on the data taking a third amount of time between the one or more input registers and the one or more output registers [the error calculation circuit 0 perform data operations taking some amount of time between the input register 0 and the output register 0] [Fig. 4] [0021-0029]; and
a first tunable delay circuit configurable to delay a clock signal [clock 32] by a first delay [dclk0] to the one or more input registers or the one or more output registers, wherein the first delay is configurable to enable time borrowing between the first hardened logic circuitry and the first path of the programmable logic circuitry or the second path of the programmable logic circuitry [0025: As previously noted, the dclk0 102 corresponds to the clk0 82, where the dclk0 102 and the clk0 82 are generated from the same pulse of the clock 32, but the dclk0 102 is delayed by a duration set by the delay model 40 that is set as a worst case scenario duration of processing of the error calculation circuit 90 and/or the error calculation circuits 92 and 94 plus a fine tuning delay] [Fig. 4][0021-0029].
PNG
media_image1.png
504
792
media_image1.png
Greyscale
However, Waldrop does not explicitly disclose a field-programmable gate array (FPGA) programmable logic circuitry. In other words, Waldrop only discloses the programmable logic circuitry, not specifying it is the FPGA type.
In the same field, Bourgeault discloses a field-programmable gate array (FPGA) programmable logic circuitry comprising a delay circuitry to selectively delay a clock signal to the one or more input registers or the one or more output registers [Claim 8: receive a circuit design for field programmable gate array (FPGA) circuitry, wherein the circuit design comprises a plurality of paths including a faster path and a slower path; and perform a time borrowing process on the circuit design, wherein the time borrowing process comprises determining routing for clock signals supplied on overlapping clock networks that supply the clock signals to a same region of the FPGA circuitry, wherein the same region of the FPGA circuitry comprises a plurality of configurable logic blocks, to cause time to be borrowed from the faster path and given to the slower path][0010-0011: delay circuitry][Fig. 7].
PNG
media_image2.png
525
779
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Waldrop and Bourgeault together because they both directed to delay the clock signal to one or more registers. Bourgealt’s disclosing of the field-programmable gate array (FPGA) programmable logic circuitry would allow Waldrop to increase system’s integrity by utilizing complex parallel processing with ultra low latency and full hardware reconfigurability.
Regarding claim 2, Bourgeault discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises selection circuitry configurable to select the clock signal or the clock signal delayed by the first delay to provide to the one or more input registers [0038: By selecting appropriate delays for the clocks, a circuit designer can configure a logic circuit so that registers in slower paths have their clock edges delayed][0059][0069][0076][0081-0082][0084][0097].
Regarding claim 3, Waldrop discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises selection circuitry configurable to select the clock signal or the clock signal delayed by the first delay to provide to respective registers of the one or more output registers [0027: each single reset control circuitry 112 may include circuitry (e.g., a multiplexer) that provides the reset signal 34 to the corresponding output register(s) unless a corresponding delay clock is simultaneously asserted][Fig. 5] [0038][0059][0069][0076][0081-0082][0084][0097].
Regarding claim 4, Waldrop discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises a second delay circuit configurable to delay the clock signal by a second tunable delay to the other of the one or more input registers or the one or more output registers [0027: each single reset control circuitry 112 may include circuitry (e.g., a multiplexer) that provides the reset signal 34 to the corresponding output register(s) unless a corresponding delay clock is simultaneously asserted][Fig. 5] [0038][0059][0069][0076][0081-0082][0084][0097].
Regarding claim 5, Waldrop discloses the integrated circuit of claim 4, wherein the first delay is different from the second delay [0027: each single reset control circuitry 112 may include circuitry (e.g., a multiplexer) that provides the reset signal 34 to the corresponding output register(s) unless a corresponding delay clock is simultaneously asserted] ][Fig. 5] [0038][0059][0069][0076][0081-0082][0084][0097].
Regarding claim 6, Bourgeault discloses the integrated circuit of claim 1, wherein the hardened logic circuit comprises a digital signal processing (DSP) block [0029][0041].
Regarding claim 7, Waldrop discloses the integrated circuit of claim 1, wherein the hardened logic circuit comprises at least one of a memory block, a processor, an error correction block, or a crypto block [0013-0018].
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-12 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Majumdar (US Patent 9798352 B1).
Regarding claim 8, Majumdar discloses a digital signal processing (DSP) circuitry of an integrated circuit [Fig. 10] comprising:
a plurality of input registers to receive data [input registers 102], wherein the plurality of input registers are configurable to be clocked by a clock signal or a first delayed version of the clock signal [input registers 102 to be clocked either by root clock 914 or by delayed clock 916] [Col. 9 lines 36-Col. 10 lines 15];
first hardened logic circuitry [Combinational logic 924] to perform a first operation on the data [Col. 9 lines 36-Col. 10 lines 15];
a plurality of output registers to output the data [output registers 102]; and
a first tunable delay circuit [circuit 902] configurable to delay the clock signal by a first delay to generate the first delayed version of the clock signal [delayed clock 916] [Col. 9 lines 36-Col. 10 lines 15].
PNG
media_image3.png
581
687
media_image3.png
Greyscale
Regarding claim 9, Majumdar discloses the DSP circuitry of claim 8, comprising: selection circuitry configurable to select whether the plurality of input registers are clocked by the clock signal or to the first delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Regarding claim 10, Majumdar discloses the DSP circuitry of claim 8, comprising: a second tunable delay circuit configurable to delay the clock signal by a second delay to generate a second delayed clock signal; wherein at least a first of the plurality of output registers is configurable to be clocked by the second delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Regarding claim 11, Majumdar discloses the DSP circuitry of claim 10, comprising: selection circuitry configurable to select whether the first of the plurality of output registers is clocked by the clock signal or to the second delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Regarding claim 12, Majumdar discloses the DSP circuitry of claim 10, comprising: a third tunable delay circuit configurable to delay the clock signal by a third delay to generate a third delayed version of the clock signal; wherein at least a second of the plurality of output registers is configurable to be clocked by the third delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar (US Patent 9798352 B1) and in view of Bourgeault (US Publication 20210216098 A1).
Regarding claim 13, Majumdar does not disclose second hardened logic circuitry to perform a second operation on the data; and a first plurality of pipeline registers between the first hardened logic circuitry and the second hardened logic circuitry.
Bourgeault discloses second hardened logic circuitry [Fig. 7, logic 604] to perform a second operation on the data; and a first plurality of pipeline registers [registers 600] between the first hardened logic circuitry [logic 602] and the second hardened logic circuitry [Fig. 7] [0053-0059].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Majumdar and Bourgeault together because they both directed to delay the clock signal to one or more registers. Bourgealt’s disclosing of second hardened logic circuitry [Fig. 7, logic 604] to perform a second operation on the data; and a first plurality of pipeline registers [registers 600] between the first hardened logic circuitry [logic 602] and the second hardened logic circuitry would allow Majumdar to increase system’s integrity by incorporating multiple logic components between the registers and adjusting the delay to each registers accordingly.
PNG
media_image4.png
509
773
media_image4.png
Greyscale
Regarding claim 14, Majumdar discloses the DSP circuitry of claim 13, comprising: a second delay circuit configurable to delay the clock signal by a second delay to generate a second delayed version of the clock signal; wherein at least a first of the first plurality of pipeline registers is configurable to be clocked by the second delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15] [Fig. 10].
Regarding claim 15, Bourgeault discloses the DSP circuitry of claim 14, comprising: third hardened logic circuitry to perform a second operation on the data; and a second plurality of pipeline registers between the second hardened logic circuitry and the third hardened logic circuitry [Fig. 7] [0053-0059].
Regarding claim 16, Majumdar discloses the DSP circuitry of claim 15, wherein at least a first of the second plurality of pipeline registers is configurable to be clocked by the second delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Regarding claim 17, Majumdar discloses the DSP circuitry of claim 14, comprising: a third tunable delay circuit configurable to delay the clock signal by a third delay to generate a third delayed version of the clock signal; wherein at least a first of the second plurality of pipeline registers is configurable to be clocked by the third delayed version of the clock signal [Col. 9 lines 36-Col. 10 lines 15][Fig. 10].
Response to Arguments
Applicant’s arguments filed on 05/18/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHIL K NGUYEN/Primary Examiner, Art Unit 2176
Prosecution Insights