DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-17 in the reply filed on 11/12/2025 is acknowledged. Claims 18 – 20 are withdrawn. Since the restriction requirement properly made, the restriction requirement is now made final. Claims 1-17 are pending in this application. Applicant is remined to cancel the withdrawn claims or amend to recite the same scope with other group of claims for rejoinder consideration if appropriate.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 17 are rejected under AIA 35 U.S.C. 102(a)(1) as being anticipated by Zompakis (US Publication 20180096086 A1).
Regarding claim 1, Zompakis discloses an integrated circuit [Fig. 10] comprising:
programmable logic circuitry [circuit 700 and 710] configurable to include:
a first path to perform first operations on data taking a first amount of time [Fig. 10, 0093-0094: first path of data operation is inputted into registers 100];
a second path to perform second operations on the data taking a second amount of time [Fig. 10, 0093-0094: second path of data operation is the output of registers 160]; and
hardened logic circuitry [circuits 100,170,160, 720] comprising:
one or more input registers [input registers 100] to receive the data from the first path of the programmable logic circuitry [Fig. 10, 0093-0094: input registers 100 receive data from the first path of circuits 710 and 700];
one or more output registers [registers 160] to output the data to the second path of the programmable logic circuitry [Fig. 10, 0093-0094: output of registers 160 output data 120];
first hardened logic circuitry [combinational circuit 170] to perform third operations on the data taking a third amount of time between the one or more input registers and the one or more output registers [0093: While the input signals 710 of the source registers are loaded in the combinational circuit] [0094] [Fig. 10]; and
a first delay circuit configurable to delay a clock signal by a first delay to the one or more input registers or the one or more output registers to enable time borrowing between the first hardened logic circuitry and the first path of the programmable logic circuitry or the second path of the programmable logic circuitry [0093] [0094: Clock manager 720 adds one clock cycle delay though the clock scheduler can also add delay cycles. The total delay cycles lead to a mismatch between the path signals that traverse the combinational circuit 170 and the applied clock cycle period. Extra register levels 700 before the source register level, equal with the delay cycles (as shown in FIG. 11A) permit synchronizing the clock frequency switch exactly on the clock cycle that the corresponding path signals that trigger the clock switch are loaded to the combinational circuit. This technique permits synchronization independently of the number of clock switches without applying any functional change in the original combinational circuit] [Fig. 10].
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Regarding claim 2, Zompakis discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises selection circuitry configurable to select the clock signal or the clock signal delayed by the first delay to provide to the one or more input registers [Fig. 10, 0082, 0093-0094: MUX 720].
Regarding claim 3, Zompakis discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises selection circuitry configurable to select the clock signal or the clock signal delayed by the first delay to provide to respective registers of the one or more output registers [Fig. 10, 0082, 0093-0094: MUX 720].
Regarding claim 4, Zompakis discloses the integrated circuit of claim 1, wherein the hardened logic circuitry comprises a second delay circuit configurable to delay the clock signal by a second delay to the other of the one or more input registers or the one or more output registers [Fig. 10, 0082, 0093-0094: selectable delay clocks].
Regarding claim 5, Zompakis discloses the integrated circuit of claim 4, wherein the first delay is different from the second delay [Fig. 10, 0090-0094: different delayed clocks].
Regarding claim 6, Zompakis discloses the integrated circuit of claim 1, wherein the hardened logic circuit comprises a digital signal processing (DSP) block [abstract, 0019, 0020, 0120-0122: digital processing block].
Regarding claim 7, Zompakis discloses the integrated circuit of claim 1, wherein the hardened logic circuit comprises at least one of a memory block, a processor, an error correction block, or a crypto block [Fig. 10, 0093-0094: storing data in the registers and combination circuit].
Regarding claims 8-10, Zompakis discloses these claims for the same reasons as set forth in claims 1, 3 and 4, respectively.
Regarding claim 11, Zompakis discloses the DSP circuitry of claim 10, comprising: selection circuitry configurable to select whether the first of the plurality of output registers is clocked to the clock signal or to the second delayed clock signal [Fig. 10, 0082, 0093-0094: MUX 720].
Regarding claim 12, Zompakis discloses the DSP circuitry of claim 10, comprising: a third delay circuit configurable to delay the clock signal by a third delay to generate a third delayed clock signal; wherein at least a second of the plurality of output registers is configurable to be clocked to the third delayed clock signal [Fig. 10, 0082, 0093-0094: selectable delay clocks].
Regarding claim 13, Zompakis discloses the DSP circuitry of claim 8, comprising: second hardened logic circuitry to perform a second operation on the data; and a first plurality of pipeline registers between the first hardened logic circuitry and the second hardened logic circuitry [Fig. 9, 0070-0074: intersection nodes 351,352,353 (combination logic circuit)].
Regarding claim 14, Zompakis discloses the DSP circuitry of claim 13, comprising: a second delay circuit configurable to delay the clock signal by a second delay to generate a second delayed clock signal; wherein at least a first of the first plurality of pipeline registers is configurable to be clocked to the second delayed clock signal [Figs. 9 and 10, 0070-0074, 0093-0094: registers are selectively clocked by different delayed clocks].
Regarding claim 15, Zompakis discloses the DSP circuitry of claim 14, comprising: third hardened logic circuitry to perform a second operation on the data; and a second plurality of pipeline registers between the second hardened logic circuitry and the third hardened logic circuitry [Fig. 9, 0070-0074: intersection nodes 351,352,353 (combination logic circuit)].
Regarding claim 16, Zompakis discloses the DSP circuitry of claim 15, wherein at least a first of the second plurality of pipeline registers is configurable to be clocked to the second delayed clock signal [Figs. 9 and 10, 0070-0074, 0093-0094: registers are selectively clocked by different delayed clocks].
Regarding claim 17, Zompakis discloses the DSP circuitry of claim 14, comprising: a third delay circuit configurable to delay the clock signal by a third delay to generate a third delayed clock signal; wherein at least a first of the second plurality of pipeline registers is configurable to be clocked to the third delayed clock signal [Figs. 9 and 10, 0070-0074, 0093-0094: registers are selectively clocked by different delayed clocks].
Pertinent arts
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
John, (US 20120119805 A1) discloses FIG. 3 is a simplified diagram of a tile 110 including a macro 120. The clock tree 130 for the tile is represented by a delay element. The logic devices 170 (e.g., flip flops) of the tile 110 receive the clock from the clock tree 130, and the logic devices 180 of the macro 120 receive the clock from the clock gater 160. In the illustrated embodiment, the clock gater 160 includes a multiplexer 162 and a plurality of delay elements 164-167. The delay elements 164-167 each impose a different amount of delay on the clock signal. The delay elements 164-167 may be implemented using various logic elements, such as shown in the clock tree 130 of FIG. 2.
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Hutton (US 8020027 B1) discloses as shown in FIG. 4, where a plurality of stages are represented by registers 401, 402, 403, each stage can be provided with a programmable clock delay 411, 412, 413 to maximize performance. The values of all delays 411-413 could be made the same, or the value of each delay 411, 412, 413 could be tailored to the operating characteristics of the respective stage, or the delays 411-413 could be adjustable either continuously or to a number of preset values.
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Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/ Primary Examiner, Art Unit 2176