DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2,4-7,10-12,14-17,20-22,24-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Madduri (patent application publication No. 2019/0196826).
Madduri taught the invention as claimed including (as to claim 1) an apparatus (e.g. see fig. 12) comprising: decoder circuitry to decode an instance of a single instruction(1230) (e.g., see fig. 12) , the instance of the single instruction to include one or more fields to reference a first source operand (SRC1)(e.g., see paragraph 0138), one or more fields to reference a second source operand(SRC2)(e.g., paragraph 0138), one or more fields to reference a destination operand (Dest)(e.g., see fig. 14 and paragraph 0139), and one or more fields for an opcode (e.g., see paragraph 0153), the opcode to indicate execution circuitry is to perform addition of data elements of corresponding data element positions of the first and second source operand(e.g., see paragraph 0143) [note Madduri states at paragraph [0143] “In one embodiment, the values in the second source register are physically rotated by the specified amount within the second source register and the resulting rotated values are thereby properly matched with corresponding data element positions in the first source register. That is, following rotation, the signed packed words in the first source register are simply added to the rotated packed signed words in corresponding data element locations in the second source register (e.g., the word at [15:0] in the first source is added to the rotated word at [15:0] in the second source).”]
Madduri taught wherein data elements of the second source operand are to be positionally rotated prior to the addition according to rotation information (e.g., see paragraph 0143 where Madduri states” values in the second source register are physically rotated …following rotation, the signed packed words in the first source register are simply added”);
and Madduri taught a result of each addition is to be stored in a corresponding data element position of the destination operand (e.g., see paragraph 0149); and execution circuitry configured to execute the decoded instruction according to the opcode (e.g., see paragraphs 0144 and 0149 and 0131).
Due to the similarities between claims 1 and 11 and 21; claim 11 and 21 are rejected for the same reasons as claim 1 as detailed above.
As to the further limitation of claim 21 Madduri taught general purpose processor coupled to a digital signal processor (e.g., see paragraphs 0093 and 0097 and 0108 and figs. 7-10).
Furthermore, as to the execution circuitry is further to saturate the result of each addition prior to storage in the destination operand (e.g., see paragraph 004 where Madduri states” a multiply-accumulate may be performed with a multiply instruction, followed by a 4-way addition, and then an accumulation with the destination quadword data to generate two 64-bit saturated results.”; and see fig. 14 and paragraph 0151 where Madduri states
“FIG. 14 such as the multipliers 1405, accumulation circuits 1420-1421, and saturation circuits 1440-1441 are not necessary for executing the described operations. In such cases, it is assumed that data passes through or bypasses these circuits without modification.).
As to claims 2, 12, 22 Madduri taught the apparatus of claim 1, wherein the first source and second source operands are vector registers (e.g., see paragraph 0135).
As to claims 4,14, 24 Madduri taught the apparatus of claim 1, wherein the instance of the single instruction further comprises a field for an immediate, wherein the immediate is to indicate how data elements of the second source operand are to be positionally rotated (e.g., see paragraph 0135 where Madduri states “a vector signed ADD of words in each of two packed data registers with a rotation of the data elements in the second source register as specified by bits in an immediate (e.g., 0°, 90°, 180°, or 270° indicated by imm8[1:0]).”).
As to claims 5,15,25 Madduri taught the apparatus of claim 4, wherein the data elements of the second source operand are to be positionally rotated are to be rotated 0-degrees, 90-degrees, 180-degrees, or 270-degrees (e.g. see paragraph 0135 where Madduri states “a vector signed ADD of words in each of two packed data registers with a rotation of the data elements in the second source register as specified by bits in an immediate (e.g., 0°, 90°, 180°, or 270° indicated by imm8[1:0]).”).
As to claims 6, 16 Madduri taught the apparatus of claim 4, wherein the immediate is to further indicate that the result of each addition is to be halved prior to storage in the destination operand (e.g., see paragraph 0135 where Madduri states “As used herein, an ADD operation refers to the addition of two positive numbers or a subtraction where a negative packed data value is added to a positive value. Depending on the implementation, the result may be halved based on additional immediate bits (e.g., halved if imm8[2] is set) and written to a corresponding word location in a packed destination register, such as xmm1.”).
As to claims 7,17 Madduri taught the apparatus of claim 6, where the result of each addition is to be halved prior to storage in the destination operand by shifting right by 1 bit (e.g. see paragraph 0155 where Madduri states “If this portion of the immediate has a first value (e.g., imm8[2]=1) then the results are halved at 1506 to generate second results. As mentioned, halving the results may comprise shifting each result to the right by 1. At 1507, the first or second results are stored as signed packed word data elements in the destination register.”).
As to claims 10,20 Madduri taught the apparatus of claim 1, wherein the data elements of the first and second source operands are 16-bit in size (e.g., see paragraph 0137) where Madduri states “FIG. 13 illustrates exemplary data element and bit distributions for an exemplary source register and/or destination register (SRCx/DESTx). Data elements may be packed into the source register and/or destination register in words (16 bits), doublewords (32 bits), and/or quadwords (64 bits) as illustrated”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3,13,23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madduri.
As to claims 3,13, 23 Madduri taught the apparatus of claim 1, wherein the first source operand is a vector register and the second source operand is a memory location (e.g., see paragraphs 0135-0136). [note Madduri taught the first and second operand may be stored registers or may be retrieved from memory. Therefore, one of ordinary skill would have been motivated, when the operand to be retrieved from memory, to store the address of the memory location in the register. This provides indirect addressing. There is a finite predictable way of accessing the data from memory including indirect addressing. One of ordinary skill would have been motivated to store the address in the register location to simplify the control of addressing data as the instruction is configured to access the register(s). This reduces the steps to access the address of the data which would reduce time to access the data and therefore increase throughput.
Claim(s) 9,19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Madduri as applied to claim 1 above, and further in view of Hoskote (patent application publication No. 2003/0140072)
As to claim 9,19 Madduri taught the apparatus of claim 1, but did not expressly detail wherein the addition of the data elements of the first and second source operands comprises adding data elements that have been extended by one bit such that the most significant bit of the stored data element is duplicated. Hoskote however tauhght at paragraph 0013] “In one embodiment, overflow prediction is achieved by first sign extending the width N input operands 43, 44 shown in FIG. 1 by 1 bit- essentially duplicating the most significant bit. If the extended operands are added and generate a N+1 bit result, the two most significant bits of the N+1 length result should have the same value. If they are different, the result cannot fit in N bits and has overflowed. FIG. 2 shows the occurrence of overflow in the sum of positive and negative numbers in 2's complement format with N=4 (Note that the most significant bit is not equal to the second most significant bit).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Madduri and Hoskote. Both references were directed to performing addition of operands in a data processor. One of ordinary skill would have been motivated to incorporate the Hoskote teachings of extending the sign bit(s) of operands to be added at least to predict whether overflow would occur which would enable the system to optimize the format of the operands being added and prevent overflow, which would require further error processing, and this would increase throughput.
Response to Arguments
Applicant's arguments filed 12/29/2025 have been fully considered but they are not persuasive at least with respect to the limitations not directed to saturation.
Applicant argues that Madduri does not disclose “wherein the execution circuitry is further to saturate the result of each addition prior to storage in the destination operand, “because Madduri states that “saturation circuits 1440-1441 are not necessary” and that data may pass through or bypass those circuits without modification.
Madduri expressly recognizes saturation in the context of SIMD/DSP arithmetic. In particular, Madduri in paragraph [0004] explains that existing SIMD microarchitectures implement multiply-accumulate operations using a multiply instruction, a 4-way addition, and accumulation with destination quadword data “to generate two 64-bit saturated results.” Thus, Madduri expressly teaches the concept of producing saturated arithmetic results in SIMD packed-data operations.
Further, Madduri’s disclosed DSP architecture includes post-processing of accumulated data by “shift, round, and saturate operations,” confirming that saturation is a contemplated operation in Madduri’s DSP execution architecture. Although paragraph [0151] states that saturation circuits 1440-1441 are not necessary in certain cases and that data may pass through or bypass those circuits without modification, this statement does not teach away from saturation. Rather, it indicates that the disclosed architecture includes saturation circuitry, and that whether saturation is applied depends on the particular instruction/operation being executed.
Accordingly, Madduri reasonably teaches execution circuitry capabable of saturating arithmetic results prior to storage. Applicant’s argument is therefore not persuasive because it focuses only on the option nature of saturation circuits in paragraph [0151] while ignoring Madduri’s express disclosure of saturated SIMD arithmetic results in paragraph [0004] and saturate post-processing in the DSP architecture.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gangalakurti (patent No. 8,447,799) disclosed process for QR transformation using Cordic processor (e.g., see abstract).
Ould-Ahmed-Vall (patent No. 11,294,679) disclosed system for multiplication and accumulation of complex values (e.g., see abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm.
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/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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