DETAILED ACTION
This office action is in response to applicant’s remarks filed on December 22, 2025 in application 17/857,661.
Claims 1-16, 18, 21, and 23-24 are presented for examination. Claims 1, 7, 12, 18, 21, 23 are amended. Claim 24 is newly added. Claims 17, 19-20, 22 are cancelled.
IDS submitted on March 29, 2023 was acknowledged.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed December 22, 2025 have been fully considered but they are not persuasive.
Applicant stated that no new matter has been added with the claim amendments and that applicant’s specification (para. 130) contain support for the amended limitations. Examiner disagreed. See new matter rejection for claim 21.
Furthermore, applicant stated that based on the claimed implementations, the clock switching duration “is at a level of nanosecond ns” and stated that Spada and Peng has not been shown to teach or suggest at least these features of amended claim 1.
Examiner disagreed. The actual claimed limitation stated that “time information of the slave clock device maintained at the communication device.”
Peng et at. teach of the clock distribution apparatus 101 may receive clock signals from more than one clock sources (fig. 1, para. 52). A clock distribution apparatus may be a boundary clock with multiple PTP ports connecting to multiple clock sources (para. 59). Since the clock distribution apparatus receive various messages from clock sources by Sync messages, one of ordinary skilled in the art would be able to equate that the timing information of those clock sources are received at the clock distribution apparatus thus reads on the time information of the slave clock device maintained at the communication device.
For these reasons, the rejections are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 is amended to recite “periodically receiving, by the slave clock device, second indication information from the master clock device, wherein the second indication information indicates that the master clock device is in the faulty state.”
Applicant specification teach of the master clock device periodically sends a synchronization (sync) packet in a normal working state (para. 4). As taught here, the master clock periodically sends sync packet when in a normal working state and not in the faulty state as claimed. Applicant specification further taught master clock sends second indication information to a slave clock based on a working status of the master clock (para. 20), and to stop sending a signal over a link when the master clock device is in a fault state (para. 22). As defined by applicant’s specification, the faulty state cannot be periodically sent because when the master clock device is in a faulty state, the second indication information is stopped from sending.
For the purpose of examination, the amended limitation of “periodically” will not be considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-14, 16-17, 21, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spada et al. (US 2014/0281037) in further view of Peng et al. (US 2022/0094515).
In regard to claim 1, Spada et al. teach a clock switching method, comprising:
monitoring, by a slave clock device, a working status of a master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22), wherein the working status comprises a normal working state or a faulty state (failure to detect or receive the pSync message within expected time period … also refer to as a pSync failure, para. 22); and
in response to determining that the master clock device is in the faulty state, sending, by the slave clock device, first indication information (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
Spada et al. does not explicitly teach wherein the first indication information is carried in a reserved field of a packet sent by the slave clock device, and wherein the first indication information in the reserved field of the packet indicates a communications device to synchronize with a system clock of the communication device based on time information of the slave clock device maintained at the communication device.
Peng et al. teach of switching from the first clock source to a second clock source by generating an output message (para. 75-76, fig. 10a). PTP message may comprises a Sync message (para. 81, 83, fig. 5). A clock distribution apparatus may be a boundary clock with multiple PTP ports connecting to multiple clock sources, such as Grandmaster (GM) or maybe a Slave, and other ports may have a state of “Passive” or “Master” which is decided according to BMCA (best master clock algorithm) (para. 59). The clock distribution apparatus 101 may receive clock signals from more than one clock sources (fig. 1, para. 52). It is noted that the clock distribution apparatus is equated to the claimed communication device where the communication device retains the time information of the slave clock from the packets received.
It would have been obvious to modify the method of Spada et al. by adding Peng et al. clock distribution. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing an output message for the clock distribution apparatus (para. 78, fig. 4).
In regard to claim 2, Spada et al. teach the method according to claim 1, wherein the monitoring, by a slave clock device, a working status of a master clock device comprises: continuously or periodically monitoring, by the slave clock device, the working status of the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
In regard to claim 3, Spada et al. teach the method according to claim 2, wherein the monitoring is continuous, and wherein the continuous monitoring, by the slave clock device, the working status of the master clock device comprises: continuously monitoring, by the slave clock device, the working status of the master clock device by using a signal output over a link connected to the master clock device, wherein the signal comprises an electrical signal or an optical signal, and the signal indicates that the master clock device is in the normal working state; and wherein determining that the master clock device is in the faulty state comprises: if the slave clock device does not receive the signal over the link, determining that the master clock device is in the faulty state (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
In regard to claim 5, Spada et al. teach the method according to claim 2, wherein the monitoring is periodic, and wherein the periodic monitoring, by the slave clock device, the working status of the master clock device comprises:
monitoring, by the slave clock device, the working status of the master clock device in a manner of periodically receiving a first message by using first duration as a periodicity (bGM may detect the pSync message within expected time period, para. 22); and
wherein determining that the master clock device is in the faulty state comprises: if the slave clock device does not successfully receive a next first message within second duration after the slave clock device most recently receives the first message, determining that the master clock device is in the faulty state, wherein the second duration comprises the first duration and first preset duration, and the first duration meets one of the first duration is less than duration between moments for sending two adjacent first synchronization packets by the master clock device to the slave clock device, wherein the first synchronization packet comprises time information of the master clock device; the first duration is less than duration between moments for sending two adjacent first announcement packets by the master clock device to the slave clock device, wherein the first announcement packet comprises capability indication information of the master clock device; the first duration is less than third duration, wherein the third duration is a smaller value in duration between moments for sending two adjacent first synchronization packets by the master clock device to the slave clock device and duration between moments for sending two adjacent first announcement packets by the master clock device to the slave clock device; the first duration is less than duration between moments for sending two adjacent second synchronization packets by the master clock device to a switch device, wherein the second synchronization packet comprises time information of the master clock device; or the first duration is less than duration between moments for sending two adjacent second announcement packets by the master clock device to a switch device, wherein the second announcement packet comprises capability indication information of the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period … the bGM’s timeout period is often shorter than the required hold-over time, para. 22).
In regard to claim 6, Spada et al. teach the method according to claim 1, wherein the sending, by the slave clock device, first indication information comprises one of: sending, by the slave clock device, a second announcement packet, wherein the second announcement packet comprises capability indication information of the slave clock device and the first indication information; and sending, by the slave clock device, a second synchronization packet, wherein the second synchronization packet comprises the time information of the slave clock device and the first indication information (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
In regard to claim 7, Spada et al. teach a clock switching method, comprising: receiving, by a communications device; obtaining, by the communications device, the time information of the slave clock device; and synchronizing, by the communications device, with the system clock of the communications device based on the first indication information and the time information of the slave clock device (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
Spada et al. does not explicitly teach wherein the first indication information is carried in a reserved field of a packet sent by the slave clock device, and instructs the communications device to synchronize with a system clock of the communication device based on time information of the slave clock device maintained at the communication device.
Peng et al. teach of switching from the first clock source to a second clock source by generating an output message (para. 75-76, fig. 10a). PTP message may comprises a Sync message (para. 81, 83, fig. 5). A clock distribution apparatus may be a boundary clock with multiple PTP ports connecting to multiple clock sources, such as Grandmaster (GM) or maybe a Slave, and other ports may have a state of “Passive” or “Master” which is decided according to BMCA (best master clock algorithm) (para. 59). The clock distribution apparatus 101 may receive clock signals from more than one clock sources (fig. 1, para. 52). It is noted that the clock distribution apparatus is equated to the claimed communication device where the communication device retains the time information of the slave clock from the packets received.
Refer to claim 1 for motivational statement.
In regard to claim 8, Spada et al. teach the method according to claim 7, wherein:
duration between a moment for most recently receiving, by the communications device, a first synchronization packet sent by a master clock device and a moment for receiving the first indication information by the communications device is less than duration between moments for receiving two adjacent first synchronization packets; duration between a moment for most recently receiving, by the communications device, a first announcement packet sent by a master clock device and a moment for receiving the first indication information by the communications device is less than duration between moments for receiving two adjacent first announcement packets; duration between a moment for most recently receiving, by the communications device, a first synchronization packet sent by a master clock device and a moment for receiving the first indication information by the communications device is less than third duration, wherein the third duration is a smaller value in duration between moments for receiving two adjacent first synchronization packets and duration between moments for receiving two adjacent first announcement packets; or duration between a moment for most recently receiving, by the communications device, a first announcement packet sent by a master clock device and a moment for receiving the first indication information by the communications device is less than third duration, wherein the third duration is a smaller value in duration between moments for receiving two adjacent first synchronization packets and duration between moments for receiving two adjacent first announcement packets (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period … the bGM’s timeout period is often shorter than the required hold-over time, para. 22).
In regard to claim 9, Spada et al. teach the method according to claim 7, wherein the receiving, by a communications device, first indication information comprises one of:
obtaining, by the communications device, the first indication information based on a received second announcement packet sent by the slave clock device, wherein the second announcement packet comprises capability indication information of the slave clock device and the first indication information; obtaining, by the communications device, the first indication information based on a received second synchronization packet sent by the slave clock device, wherein the second synchronization packet comprises the time information of the slave clock device and the first indication information (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
In regard to claim 10, Spada et al. teach the method according to claim 7, wherein the obtaining, by the communications device, time information of the slave clock device comprises: determining, by the communications device, the time information of the slave clock device from pre-maintained time information of the slave clock device; or receiving, by the communications device, a second synchronization packet sent by the slave clock device, wherein the second synchronization packet comprises the time information of the slave clock device (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
In regard to claim 11, Spada et al. teach the method according to claim 7, wherein after the receiving, by a communications device, first indication information, the method further comprises: sending, by the communications device, the first indication information to another node (end stations such as Ethernet stations … the end stations may also include interfaces for transmission and receipt of message over the network, para. 18).
In regard to claim 12, Spada et al. teach a slave clock device, comprising:
at least one processor (grandmaster clock devices may include one or more processors, para. 43); and
one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor (one or more non-transitory memory devices, para. 43) to:
monitor a working status of a master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22), wherein the working status comprises a normal working state or a faulty state (failure to detect or receive the pSync message within expected time period … also refer to as a pSync failure, para. 22); and
in response to determining that the master clock device is in the faulty state, send first indication information by using a transceiver, wherein the first indication information indicates to synchronize with a system clock based on time information of the slave clock device (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
Spada et al. does not explicitly teach wherein the first indication information is carried in a reserved field of a packet sent by the slave clock device, and wherein the first indication information in the reserved field of the packet indicates a communications device to synchronize with a system clock of the communication device based on time information of the slave clock device maintained at the communication device.
Peng et al. teach of switching from the first clock source to a second clock source by generating an output message (para. 75-76, fig. 10a). PTP message may comprises a Sync message (para. 81, 83, fig. 5). A clock distribution apparatus may be a boundary clock with multiple PTP ports connecting to multiple clock sources, such as Grandmaster (GM) or maybe a Slave, and other ports may have a state of “Passive” or “Master” which is decided according to BMCA (best master clock algorithm)(para. 59). The clock distribution apparatus 101 may receive clock signals from more than one clock sources (fig. 1, para. 52). It is noted that the clock distribution apparatus is equated to the claimed communication device where the communication device retains the time information of the slave clock from the packets received.
Refer to claim 1 for motivational statement.
In regard to claim 13, Spada et al. teach the slave clock device according to claim 12, wherein the programming instructions are for execution by the at least one processor to: continuously or periodically monitor the working status of the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
In regard to claim 14, Spada et al. teach the slave clock device according to claim 13, wherein the programming instructions are for execution by the at least one processor to:
continuously monitor the working status of the master clock device by using a signal output over a link connected to the master clock device, wherein the signal comprises an electrical signal or an optical signal, and the signal indicates that the master clock device is in the normal working state; and if the signal is not received over the link, determine that the master clock device is in the faulty state (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
In regard to claim 16, Spada et al. teach the slave clock device according to claim 12, wherein the programming instructions are for execution by the at least one processor to:
monitor the working status of the master clock device in a manner of periodically receiving a first message by using first duration as a periodicity (bGM may detect the pSync message within expected time period, para. 22); and
if a next first message is not successfully received within second duration after the first message is most recently received, determine that the master clock device is in the faulty state, wherein the second duration comprises the first duration and first preset duration, and the first duration meets one of the first duration is less than duration between moments for sending two adjacent first synchronization packets by the master clock device to the slave clock device, wherein the first synchronization packet comprises time information of the master clock device; the first duration is less than duration between moments for sending two adjacent first announcement packets by the master clock device to the slave clock device, wherein the first announcement packet comprises capability indication information of the master clock device; the first message is different from a first announcement packet, and the first duration is less than third duration, wherein the third duration is a smaller value in duration between moments for sending two adjacent first synchronization packets by the master clock device to the slave clock device and duration between moments for sending two adjacent first announcement packets by the master clock device to the slave clock device; the first duration is less than duration between moments for sending two adjacent second synchronization packets by the master clock device to a switch device, wherein the second synchronization packet comprises time information of the master clock device; or the first duration is less than duration between moments for sending two adjacent second announcement packets by the master clock device to a switch device, wherein the second announcement packet comprises capability indication information of the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period … the bGM’s timeout period is often shorter than the required hold-over time, para. 22).
In regard to claim 17, Spada et al. teach the slave clock device according to claim 12, wherein the transceiver is configured to perform one of: sending a second announcement packet, wherein the second announcement packet comprises capability indication information of the slave clock device and the first indication information; sending a second synchronization packet, wherein the second synchronization packet comprises the time information of the slave clock device and the first indication information (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
In regard to claim 21, Spada et al. teach the method according to claim 1, comprising: periodically receiving, by the slave clock device, second indication information from the master clock device, wherein the second indication information indicates that the master clock device is in the faulty state (in a case of a failure to receive a primary synchronization signal form the pGM. When a pGM fails then a bGM may become the new grandmaster. Switching from the pGM to the bGM may include a controlled phase and frequency deviation, para. 17).
In regard to claim 23, Spada et al. teach the method according to claim 1, wherein the master clock is preconfigured based on a Best Master Clock Algorithm (BMCA) (BMCA may select the pGM in advance and may be preconfigured, para. 15, para. 19), and wherein the slave clock device sends the first indication information without executing a Best Master Clock Algorithm (BMCA) (bMG can be dynamically discovered, para. 17, and may be selected after a pGM failure is detected, para. 19).
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Claims 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spada et al. (US 2014/0281037) in further view of Peng et al. (US 2022/0094515) in further view of Aleman et al. (US 2011/0234417).
In regard to claim 4, Spada et al. teach the method according to claim 2, wherein the monitoring is continuous, and wherein the continuous monitoring, by the slave clock device, the working status of the master clock device comprises: continuously monitoring, by the slave clock device, the working status of the master clock device by using an electrical signal output over a link connected to the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
Spada et al. and Peng et al. does not explicitly teach but Aleman et al. teach wherein the electrical signal comprises a first level signal and a second level signal, the first level signal indicates that the master clock device is in the working state, and the second level signal indicates that the master clock device is in the faulty state (a voltage comparator is connected to a reference voltage, wherein when the voltage is greater than the reference voltage the output of the voltage comparator is at a first logic level, and when the voltage on the voltage comparator is less than or equal to the reference voltage the output of the voltage comparator is at a second logic level (para. 4); and wherein determining that the master clock device is in the faulty state comprises: if the electrical signal received by the slave clock device over the link is the second level signal, determining that the master clock device is in the faulty state (when the voltage storage capacitor is less than or equal to the reference voltage the alarm is issued from the voltage comparator, para. 5).
It would have been obvious to modify the device of Spada et al. and Peng et al. by adding Aleman et al. failsafe oscillator monitor and alarm. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in monitoring and raising an alarm (para. 4-5).
In regard to claim 15, Spada et al. teach the slave clock device according to claim 13, wherein the programming instructions are for execution by the at least one processor to: continuously monitor the working status of the master clock device by using an electrical signal output over a link connected to the master clock device (in passive mode, the bGM may detect the pSync message and upon failure to detect or receive the pSync message within expected time period, para. 22).
Spada et al. and Peng et al. does not explicitly teach but Aleman et al. teach wherein the electrical signal comprises a first level signal and a second level signal, the first level signal in the electrical signal indicates that the master clock device is in the working state, and the second level signal in the electrical signal indicates that the master clock device is in the faulty state (a voltage comparator is connected to a reference voltage, wherein when the voltage is greater than the reference voltage the output of the voltage comparator is at a first logic level, and when the voltage on the voltage comparator is less than or equal to the reference voltage the output of the voltage comparator is at a second logic level (para. 4); and if the electrical signal received over the link is the second level signal, determine that the master clock device is in the faulty state (when the voltage storage capacitor is less than or equal to the reference voltage the alarm is issued from the voltage comparator, para. 5).
Refer to claim 4 for motivational statement.
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Claims 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spada et al. (US 2014/0281037) in further view of Peng et al. (US 2022/0094515) in further view of Yang et al. (US 2016/0156427).
In regard to claim 18, Spada et al. teach a communications device, comprising:
at least one processor (grandmaster clock devices may include one or more processors, para. 43); and
one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor (one or more non-transitory memory devices, para. 43) to: obtain the time information of the slave clock device; and synchronize with the system clock of the communications device based on the first indication information and the time information of the slave clock device (when the pGM failed to send accurate pSync messages, the bGM may continue to send bSync messages to the Ethernet station so the Ethernet station may continue to operate seamlessly based on the continuously received and derive the clock based on the bSync message, para. 24, fig. 2).
Spada et al. does not explicitly teach wherein the first indication information is carried in a reserved field of a packet sent by the slave clock device, and instructs the communications device to synchronize with a system clock of the communication device based on time information of the slave clock device maintained at the communication device.
Peng et al. teach of switching from the first clock source to a second clock source by generating an output message (para. 75-76, fig. 10a). PTP message may comprises a Sync message (para. 81, 83, fig. 5). A clock distribution apparatus may be a boundary clock with multiple PTP ports connecting to multiple clock sources, such as Grandmaster (GM) or maybe a Slave, and other ports may have a state of “Passive” or “Master” which is decided according to BMCA (best master clock algorithm) (para. 59). The clock distribution apparatus 101 may receive clock signals from more than one clock sources (fig. 1, para. 52). It is noted that the clock distribution apparatus is equated to the claimed communication device where the communication device retains the time information of the slave clock from the packets received.
It would have been obvious to modify the method of Spada et al. by adding Peng et al. clock distribution. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing an output message for the clock distribution apparatus (para. 78, fig. 4).
Spada et al. and Peng et al. does not explicitly teach a transceiver, the transceiver configured to receive first indication information sent by a slave clock device.
Yang et al. teach of a node comprises a clock recovery controlling unit and a transceiver adapt to transmit the generated message to the switched backup master clock node for the switch backup master clock node to reselect its master clock node, (para. 36, fig. 6).
It would have been obvious to modify the device of Spada et al. and Peng et al. by adding Yang et al. clock recovery. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in clock recovery (para. 36).
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Claim 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Spada et al. (US 2014/0281037) in further view of Peng et al. (US 2022/0094515) in further view of Kim et al. (US 2016/0149692).
In regard to claim 24, Spada et al. and Peng et al. does not explicitly teach but Kim et al. teach the method according to claim 1, wherein the communications device includes a device of an in-vehicle network (providing time synchronization in an in-vehicle communication network, para. 2-12).
It would have been obvious to modify the device of Spada et al. and Peng et al. by adding Kim et al. time synchronization. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing time synchronization for an in-vehicle communication network where a grandmaster may be rapidly selected (para. 2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Banerjee (US 6,091,804) master/slave clock connected through a modem and switch
Shemesh (US 2004/0167739) slave clocks
Noebauer et al. (US 2015/0134764) sync master to slave clock, in-vehicle network
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Yang (US 2013/0227008) clock synchronization based on grandmaster
Jones et al. (US 9,225,344) aligning clock signals
Doblar et al. (US 6,516,422) slave and master clock failover
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Abdelhameed et al. (US 2023/0353469) synchronizing clocks
Smith et al. (US 2023/0164710) switch roles of master and slave clock
Budnik et al. (US 2023/0092840) switching of master and slave clock
Herber et al. (US 11,539,451) slave clock and switches
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Fong et al. (US 11,502,767) master/slave clock
Whitefield et al. (US 2021/0203412) best master clock algorithm
Sandberg (US 2020/0077355) master/slave clock selection
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Olsen et al. (US 2012/0263263) media clock negotiation
KNORR et al. (US 2020/0073838) master and slave clock
Fair et al. (US 10,263,720) clock synchronization
Lee et al. (US 8,812,256) measure and adjust backup time
Bertacchini et al. (US 6,341,149) backup clock priority
Mizuhara (US 2010/0046959) monitor clock electrical signal degrades level
Wu (US 7,334,149) backup clock monitors the clock signal provided by the master
Vartti et al. (US 5,381,416) standby clock can be switched into place when a clock fails
Wojewoda et al. (US 2019/0114235) determine test clock input to reference clock input to determine faulty
Imran (US 4,667,328) clocking with backup clock source
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
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