DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/19/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 9, 11-14, 16-18, 20-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Manero (US2014/0231127A1) in view of Yi (US2016/0186327A1) as well as, alternatively, over Yi in view of Manero.
Manero discloses (refer to Figs. 3-5B) the claimed invention as follows (limitations not disclosed are crossed out, below):
Claim 1/9. An electronic circuit, comprising:
A 3-dimensional (see Fig. 4L) integrated substrate structure (400) comprising one or more electrically conductive traces (424), the one or more electrically conductive traces comprising:
one or more electrically conductive pads (422) at one or more predetermined positions along the one or more electrically conductive traces, wherein the one or more electrically conductive pads are positioned on the 3-dimensional integrated substrate structure to provide an increased surface contact area between each of the one or more electrically conductive pads and the 3-dimensional integrated substrate structure by having a pad width that is greater than a width of an adjacent portion of a corresponding electrically conductive trace (see Fig. 4L; the pads 422 are wider than the traces 424; see numbering in Fig. 4E) and wherein the one or more electrically conductive pads have a copper dimension thickness for connection with a heat sink to provide increased and even heat dissipation1;
a solder mask layer (426; see Fig. 4G and [0050]) covering the one or more electrically conductive traces and leaving exposed/uncovered the one or more electrically conductive pads;
a protective layer (see Fig. 4H and [0052]-[0060]) covering the one or more electrically conductive pads left exposed by the solder mask layer; and
an electrical component surface mounted to the one or more electrically conductive pads with interconnect and bonding material (e.g., solder; see [0001] and [0002], [0052], [0058]).
Claim 3/11. The electronic circuit of Claim 1/9,
Claim 4/12. The electronic circuit of Claim 1/9,
Claim 5/13. The electronic circuit of Claim 1/9,
Claim 6/14. The electronic circuit of Claim 1/9,
Claim 16. The electronic circuit of Claim 1/9, further comprising: the protective layer covering at least some of the portions of the one or more electrically conductive pads left uncovered by the solder mask layer (see Fig. 4L).
Claim 17. The electronic circuit of Claim 16, wherein the protective layer comprises a glossy plating layer formed from at least one of copper, nickel, or gold. e.g., ENIG in [0060].
Claim 18. The electronic circuit of Claim 16, wherein the protective layer comprises organic solderability preservative. See OSP in [0058].
Claim 21. The electronic circuit of Claim 1, wherein the protective layer comprises organic solderability preservative. See OSP in [0060].
Claim 22. The electronic circuit of Claim 1, wherein the protective layer comprises a glossy plating formed from at least one of copper, nickel, or gold. e.g., ENIG in [0060].
Claim 23. The electronic circuit of Claim 11,
Manero discloses the claimed invention, except for the claim limitations crossed out, above.
Yi teaches a circuit pattern on a substrate, comprising:
as in claims 1 and 9: an integrated substrate structure (3, Fig. 13) comprising one or more electrically conductive traces (see Fig. 13), the one or more electrically conductive traces comprising:
a non-conductive isolation layer (2) formed from an activation ink (see Fig. 3) printed in a pattern forming region (111) of an insulating surface of the integrated substrate structure (see [0024]); a first metal layer (31, Fig. 13) formed on the non-conductive isolation layer; and a second metal layer (32, Fig. 13) formed on a laser-etched (note this is a product-by-process limitation, i.e. it is sufficient for prior art to disclose the structure resulting from the process; however, see [0027]), patterned portion of the first metal layer, wherein the laser-etched, patterned portion is isolated from a remaining portion of the pattern forming region of the insulating surface (see Fig. 11).
as in claims 3 and 11: wherein the laser-etched, patterned portion of the first metal layer is formed by removing part of the first metal layer along an outer periphery of the one or more electrically conductive traces to isolate the one or more electrically conductive traces of the first metal layer. See Fig. 13. Note this is a product-by-process limitation, i.e., it is sufficient for prior art to disclose the structure resulting from the process.
as in claims 4 and 12: wherein the non-conductive isolation layer is electrically non-conductive (see “insulating surface 11” in [0023]).
as in claims 5 and 13: wherein the integrated substrate structure includes a metal base layer (12) and an insulating layer (13) formed on the metal base layer to provide the insulating surface (see [0023]).
as in claims 6 and 14. wherein the activation ink includes N-methyl-2-pyrrolidone (see [0025]).
as in claim 23: wherein the part of the first metal layer and the non-conductive isolation layer is removed by laser ablation (note this is a product-by-process limitation, i.e., it is sufficient for prior art to disclose the structure resulting from the process; however, see [0027]).
The focus of Manero is on improving solderability and prevent oxidation of electrically conductive elements such as plated through holes and surface mount pads for receiving electronic components that are to be soldered to the PCB (see [0001] and [0002]). Whereas, in describing the manufacturing process, Manero describes not just steps pertaining to applying a surface finish to pads and other electrically conductive elements of the PCB but also how the circuit patterns are formed. Manero discloses providing (Fig. 3, step 302) an insulating substrate (404, Fig. 4A) having a copper foil (410) thereon, drilling holes (412, Fig. 4B; Fig. 3, step 304), plating the through holes with copper (Fig. 3, step 306), then patterning (Fig. 3, steps 308 to 319; Figs. 4C-4F) the copper foil by means of photolithography to define the circuits, including pads (422, Fig. 4E) and traces (424, Fig. 4E), applying a solder mask (Fig. 3, step 320; Fig. 4G) and applying the surface finish treatments (Fig. 3, steps 322-330; Figs. 4H-4L) to copper areas not covered by a solder mask.
Yi discloses a conventional process for forming a patterned circuit on a substrate (1), whereby a circuit pattern is formed by applying (see Fig. 3) an activation ink on an insulating surface (11) of the substrate, to form an activator layer (2) only in a pattern-forming region (111). Electroless plating can then be performed (see Fig. 5) on the pattern-forming region, to form an electroless plated layer (31). The electroless metal layer is then patterned (see Fig. 7) to define the circuit pattern, and electroplating is performed (see Fig. 9) to form a metal layer (32) defining the circuit pattern. Also refer to [0023]-[0028].
From the disclosure of Manero one of ordinary skill in the art recognizes as conventional the steps up to and including the applying of the solder mask (compare steps 302-320 of Fig. 3 to steps 102 to 120 of Fig. 1 showing a conventional process). The invention of Manero is in the forming of the finish layers (Fig. 3, steps 322-330), not in the steps of manufacturing the patterned circuit up to the point just prior to applying the finish layers. One of ordinary skill in the art would have found it obvious to replace the conventional steps 302-320 of Fig. 3 with other conventional circuit patterning techniques, such as the process taught by Yi, to obtain the structure of Fig. 4F, as a simple substitution of one known circuit patterning process for another, with predictable results (i.e., obtaining the circuit pattern of Fig. 4F of Manero). See MPEP 2143(I)(B).
Alternatively, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious that the process of Yi is intended to be used to manufacture usable circuits, i.e., having electronic components. One of ordinary skill in the art would have therefore found it obvious to pattern using the technique of Yi circuit traces including pads, as taught by Manero, to which surface-mount components can be soldered, in order to manufacture a useful electronic device.
Claim(s) 19 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Manero, Yi, as applied above, further in view of Cardona (US2008/0121413A1).
Manero and Yi do not mention a silkscreen configured as a reference designator and a pin marker for the electrical component.
However, such a use of a silkscreen is conventional in the art. Please refer to para. [0020] and [0021] of Cardona.
One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to provide the integrated substrate structure discussed above with respect to Manero and Yi with a silkscreen as claimed, for the same purpose as used conventionally in the art (see Cardona [0020] and [0021]).
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are not persuasive.
Applicant argues the prior art does not disclose the newly-added limitations. The examiner respectfully disagrees. The new amendment has not added anything not already disclosed by the cited prior art, as discussed above.
Conclusion
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIVIUS R CAZAN whose telephone number is (571)272-8032. The examiner can normally be reached Monday - Friday noon-8:30 pm ET.
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
1 The language in italics is intended use that does not further limit the structure of the claimed device, other than that it must be capable of use in this manner. The pads are made of copper (copper foil 410 is patterned to form the pads 422; see [0038] and [0049]), which would result in increased and even heat dissipation if connected to a heat sink, compared to if not connected. Note that the specification mentions a heat sink 200 (see [0023] and [0026]) but does not mention connecting pads to it. Therefore, “for connection with a heat sink” is understood to mean thermal connection, as in heat from the pads can be transferred to the heat sink, not that the heat sink would actually be directly connected to the pads. In any case, a connection to a heat sink is not currently required by the claims.