DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Amendment filed on September 14, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-14 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over by Matsuda (US 2018/0190868) in view of Takada et al. (US 2012/0275128, hereinafter Takada), and further in view of Lee et al. (KR 102413303, hereinafter Lee).
Regarding claim 1, Matsuda discloses for a light emitting module comprising that
a support substrate (first support member 30, Fig. 6);
a light emitting diode chip (light emitting part 12, Fig. 6) mounted on a first surface of the support substrate (upper surface of first support member 30, Fig. 6);
a wavelength conversion member (phosphor layer 61, Fig. 6) formed on a light emitting surface of the light emitting diode chip (upper surface of 12, Fig. 6), and a reflection member (reflective member 71, Fig. 6) formed to surround a side surface of the wavelength conversion member (side surface of 61, Fig. 6);
an electrode pad (first or second metal layer 35 or 37, Fig. 6) formed on a second surface of the support substrate (first or second metal layer 35 or 37, Fig. 6) to be electrically connected with the light emitting diode chip (12, Fig. 6), because the first or second metal layer 35 or 37 is electrically connected with the light emitting part 12 through the via electrodes 31 and 33 (Fig. 6);
a conductive bonding material (first or second bonding member 133 or 143, Fig. 6) formed on one surface of the electrode pad (lower surface of 35 or 37, Fig. 6); and
a thermal expansion compensation layer (a composite layer of second support member 40 and first/second lead electrodes 41/43, Fig. 6) formed on one surface of the conductive bonding material (upper surface of 133 or 143, Fig. 6),
wherein the thermal expansion compensation layer (40/41/43, Fig. 6) includes an insulating layer (40, resin material, [0040]), because “the second support member 40 may include a resin material and may be a resin substrate or an insulation substrate” ([0040]), and
wherein the support substrate (30, Fig. 6) is disposed between the light emitting diode chip (12, Fig. 6) and the electrode pad (35 or 37, Fig. 6).
Matsuda differs from the claimed invention by not showing that the thermal expansion compensation layer includes an insulating layer having at least one via hole, a first conductive layer formed on a first surface of the insulating layer and a second conductive layer formed on a second surface of the insulating layer, wherein the first conductive layer and the second conductive layer are electrically connected through the at least one via hole formed through the insulating layer, wherein a portion of the first conductive layer is surrounded by the insulating layer.
However, Takada discloses electronic components and a wiring substrate including a heat insulating layer 17 and a thermal diffusion layer 18 formed between a second wiring layer 14 and an external connection terminal 24 (Fig. 1), and the composite layer of the heat insulating layer 17 and the thermal diffusion layer 18 can correspond to the claimed thermal expansion compensation layer. Also, the second wiring layer 14 and the external connection terminal 24 further correspond to the claimed electrode pad and conductive bonding material, respectively (Fig. 1). Takada expressly teaches that “examples of the material of the heat insulating layer 17 may include low thermal conductivity ceramics such as aluminum titanate (AlTiO3) and zirconia (ZrO2), and polyimide resin” ([0055]), and these materials are electrically insulating materials having good thermal management properties for the semiconductor packaging applications. Accordingly, the heat insulating layer 17 can correspond to the claimed insulating layer. Takada further discloses that the third wiring layer 16 disposed on a top surface of the heat insulating layer 17 and the external electrode 21 disposed on a bottom surface of the heat insulating layer 17, wherein the third wiring layer 16 and the external electrode 21 are electrically connected through the third through-wire 17x extending through the heat insulating layer 17 and thermal diffusion layer 18. Accordingly, the third wiring layer 16 corresponds to the claimed first conductive layer, the external electrode 21 corresponds to the claimed second conductive layer, and the third through-wire 17x corresponds to the claimed at least one via hole. Further, Takada teaches that the third wiring layer 16 and the third through-wire 17x may be made of the same conductive material, such as copper (Cu) and aluminum (Al) ([0047]), and as illustrated in Fig. 1, the third wiring layer 16 may be continuous with and include an upper portion of the third through-wiring 17x, therefore, a portion of the third wiring layer 16 extends into and is surrounded by the heat insulating layer 17, which corresponds to the claimed insulating layer. Therefore, in view of Takada, one of ordinary skill in the art would have recognized that the thermal management structure of Takada can be incorporated into the package structure of Matsuda, to manage heat and accommodate thermal effects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring structure of Matsuda in view of Takada by incorporating the heat insulation layer, thermal diffusion layer and conductive structures, in order to improve heat dissipation and reduce thermal stress resulting from mismatches in coefficients of thermal expansion (CTE), and therefore, one of ordinary skill in the art would have a motivation to combine the teachings of Matsuda and Takada with a reasonable expectation of success in optimizing the thermal performance of the semiconductor LED device.
Further regarding claim 1, Matsuda in view of Takada does not explicitly disclose that a corner portion of the electrode pad is curved with a radius of curvature in a top view.
However, Lee discloses a semiconductor device package including the semiconductor device 130 formed on the resin layer 240 (Fig. 5a). Lee further discloses that the semiconductor device may include light emitting diodes or laser diodes ([0003]), therefore, the semiconductor device 130 corresponds to the claimed light emitting diode chip. Also, Lee expressly discloses that “the resin layer 240 may include a plurality of openings” ([0063]), therefore, the resin layer 240 can correspond to the claimed support substrate. Lee further discloses the first electrode pad 231 and second electrode pad 232 disposed on a lower surface of the resin layer 240 and electrically connected to the semiconductor device 130 through the first and second conductive layers 251 and 252, respectively, therefore, the first or second electrode pad 231 or 232 corresponds to the claimed electrode pad. As illustrated in Fig. 3 of a plan view (i.e., top view), the electrode pads 231 and 232 have curved corner portion having a radius of curvature r2. Lee further teaches that “the radius of curvature r2 of the electrode pad 230 may be 0.4 mm or more and 0.6 mm or less. When the radius of curvature r2 of the electrode pad 230 is 0.4 mm or more, as the curvature is included, damage to the resin layer 240 can be prevented, thereby improving the reliability of the semiconductor device package” ([0135-0136], see attached machine-translated copy). Therefore, one of ordinary skill in the art would have recognized that the metal layer configuration of Matsuda can be modified with a curved corner portion having a radius of curvature, as taught by Lee, to reduce damage to adjacent layers or substrate, thereby improving the package reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer of Matsuda to include a curved corner portion having a radius of curvature in a top view, as taught by Lee, in order to reduce damage to the surrounding package structure and improve the reliability of the semiconductor LED package.
Regarding claim 2, Matsuda further discloses that the support substrate (30, Fig. 6) is implemented with a ceramic material including AlN (“AlN”, [0041]), and the reflection member (71, Fig. 6) is implemented with a silicon material.
Matsuda does not explicitly disclose a silicon material having a white color.
However, Matsuda further discloses that “the reflective member 71 may include a non-metal material or an insulating material, and for example, may be formed of a resin material such as silicon or epoxy. The reflective member 71 may include impurities having a refractive index which is higher than that of the resin material. At least one of compounds such as oxide, nitride, fluoride, and sulfide having at least one of Al, Cr, Si, Ti, Zn, and Zr may be added to the reflective member 71. The reflective member 71 may include, for example, at least one of TiO2, SiO2, and Al2O3” (emphasis added, [0083]) and it is obvious to one of ordinary skill in the art that the white color reflects light better than other colors and additives such as TiO2 or Al2O3 in a silicon material can form white-colored silicon resin material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a white-colored silicon resin material for the reflective layer in LED device, as disclosed by Matsuda, in order to improve optical properties and overall performance of the LED device.
Regarding claim 5, Matsuda further discloses that the electrode pad (35 or 37, Fig. 6) includes a pair of first (35, Fig. 6) and second electrode pads (37, Fig. 6) which are electrically connected with the light emitting diode chip (12, Fig. 6) corresponding to the electrode pad (35/37, Fig. 6), because the first and second metal layers 35 and 37 are electrically connected with the light emitting part 12 through the via electrodes 31 and 33 (Fig. 6).
Regarding claim 9, Matsuda further discloses that the insulating layer (40, Fig. 6) is implemented with a polyimide material whose coefficient of thermal expansion is relatively small as compared to the electrode pad (35/37, Fig. 6) and conductive bonding material (133/143, Fig. 6), because “the second support member 40 may include a thermal conductive film. The thermal conductive film may use polyester resins such as polyethylene terephthalate, polybutylene terephthalate-laid, and polyethylene terephthalate; polyimide resin; acrylic resin; styrene-based resin such as polystyrene and acrylonitrile-styrene; polycarbonate resin; polylactic acid resin; polyurethane resin, etc” (emphasis added, [0048]).
Regarding claim 10, Takada further discloses that the first conductive layer (16, Fig. 1) and the second conductive layer (21, Fig. 1) are implemented with a same material as the electrode pad (14, Fig. 1), because “examples of the material of the first wiring layer 12, the second wiring layer 14, the third wiring layer 16, the fourth wiring layer 20, the first through-wire 13x, the second through-wire 15x, and the third through-wire 17x may include conductive materials such as copper (Cu) and aluminum (Al)” ([0047]) and each is implemented in a pattern shape which has a same width and shape as the electrode pad, because as shown in Fig. 1 of Takada, the second wiring layer 14 (claimed electrode pad), third wiring layer 16 (claimed first conductive layer), and external electrode 21 (claimed second conductive layer) have substantially the same shape and width (Fig. 1).
Regarding claim 11, Takada further discloses that the insulating layer (17/18, Fig. 1) is implemented in a pattern of a shape which protrudes by a predetermined distance out of the first conductive layer (16, Fig. 1) and the second conductive layer (21, Fig. 1) when viewed on a cross-section, because Applicant do not specifically claim what the pattern of shape the insulating layer has, what the patterned shape of the insulating layer looks like, and/or what the predetermined distance refers to, the heat insulating layer 17 and the thermal diffusion layer 18 exhibit a rectangular shape and are extended out of the third wiring layer 16 and the external electrode 21 viewed on a cross-section in Fig. 1.
Regarding claim 12, Matsuda discloses for a light emitting module comprising that
a light emitting diode chip (light emitting part 12, Fig. 6) mounted on a first surface of a support substrate (upper surface of first support member 30, Fig. 6);
a wavelength conversion member (phosphor layer 61, Fig. 6) formed on a light emitting surface of the light emitting diode chip (upper surface of 12, Fig. 6), and a reflection member (reflective member 71, Fig. 6) formed to surround a side surface of the wavelength conversion member (side surface of 61, Fig. 6);
an electrode pad (first or second metal layer 35 or 37, Fig. 6) formed on a second surface of the support substrate (lower surface of 30, Fig. 6) to be electrically connected with the light emitting diode chip (12, Fig. 6), because the first or second metal layer 35 or 37 is electrically connected with the light emitting part 12 through the via electrodes 31 and 33 (Fig. 6);
a circuit board (light emitting chip 111, Fig. 6) formed with a circuit pattern (circuit board pads 131 and 141, Fig. 6) which is electrically connected with the electrode pad (35 or 37, Fig. 6), because the circuit board pads 131 and 141 by Matsuda are electrically connected with the first and second metal layers 35 and 37 through the first/second bonding members 133/143 and the first/second lead electrodes 41/43 (Fig. 6);
a conductive bonding material (first or second bonding member 133 or 143, Fig. 6) formed between the electrode pad (35 or 37, Fig. 6) and the circuit pattern (131 or 141, Fig. 6) to electrically connect the electrode pad (35 or 37, Fig. 6) and the circuit pattern (131 or 141, Fig. 6); and
a thermal expansion compensation layer (a composite layer of second support member 40 and first/second lead electrodes 41/43, Fig. 6) included between the electrode pad (35 or 37, Fig. 6) and the conductive bonding material (133 or 143, Fig. 6),
wherein coefficients of thermal expansion of the support substrate (CTE of 30, Fig. 6), the electrode pad (35 or 37, Fig. 6) and the conductive bonding material (133 or 143, Fig. 6) are different, because the first support member 30 by Matsuda includes AlN ([0057]), “the first and second metal layers 35 and 37 may include at least one of gold (Au), copper (Cu), titanium (Ti), and nickel (Ni)” ([0045]), and the first and second bonding members 133 and 143 include “at least one of gold (Au), tin (Sn), plumbum (Pb), copper (Cu), bismuth (Bi), indium (In), and silver (Ag)” ([0122]), therefore, each of these elements can be made of different material, and therefore, the coefficient of thermal expansion would be different each other, and
a coefficient of thermal expansion gradually increases from the support substrate (30, Fig. 6) to the circuit board (111, Fig. 6), because the first support member 30 by Matsuda can be made of AlN ([0057]) and a coefficient of thermal expansion (CTE) of AlN is approximately 4-5 ppm/°C (Examiner’s search result), the first/second bonding members 133/143 can be made of copper ([0122]) and a CTE of copper is approximately 16.5 ppm/°C (Examiner’s search result), therefore, CTE would gradually increase from the first support member 30 to the circuit board 111, which correspond to the claimed support substrate and circuit board,
wherein the support substrate (30, Fig. 6) is disposed between the light emitting diode chip (12, Fig. 6) and the electrode pad (35 or 37, Fig. 6),
wherein the thermal expansion compensation layer (40/41/43, Fig. 6) includes an insulating layer (40, resin material, [0040]), because “the second support member 40 may include a resin material and may be a resin substrate or an insulation substrate” ([0040]) which
Matsuda differs from the claimed invention by not showing that the thermal expansion compensation layer has at least one via hole, a first conductive layer which is formed on a first surface of the insulating layer and a second conductive layer which is formed on a second surface of the insulating layer, and the first conductive layer and the second conductive layer are electrically connected through the at least one via hole formed through the insulating layer.
However, Takada discloses electronic components and a wiring substrate including a heat insulation layer 17 and a thermal diffusion layer 18 formed between a second wiring layer 14 and an external connection terminal 24 (Fig. 1), and the composite layer of the heat insulation layer 17 and the thermal diffusion layer 18 can correspond to the claimed thermal expansion compensation layer. Also, the second wiring layer 14 and external connection terminal 24 can correspond to the claimed electrode pad and conductive bonding material, respectively (Fig. 1). Takada expressly teaches that “examples of the material of the heat insulating layer 17 may include low thermal conductivity ceramics such as aluminum titanate (AlTiO3) and zirconia (ZrO2), and polyimide resin” ([0055]), and these materials are electrically insulating materials having good thermal management properties for the semiconductor packaging applications. Accordingly, the heat insulating layer 17 can correspond to the claimed insulating layer. Takada further discloses that the third wiring layer 16 disposed on a top surface of the heat insulating layer 17 and the external electrode 21 disposed on a bottom surface of the heat insulating layer 17, wherein the third wiring layer 16 and the external electrode 21 are electrically connected through the third through-wire 17x extending through the heat insulating layer 17 and thermal diffusion layer 18. Accordingly, the third wiring layer 16 corresponds to the claimed first conductive layer, the external electrode 21 corresponds to the claimed second conductive layer, and the third through-wire 17x corresponds to the claimed at least one via hole. Therefore, in view of Takada, one of ordinary skill in the art would have recognized that the thermal management structure of Takada can be incorporated into the package structure of Matsuda, to manage heat and accommodate thermal effects.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the wiring structure of Matsuda in view of Takada by incorporating the heat insulation layer, thermal diffusion layer and conductive structures, in order to improve heat dissipation and reduce thermal stress resulting from mismatches in coefficients of thermal expansion (CTE), and therefore, one of ordinary skill in the art would have a motivation to combine the teachings of Matsuda and Takada with a reasonable expectation of success in optimizing the thermal performance of the semiconductor LED device.
Further regarding claim 12, Matsuda in view of Takada does not explicitly disclose that a corner portion of the electrode pad is curved with a radius of curvature in a top view.
However, Lee discloses a semiconductor device package including the semiconductor device 130 formed on the resin layer 240 (Fig. 5a). Lee further discloses that the semiconductor device may include light emitting diodes or laser diodes ([0003]), therefore, the semiconductor device 130 corresponds to the claimed light emitting diode chip. Also, Lee expressly discloses that “the resin layer 240 may include a plurality of openings” ([0063]), therefore, the resin layer 240 can correspond to the claimed support substrate. Lee further discloses the first electrode pad 231 and second electrode pad 232 disposed on a lower surface of the resin layer 240 and electrically connected to the semiconductor device 130 through the first and second conductive layers 251 and 252, respectively, therefore, the first or second electrode pad 231 or 232 corresponds to the claimed electrode pad. As illustrated in Fig. 3 of a plan view (i.e., top view), the electrode pads 231 and 232 have curved corner portion having a radius of curvature r2. Lee further teaches that “the radius of curvature r2 of the electrode pad 230 may be 0.4 mm or more and 0.6 mm or less. When the radius of curvature r2 of the electrode pad 230 is 0.4 mm or more, as the curvature is included, damage to the resin layer 240 can be prevented, thereby improving the reliability of the semiconductor device package” ([0135-0136], see attached machine-translated copy). Therefore, one of ordinary skill in the art would have recognized that the metal layer configuration of Matsuda can be modified with a curved corner portion having a radius of curvature, as taught by Lee, to reduce damage to adjacent layers or substrate, thereby improving the package reliability.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metal layer of Matsuda to include a curved corner portion having a radius of curvature in a top view, as taught by Lee, in order to reduce damage to the surrounding package structure and improve the reliability of the semiconductor LED package.
Regarding claim 13, Matsuda further discloses that the support substrate (30, Fig. 6) is implemented with a ceramic material including AlN (“AlN”, [0041]), and the reflection member (71, Fig. 6) is implemented with a silicon material.
Matsuda does not explicitly disclose a silicon material having a white color.
However, Matsuda further discloses that “the reflective member 71 may include a non-metal material or an insulating material, and for example, may be formed of a resin material such as silicon or epoxy. The reflective member 71 may include impurities having a refractive index which is higher than that of the resin material. At least one of compounds such as oxide, nitride, fluoride, and sulfide having at least one of Al, Cr, Si, Ti, Zn, and Zr may be added to the reflective member 71. The reflective member 71 may include, for example, at least one of TiO2, SiO2, and Al2O3” (emphasis added, [0083]) and it is obvious to one of ordinary skill in the art that the white color reflects light better than other colors and additives such as TiO2 or Al2O3 in a silicon material can form white-colored silicon resin material.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a white-colored silicon resin material for the reflective layer in LED device, as disclosed by Matsuda, in order to improve optical properties and overall performance of the LED device.
Regarding claim 14, Matsuda further discloses that the electrode pad (35 or 37, Fig. 6) includes a pair of first (35, Fig. 6) and second electrode pads (37, Fig. 6) which are electrically connected with the light emitting diode chip (12, Fig. 6) corresponding to the electrode pad (35/37, Fig. 6), because the first and second metal layers 35 and 37 are electrically connected with the light emitting part 12 through the via electrodes 31 and 33 (Fig. 6).
Regarding claim 18, Matsuda further discloses that the insulating layer (40, Fig. 6) is implemented with a polyimide material whose coefficient of thermal expansion is relatively small as compared to the electrode pad (35/37, Fig. 6) and conductive bonding material (133/143, Fig. 6), because “the second support member 40 may include a thermal conductive film. The thermal conductive film may use polyester resins such as polyethylene terephthalate, polybutylene terephthalate-laid, and polyethylene terephthalate; polyimide resin; acrylic resin; styrene-based resin such as polystyrene and acrylonitrile-styrene; polycarbonate resin; polylactic acid resin; polyurethane resin, etc” (emphasis added, [0048]).
Regarding claim 19, Takada further discloses that the first conductive layer (16, Fig. 1) and the second conductive layer (21, Fig. 1) are implemented with a same material as the electrode pad (14, Fig. 1), because “examples of the material of the first wiring layer 12, the second wiring layer 14, the third wiring layer 16, the fourth wiring layer 20, the first through-wire 13x, the second through-wire 15x, and the third through-wire 17x may include conductive materials such as copper (Cu) and aluminum (Al)” ([0047]) and each is implemented in a pattern shape which has a same width and shape as the electrode pad, because as shown in Fig. 1 of Takada, the second wiring layer 14 (claimed electrode pad), third wiring layer 16 (claimed first conductive layer), and external electrode 21 (claimed second conductive layer) have substantially the same shape and width (Fig. 1).
Regarding claim 20, Takada further discloses that the insulating layer (17/18, Fig. 1) is implemented in a pattern of a shape which protrudes by a predetermined distance out of the first conductive layer (16, Fig. 1) and the second conductive layer (21, Fig. 1) when viewed on a cross-section, because Applicant do not specifically claim what the pattern of shape the insulating layer has, what the patterned shape of the insulating layer looks like, and/or what the predetermined distance refers to, the heat insulating layer 17 and the thermal diffusion layer 18 exhibit a rectangular shape and are extended out of the third wiring layer 16 and the external electrode 21 viewed on a cross-section in Fig. 1.
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuda (US 2018/0190868) in view of Takada et al. (US 2012/0275128, hereinafter Takada), and further in view of Lee et al. (KR 102413303, hereinafter Lee) as applied to claims 1 and 12, and further in view of Kim et al. (KR 20140078823, hereinafter Kim) The teachings of Matsuda in view of Takada, and further in view of Lee are discussed above.
Regarding claim 6, Matsuda further discloses that the first and second electrode pads (35 and 37, Fig. 3) are formed on the second surface of the support substrate (bottom surface of 30, Fig. 3) to be vertically or horizontally symmetrical to each other (Fig. 3).
Matsuda in view of Takada, and further in view of Lee does not explicitly disclose that the first and second electrode pads have a same polarity.
However, Kim discloses LED package structure including the first electrode pad 250 positioned between the light emitting device 100 and the body 210 (Fig. 3), and further teaches that “when the plurality of light emitting devices 100 are connected in parallel to each other, the plurality of first electrode pads 250 are electrically connected to each other with the same polarity in the body 210” (emphasis added, [0104]), therefore, Kim expressly recognizes that electrode pads associated with the LED devices connected in parallel are maintained at the same polarity to provide proper electrical operation of the LED package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure electrode pads connected to parallelly connected LED devices to have the same polarity, as taught by Kim, in order to ensure proper electrical performance and reliable operation of the LED package.
Regarding claim 15, claim 15 is rejected for the same reason stated in claim 6 above.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/WOO K LEE/Examiner, Art Unit 2815
