DETAILED ACTION
Response to Arguments
Applicant’s arguments, see page 1 of the remarks, filed September 23, 2025, with respect to specification objections have been fully considered and are persuasive. The objection of the specification has been withdrawn.
Applicant’s arguments, see page 1 of the remarks, filed September 23, 2025, with respect to claim objections have been fully considered and are persuasive. The objection of claims 1-7 has been withdrawn.
Applicant’s arguments, see pages 1 and 2 of the remarks, filed September 23, 2025, with respect to claim rejections under 35 U.S.C. §112(a) and under 35 U.S.C. §112(b) have been fully considered and are persuasive. The rejection of claims 1-21 has been withdrawn.
Claim Objections
Claims 5-6 and 9-13 are objected to because of the following informalities:
Line 1 of claims 5, 9, 10, 12, and 13, “further including” should be “further comprising” in consistence with “comprising” recited in the preamble of the independent claims 1 and 8.
Claim 6 depends from claim 5, therefore it is also objected.
Claim 11 depends from claim 10, therefore it is also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 8, 10, and 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bai et al. (US 2021/0313993 A1), herein “Bai”.
Bai illustrates alternative cross-clock-domain processing circuits in Figures 2, 3, 8, and 10. For example, the cross-clock-domain processing circuit shown in Figure 8 comprises a first device 210, a re-timer 300, and a second device 220. The re-timer 300 performs data transmission from the first device 210 to the second device 220 and also performs data reception from the second device 220 to the first device 210 (see the embodiments shown in Figures 2 and 10). The re-timer 300 comprises: a receiver circuit 310 including an equalizer 316, a first clock circuit 318, a clock recovery circuit 312, and a serial-to-parallel conversion circuit 314; a data processing circuit 350; a data selector 360; and a transmitter circuit 320 including a jitter filtering circuit 330, a synchronization circuit 340, and a parallel-to-serial conversion circuit 370.
Figure 4 shows a jitter filtering circuit 330 according to the embodiments of Figures 3 and 8 comprising: a frequency divider (DIV) 332; a jitter filtering phase-locked loop 334; and a phase interpolator (PI) 336.
Figure 6 shows a jitter filtering phase-locked loop 334 of the jitter filtering circuit 330 shown in Figure 4.
Regarding claim 1, as shown in Figure 8, Bai illustrates a system (cross-clock-domain processing circuit) for communication link synchronization, the system comprising: a first re-timer (re-timer 300) configured to perform a first clock signal recovery (by the clock recovery circuit 312) of a first clock signal (generated by the first clock circuit 318) subsequent to exiting a low-power communication link mode (a clock recovery circuit (CRC), often implemented as a Clock and Data Recovery (CDR) circuit using a Phase-Locked Loop (PLL), inherently needs to re-establish synchronization and perform a clock signal recovery sequence after exiting a low-power mode); a receiver (the second device 220) configured to generate a clock modulation enablement control signal (the second device 220 coupled after the clock recovery (CR) circuit 312 inherently uses the recovered clock to sample and clean up the incoming data from the first device 210, generating a control signal (the recovered clock itself) that aligns the receiver's timing, but it's the CR circuit's internal components (like PLLs/VCOs) that generate this synchronized clock, often using phase/frequency error signals to adjust themselves to match the data's rate, essentially making the data stream itself the "enable" for precise sampling and recovery. Therefore, the second device 220 (receiver's CDR function) inherently generates the necessary timing (a recovered clock) that controls when data is sampled and processed, acting as the enablement signal for the data path) responsive to the first clock signal recovery; and a transmitter (the first device 210) configured to send communication data through the first re-timer (30) to the receiver (the second device 220) in response to receiving the clock modulation enablement control signal (shown in Figures 2 and 10).
Regarding claim 8, claim 8 is a method claim and the claim features recited in the method steps are similar to the claim features recited in the apparatus claim 1 for the similar reasons described in claim 1 above.
Regarding claims 3 and 10, although Bai does not explicitly show or teach that
the first re-timer further configured to switch the first clock signal from a first local re-timer clock signal to a first recovered clock signal in response to completion of the first clock signal recovery and generate a first re-timer data based on the first clock signal,
that's essentially what a re-timer does: inherently, it uses Clock and Data Recovery (CDR) to extract a clock from the incoming degraded signal, then uses its own local clock to re-time the recovered data, creating a clean, re-generated data signal, effectively switching from the messy local clock (for initial capture) to the precisely recovered clock for retransmission. This process removes jitter and noise, allowing signals to travel much further.
Regarding claims 4 and 11, as shown in Figure 8, the receiver (second device 220) further configured to generate the clock modulation enablement control signal based on the first re-timer data (generated by the clock recovery circuit 312). A receiver,
as described in paragraph [0082], particularly in high-speed digital systems (like SerDes for Ethernet, PCIe), inherently performs CDR, which involves generating a clean, synchronized clock from the incoming, potentially jittery data stream to sample it accurately, and this recovered clock signal essentially serves as the enablement for data processing, acting like an internal “clock modulation enablement” by providing precise timing, often using a Phase-Locked Loop (PLL). While not always called “modulation enablement,” the CDR's job is to create a stable timing reference from data transitions, allowing the re-timer to re-clock data for clean transmission forward. Therefore, the receiver's CDR function inherently generates the necessary timing (a recovered clock) that controls when data is sampled and processed, acting as the enablement signal for the data path.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7, 12-15, and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Bai in view of SHOOR et al. (US 2017/0366468 A1), hereinafter “Shoor).
Regarding claim 15, as described in claim 1 above, although Bai illustrates a cross-clock-domain processing circuit shown in Figure 8 comprises a first device 210, a re-timer 300, and a second device 220 configured to perform the similar claim features performed by the processor circuitry as recited in claim 1, Bai fails to show or teach that at least one non-transitory machine-readable storage medium, comprising instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the processor circuitry to perform the claim functions.
Shoor illustrates a high-level link with low latency re-timer in Figure 1 for systems similar to Bai’s cross-clock-domain processing circuit of Figure 8 comprising: a downstream port 1010 (e.g., Host); a first re-timer 102; a second re-timer 103; and an uplink port 104 (e.g., Device).
Shoor further illustrates a smart device or a computer system or a SoC (System-on-Chip) in Figure 8 with one or more low latency re-timers comprising at least a memory subsystem 1660 and a processor 1610, and teaches in paragraph [0056] that the processor 1610 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by the processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Shoor further teaches in paragraphs [0062] and [0063] that the memory subsystem 1660 (as a machine-readable medium) can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Bai’s cross-clock-domain processing circuit as taught by Shoor to include at least a non-transitory machine-readable storage medium (memory device), comprising instructions that, responsive to being executed with processor circuitry of a computer-controlled device, cause the processor circuitry to perform the operations by Bai’s first device 210, re-timer 300, and second device 220 described in claim 1 in order to enable deep signal analysis, protocol awareness, and intelligent regeneration of high-speed data, allowing it to clean up degraded signals (jitter, noise) and extend connection distances, crucial for modern standards like, by reconstructing data with a clean clock rather than just amplifying it. The processor runs logic (like Equalization & CDR) that understands the data's protocol, while memory buffers data to precisely manage timing and create a perfect, fresh copy of the signal for reliable transmission.
Regarding claim 17, similar to claim 3 described above, although Bai does not explicitly show or teach that the instructions further causing the processor circuitry to: switch, at the first re-timer, the first clock signal from a first local re-timer clock signal to a first recovered clock signal in response to completion of the first clock signal recovery; and generate, at the first re-timer, a first re-timer data based on the first clock signal, again, that's essentially what a re-timer does: inherently, it uses Clock and Data Recovery (CDR) to extract a clock from the incoming degraded signal, then uses its own local clock to re-time the recovered data, creating a clean, re-generated data signal, effectively switching from the messy local clock (for initial capture) to the precisely recovered clock for retransmission. This process removes jitter and noise, allowing signals to travel much further.
Regarding claim 18, as shown in Figure 8, and similar to claim 4 described above, the receiver (second device 220) further configured to generate the clock modulation enablement control signal based on the first re-timer data (generated by the clock recovery circuit 312). A receiver, as described in paragraph [0082], particularly in high-speed digital systems (like SerDes for Ethernet, PCIe), inherently performs CDR, which involves generating a clean, synchronized clock from the incoming, potentially jittery data stream to sample it accurately, and this recovered clock signal essentially serves as the enablement for data processing, acting like an internal “clock modulation enablement” by providing precise timing, often using a Phase-Locked Loop (PLL). While not always called “modulation enablement,” the CDR's job is to create a stable timing reference from data transitions, allowing the re-timer to re-clock data for clean transmission forward. Therefore, the receiver's CDR function inherently generates the necessary timing (a recovered clock) that controls when data is sampled and processed, acting as the enablement signal for the data path.
Regarding claim 5 (as applied to claims 1, 3 and 4), claim 12 (as applied to claims 8, 10 and 11), and claim 19 (as applied to claims 15, 17 and 18), Bai fails to show or teach that the cross-clock-domain processing circuit shown in Figure 8 further including a second re-timer configured to: perform a second clock signal recovery of a second clock signal subsequent to receiving the first re-timer data; switch the second clock signal from a second local re-timer clock signal to a second recovered clock signal in response to completion of the second clock signal recovery; and generate a second re-timer data based on the second clock signal.
Shoor illustrates a high-level link with low latency re-timer in Figure 1 for systems similar to Bai’s cross-clock-domain processing circuit of Figure 8 comprising: a downstream port 1010 (e.g., Host); a first re-timer 102; a second re-timer 103; and an uplink port 104 (e.g., Device). Clearly, the second re-timer 103 is connected between the first re-timer 102 and the device 104, and a re-timer is well known in the communications art.
The statement describes a common operational sequence for a second re-timer in a cascaded system, and this sequence is generally true for how such devices function to maintain signal integrity. This process is fundamental to how re-timers work in series to extend the reach and integrity of high-speed data links, such as those used in systems following standards like PCI Express (PCIe) or USB4.
Inherent functions of a second re-timer coupled after a first re-timer typically include:
Second Clock Signal Recovery: The second re-timer must recover the clock signal (the second clock signal) from the incoming (retimed) data stream it receives from the first re-timer. This is necessary because the signal may have experienced jitter and degradation even after the first re-timing.
Clock Switching: Upon successfully locking onto and recovering the embedded clock from the incoming data stream, the re-timer switches from an internal reference clock (local re-timer clock signal) to the more accurate, newly recovered clock signal. This synchronized clock is crucial for correctly sampling the data.
Second Re-timer Data Generation: The device uses this stable, recovered clock to re-time the incoming data, generating a clean, de-risked (lower jitter) output data stream (the second re-timer data) for transmission further down the link.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Bai’s cross-clock-domain processing circuit as taught by Shoor to include a second re-timer connected between Bai’s re-timer 300 and the second device 220 to perform a second clock signal recovery of a second clock signal subsequent to receiving the first re-timer data, switch the second clock signal from a second local re-timer clock signal to a second recovered clock signal in response to completion of the second clock signal recovery, and generate a second re-timer data based on the second clock signal to recover the clock signal (the second clock signal) from the incoming (retimed) data stream it receives from the first re-timer in order to further reduce the signal may have experienced jitter and degradation even after the first re-timing.
Regarding claim 6 (as applied to claim 5), claim 13 (as applied to claim 12), and claim 20 (as applied to claim 19), as shown in Figure 8 of Bai’s cross-clock-domain processing circuit, inherently, after including a second re-timer, the receiver (second device 220) further configured to generate the clock modulation enablement control signal based on the second re-timer data.
Regarding claim 7 (as applied to claim 1), claim 14 (as applied to claim 8), and claim 21 (as applied to claim 15), although Bai does not explicitly show or teach that the transmitter (first device 210), the first re-timer (300), and the receiver (second device 220) form a universal serial bus (USB) communication link, as described in at least paragraph [0082], an embodiment of this application further provides a re-timer chip, configured to relay a data signal on a high-speed serial transmission link and filter out a jitter.
Shoor illustrates a low-latency re-timer in Figure 3 and shown as a USB re-timer 300 which may apply to the first re-timer 102 and the second re-timer 103 shown in Figure 1.
Re-timers are often used in modern, high-speed USB links (USB 3.x and USB4) to boost and clean up the signal over longer distances or through complex connections (like docking stations). They regenerate the data signal, ensuring signal integrity, and they operate within the context of the existing USB protocol, not as a standalone generic link.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify Bai’s cross-clock-domain processing circuit as taught by Shoor to implement the re-timer 300 as a USB re-timer connected between the first device 210 and the second device 220 configured to perform a universal serial bus (USB) communication link in order to boost and clean up the signal over longer distances or through complex connections to ensure signal integrity.
Claims 2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bai in view of Ebuchi et al. (US 2010/0127739 A1), hereinafter “Ebuchi”.
Regarding claim 2, as applied to claim 1 and claim 9, as applied to claim 8, Bai fails to show or teach the detail diagram of the transmitting circuit in the first device 210 includes a phase-locked loop configured to generate a phase-locked clock signal based on the clock modulation enablement control signal and a reference clock signal.
Ebuchi illustrates a data transmitter (Tx) 100 in Figure 13 comprises an SSC-PLL 10, a parallel-serial conversion circuit (P/S) 101, and a driver circuit 102. The block diagram of the SSC-PLL 10 is shown in Figure 1 which includes at least a phase-frequency detector (PFD) 11 configured to generate a detection circuit based on a reference clock (REFCLK) and a spread spectrum controlled (SSC) signal generated by an SSC generator 16.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement Bai’s transmitter circuit of the first device 210 to include a phase-locked loop configured to generate a phase-locked clock signal based on the clock modulation enablement control signal and a reference clock signal as taught by Ebuchi in order to create a highly stable, adjustable, and synchronized timing signal for data transmission, where the PLL locks its output frequency/phase to a reference while the clock modulation enablement control signal allows for dynamic adjustment (like spreading spectrum or frequency hopping) to improve signal integrity, reduce interference (EMI), and enhance security, ensuring precise data timing across various communication protocols.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Bai in view of Shoor, as applied to claim 15, and further in view of Ebuchi.
Regarding claim 16, as applied to claim 15, similar to claims 2 and 9 described above. Bai fails to show or teach the detail diagram of the transmitting circuit in the first device 210 and Shoor also fails to show or teach the detail diagram of the transmitting circuit in the downlink port 101 include a phase-locked loop configured to generate a phase-locked clock signal based on the clock modulation enablement control signal and a reference clock signal.
Ebuchi illustrates a data transmitter (Tx) 100 in Figure 13 comprises an SSC-PLL 10, a parallel-serial conversion circuit (P/S) 101, and a driver circuit 102. The block diagram of the SSC-PLL 10 is shown in Figure 1 which includes at least a phase-frequency detector (PFD) 11 configured to generate a detection circuit based on a reference clock (REFCLK) and a spread spectrum controlled (SSC) signal generated by an SSC generator 16.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement Bai’s transmitter circuit of the first device 210 to include a phase-locked loop configured to generate a phase-locked clock signal based on the clock modulation enablement control signal and a reference clock signal as taught by Ebuchi in order to create a highly stable, adjustable, and synchronized timing signal for data transmission, where the PLL locks its output frequency/phase to a reference while the clock modulation enablement control signal allows for dynamic adjustment (like spreading spectrum or frequency hopping) to improve signal integrity, reduce interference (EMI), and enhance security, ensuring precise data timing across various communication protocols.
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/Young T. Tse/Primary Examiner, Art Unit 2632