DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to claims filed 7/07/2022.
Claims 1-20 are pending.
Response to Arguments
Regarding 35 U.S.C. 112:
Applicant’s amendments and arguments regarding the rejection of claim 20 under 35 U.S.C. 112(b) have been fully considered and are found to be persuasive. The rejections of claim 20 under 35 U.S.C. 112(b) is withdrawn.
Regarding: Prior Art Rejections:
Applicant’s amendments and arguments regarding the rejection of claims 1-20 under 35 U.S.C. 103 have been fully considered and are moot due to new grounds of rejection necessitated by amendment.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Vijayaraghavan et al. US 20190050265 A1 in view of Olarig et al. US 20180267836 A1 in further view of HuangFu et al. US 20230281128 A1.
Regarding claim 1, Vijayaraghavan teaches the invention substantially as claimed including:
An information handling system, comprising:
a processor configured to instantiate machine learning code (Fig 2 Workload Orchestrator 110; [0012] workload orchestrator includes an accelerator selection processor 114 that utilizes a neural network processor 118);
a first plug-in connector interface coupled to the processor; a first accelerator module installed into the first plug-in connector interface; a second plug-in connector interface coupled to the processor; and a second accelerator module installed into the second plug-in connector interface (Fig 1 Accelerator Farm 120 with Accelerators 122, 124, 126; Fig 2 Accelerator interface 240; [0023] accelerator interface 240 may, in some examples, enable communication with multiple (e.g., two or more) different accelerator farms; [0054] The processor platform 600 of the illustrated example also includes an interface circuit 620. The interface circuit 620 may be implemented by any type of interface standard, such as such as an Ethernet interface, a universal serial bus (USB) … and/or a PCI express interface. In the illustrated example of FIG. 6, the interface circuit 620 implements the example workload interface 210 and the example accelerator interface 240; Examiner notes: Vijayaraghavan teaches multiple accelerator farms which are able to contain multiple accelerators that are able to be interfaced with via multiple forms of plug-in connectors such as ethernet, usb, PCI express. The system supporting interfacing with multiple accelerators and accelerator farms indicates there being multiple plug-in connections via ethernet, usb, PCI express);
wherein the information handling system is configured to instantiate a first workload on the processor (Fig 2 Workload Interface 210; [0012] the workload provider 105 provides a workload to the workload orchestrator 110. The example workload orchestrator includes an accelerator selection processor 114; [0020] workload interface 210 passes the workload to the accelerator selection processor 114 for processing); and
wherein the machine learning code ([0014] workload orchestrator 110 of the illustrated example of FIG. 1 is implemented by a logic circuit such as, for example, a hardware processor. However, any other type of circuitry may additionally or alternatively be used such as, for example, one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)), field programmable logic device(s) (FPLD(s)), digital signal processor(s) (DSP(s))… workload orchestrator 110 … using machine learning ; Examiner notes: workload orchestrator being processors/circuits/devices using machine learning indicates machine learning code is executed on the workload orchestrator) is configured to determine a first processing need of the first workload (Fig 5 530; [0050] accelerator selection processor 114 provides the attribute(s) of the workload to the neural network processor 118; [0041] attribute(s) may include, for example, whether the workload can be parallelized, whether the workload is resource intensive, whether the workload deals with image processing, whether the workload deals with text processing, and/or any other information about the execution of the workload and/or data to be processed in connection with the workload), and to allocate a first processing resource of the first accelerator module to the first workload based upon an evaluation of the first processing need, the first processing capability, and the second processing capability (Fig 5 540; [0024] Those neural network parameters may then be stored in the example neural network parameter memory 260. Such information may include, for example, attribute(s) of workload(s) and their corresponding selected accelerator; [0050] neural network processor 118 uses the neural network parameters stored in the example neural network parameter memory 260 to generate an indication of one or more accelerators to be used to execute the workload. (Block 530). The accelerator selection processor 114 then provides the workload to the selected accelerator(s) via the example accelerator interface 240. (Block 540); [0021] accelerator selection processor 114 uses the attributes of the subsequent workload as an input to the neural network implemented by the neural network processor 118 to identify which accelerator should be used for execution of the workload; Examiner notes: the stored neural network parameters represent the first and second processor capabilities mapped to their previously assigned workloads. The next workload is allocated to an accelerator that best suits that workload using the previous learned mappings); and
to execute the first workload on the first processing resource in response to the allocation of the first processing resource ([0050] The accelerator(s) may then execute the workload and/or portions thereof in a parallel fashion and/or in a serial fashion).
While Vijayaraghavan teaches different processors possessing different processing capabilities, it does not explicitly teach a baseboard management controller configured to determine a first characteristic of the first accelerator module and a second characteristic of the second accelerator module, and to provide the first characteristic and the second characteristic to the machine learning code; the determining of a first processing capability of the first accelerator module and a second processing capability of the second accelerator module; and allocating resources for workloads according to resource characteristics.
However, Olarig teaches a baseboard management controller configured to determine a first characteristic of the first accelerator module and a second characteristic of the second accelerator module ([0043] a traditional BMC 116 merely polls the resources of a system (e.g., system 100) and determines their capabilities and general status (e.g., temperature, fan speed, the existence of a graphical processing unit; [0049] the BMC 116 may check the availability or capability of the shared processor 118), and to provide the first characteristic and the second characteristic to the machine learning code ([0065] a capabilities table 203 may be configured to store the traditional data collected by the BMC (e.g., existence of a GPU, amount of memory, bus speed) … In one such embodiment, the capabilities tables 203 may include a listing of devices in the system and a field indicating if that device is a shared resource.); determining a first processing capability of the first accelerator module and a second processing capability of the second accelerator module ([0065]In the illustrated embodiment, the capabilities table 203 may also be configured to store information regarding the resources in the system that are shared, such as, for example if the GPU is shared, how many shaders or cores a processor has); and allocate a first processing resource of the first accelerator module to the first workload based upon an evaluation of the first characteristic, and the second characteristic ([0058] a pool of shared resources 188 may be added to a system 101. In such an embodiment, the BMC 116 may arbitrate and allocate the use of those shared resources 188 and shared processing resources 118; [0066] an availability table 206. In such an embodiment, the availability table 206 may be configured to indicate the availability state of the shared resource(s). In one embodiment, the availability table 206 may indicate the percentage of availability a shared resource may possess at a given time (e.g., 100% used, 50% used, 8 encoding transform units free, 14 vector processors used, and so on). In another embodiment, the availability table 206 may also include a prediction as to when the shared resource will be next available or other time-based measurement. In such an embodiment, the availability table 206 may be checked to see if a resource usage request can be fulfilled. If so, the availability table 206 may then be updated (e.g., by the BMC processor 204) to indicate the updated availability of the given resource. In some embodiments, this updating may include polling the resource or merely marking the whole resource as unavailable until the assigned task completes; Examiner notes: shared GPU resources are allocated work by considering availability of shared GPU resources).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Olarig’s shared GPU allocation system with BMC for system monitoring with the system of Vijayaraghavan. A person of ordinary skill in the art would have been motivated to make this combination to provide Vijayaraghavan’s system with the advantage of monitoring the system for making more informed and optimal resource allocations (see Olarig [0004] The baseboard management controller (BMC) frequently provides the intelligence in the IPMI architecture. It generally is a specialized microcontroller embedded on the motherboard of a computer—generally a server. The BMC often manages the interface between system-management software and platform hardware).
Vijayaraghavan and Olarig do not explicitly teach:
The processor being a Compute Express Link (CXL) processor,
The accelerator modules being a first CXL accelerator module and a second CXL accelerator module.
However, HuangFu teaches A Compute Express Link (CXL) processor (Fig 3 Processor 110; [0031] In FIG. 3A, processor 110 may be connected to switches 305-1 and 305-2. In FIG. 3A, switches 305-1 and 305-2 (which may be referred to collectively as switches 305) may be cache-coherent interconnect switches: for example, switches 305-1 and 305-2 may be Compute Express Link (CXL) switches), A first CXL accelerator module (Fig 4B accelerators 410-2), A second CXL accelerator module ([0039] accelerator 410-2 may be implemented directly as part of CXL memory modules 310, or accelerator 410-2 may implemented as a separate component that may be installed within or connected to CXL memory modules 310).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined HuangFu’s CXL processor and accelerators with the existing system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of high bandwidth transfers of data to-from memory (see HuangFu’s [0023] Using the Compute Express Link (CXL) protocol or some other cache-coherent interconnect protocol, data may be accessed from a memory module. The CXL or other cache-coherent interconnect protocol may provide data at a higher bandwidth than might be used to transfer data to the host processor. The processing element may be designed to perform specific near data processing tasks, and may therefore do so more efficiently than a generic processor executing commands).
Regarding claim 2, Vijayaraghavan, Olarig, and HuangFu teach the information handling system of claim 1.
Vijayaraghavan further teaches wherein the information handling system is further configured to instantiate a second workload on the processor; and the machine learning code is further configured to determine a second processing need of the second workload, and to allocate a second processing resource of the second accelerator module to the second workload based upon an evaluation of the second processing need, the first processing capability, and the second processing capability, and to execute the second workload on the second processing resource in response to the allocation of the second processing resource ([0039] As a result of the training, upon receipt of subsequent workloads, an accelerator can be selected by the neural network processor 118 using the neural network parameters stored in the neural network parameter memory 260 and attribute(s) of the subsequent workload; [Claim 1] using the machine learning model, the second attribute to select one of the at least two accelerators to execute the second workload; [0050] The accelerator(s) may then execute the workload and/or portions thereof in a parallel fashion and/or in a serial fashion);
Olarig teaches allocate a second processing resource of the second accelerator module to the second workload based upon an evaluation of the first characteristic, and the second characteristic ([0066] In such an embodiment, the availability table 206 may be checked to see if a resource usage request can be fulfilled. If so, the availability table 206 may then be updated (e.g., by the BMC processor 204) to indicate the updated availability of the given resource. In some embodiments, this updating may include polling the resource or merely marking the whole resource as unavailable until the assigned task completes; Examiner notes: when a task occupies a resource and the resource becomes unavailable, the allocation of a second task will factor in updated resource availabilities).
Regarding claim 3, Vijayaraghavan, Olarig, and HuangFu teach the information handling system of claim 2.
Vijayaraghavan further teaches wherein the processor further instantiates a database of accelerator modules and their associated processing capabilities, the database including the first accelerator module and the associated first processing capability and the second accelerator module and the associated second processing capability ([0037] accelerator selection processor 114 stores the association of the workload attribute(s) and the allocated accelerator in the training data store 245; [0024] The training data store 245 of the example of FIG. 2 is implemented by any memory, storage device and/or storage disc for storing data such as, for example, flash memory, magnetic media, optical media, etc. Furthermore, the data stored in the example training data store 245 may be in any data format such as … structured query language (SQL) structures … the example training data store 245 stores information used to train the neural network parameters. Those neural network parameters may then be stored in the example neural network parameter memory 260. Such information may include, for example, attribute(s) of workload(s) and their corresponding selected accelerator).
Regarding claim 4, Vijayaraghavan, Olarig, and HuangFu teach the information handling system of claim 3.
Vijayaraghavan further teaches wherein the machine learning code is configured to determine the first capability and the second capability from the database ([0037] accelerator selection processor 114 stores the association of the workload attribute(s) and the allocated accelerator in the training data store 245; [0038] neural network trainer 255 to train neural network parameters stored in the example neural network parameter memory 260 based on the workload attribute(s) and selected accelerator(s)).
Regarding claim 5, Vijayaraghavan, Olarig, and HuangFu teach the information handling system of claim 1,
Vijayaraghavan further teaches wherein the machine learning code includes at least one neural network ([0038] neural network trainer 255 stores the neural network parameters in the neural network parameter memory 260. (Block 380). The example neural network trainer 255 performs training of the neural network implemented by the neural network processor 118).
Regarding claim 11, it is the method of claim 1. Therefore, it is rejected for the same reasons as claim 1.
Regarding claims 12-15, they are the methods of claims 2-5 respectively. Therefore, they are rejected for the same reasons as claims 2-5 respectively.
Claims 6-10 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Vijayaraghavan et al. US 20190050265 A1 in view of Olarig et al. US 20180267836 A1 in view of HuangFu et al. US 20230281128 A1 in further view of Zhao et al. US 20200133735 A1.
Regarding claim 6, Vijayaraghavan, Olarig, and HuangFu teach the information handling system of claim 5.
Vijayaraghavan, Olarig, and HuangFu do not explicitly teach wherein the at least one neural network includes a Generative Adversarial Network (GAN) to allocate the first processing resource to the first workload.
However, Zhao teaches wherein the at least one neural network includes a Generative Adversarial Network (GAN) to allocate the first processing resource to the first workload (Fig 1 Deep Learning Model 110; [0026] The deep learning model 110 may be a machine learning model of any deep learning model, including … Generative Adversarial Networks (GAN); Fig 2 Task allocations 200; Fig 3 302, 304).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Zhao’s utilization of GAN to allocate tasks to resources with the machine learning resource allocation system of Vijayaraghavan, Olarig and HuangFu. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of utilizing available machine learning techniques known in the art to more efficiently allocate different resources (see Zhao [0021] Dedicated processing resources (such as accelerator devices) are widely used as accelerators for many applications, such as machine learning applications and deep neural network (DNN) learning applications, due to their high-performance advantages (such as multi-core and suitability for matrix operations). Generally, for high-performance computing tasks, multiple dedicated processing resources are usually required to be executed concurrently. These multiple dedicated processing resources may have different device types due to the different purchase orders; [0026]).
Regarding claim 7, Vijayaraghavan, Olarig, HuangFu, and Zhao teach the information handling system of claim 6.
Vijayaraghavan further teaches wherein in training the GAN, the machine learning code is further configured to receive the first workload ([0040] workload interface 210 accesses a workload provided by the workload provider 105. (Block 410). In examples disclosed herein, the workload is received via a web interface (e.g., the Internet). However, the example workload may be received in any other fashion. In some examples, the workload interface 210 may receive multiple workloads) and in response, to determine a first performance metric for the first workload on the first accelerator module ([0042] accelerator selection processor 114 provides a workload (e.g., the received workload) to an identified accelerator for execution via the accelerator interface 240. (Block 430); [0043] accelerator selection processor 114 accesses performance metrics of the workload execution via the accelerator interface 240. (Block 435)).
While Vijayaraghavan and Olarig do not explicitly teach determining that the first workload is not a first in time workload received by the machine learning code then if so, determining a first performance metric for the first workload on the first accelerator module.
However, Vijayaraghavan teaches determining that the first workload is not a first in time workload received by the machine learning code then if so, determining a first metric for the first workload on the first accelerator module ([0015] Upon receipt of a subsequent workload, the example accelerator selection processor 114 uses the attributes of the subsequent workload as an input to the neural network (e.g., the neural network implemented by the neural network processor 118) to identify which accelerator should be used for execution of the workload).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Vijayaraghavan’s detection of whether or not a job is a first job with the performance metric determination of Vijayaraghavan and Olarig’s machine learning resource allocation system. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of utilizing previous metrics from allocations to inform a future allocation decision (see Vijayaraghavan [0039] As a result of the training, upon receipt of subsequent workloads, an accelerator can be selected by the neural network processor 118 using the neural network parameters stored in the neural network parameter memory 260 and attribute(s) of the subsequent workload).
Regarding claim 8, Vijayaraghavan, Olarig, HuangFu, and Zhao teach the information handling system of claim 7.
Vijayaraghavan further teaches wherein in training the GAN, the machine learning code is further configured to provide an adversarial allocation of the first workload on the information handling system, and to determine a second performance metric for the first workload based upon the adversarial allocation ([0043] accelerator selection processor 114 determines whether there are any other accelerators that may be used to execute the workload. (Block 440). If an additional accelerator exists (e.g., block 440 returns a result of YES), the example process of blocks 430 through 440 is repeated to create performance metrics for the workload in combination with each of the accelerators).
Regarding claim 9, Vijayaraghavan, Olarig, HuangFu, and Zhao teach the information handling system of claim 8.
Vijayaraghavan further teaches wherein in training the GAN, the machine learning code is further configured to make a prediction as to whether the first performance metric is a higher performance metric than the second performance metric ([0042] a portion of the workload is provided to the accelerator. Providing a portion of the workload ensures that, for workloads that would otherwise take long amounts of time to complete, the workload can be completed in a shorter amount of time. As a result, the amount of time required to determine which accelerator should be selected is reduced; [0044] accelerator selection processor 114 selects an accelerator based on the collected performance metrics. (Block 445). For example, the accelerator selection processor 114 may select an accelerator that resulted in the shortest execution time).
Regarding claim 10, Vijayaraghavan, Olarig, HuangFu, and Zhao teach the information handling system of claim 9.
Vijayaraghavan further teaches wherein in training the GAN, the machine learning code is further configured to train the GAN based upon the prediction ([0044] accelerator selection processor 114 stores an association of the workload attribute(s) and the corresponding selected accelerator in the training data store 245. (Block 450); [0024] training data store 245 stores information used to train the neural network parameters).
Regarding claims 16-19, they are the methods of claims 6-9 respectively. Therefore, they are rejected for the same reasons as claims 6-9 respectively.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Vijayaraghavan et al. US 20190050265 A1 in view of HuangFu et al. US 20230281128 A1 in further view of Ramesh US 20220214923 A1.
Regarding claim 20, it is the information handling system of claim 1 which utilizes memory riser module capabilities to inform allocations. Therefore, it is rejected for the same reasons as claim 1.
Vijayaraghavan does not explicitly teach a Compute Express Link (CXL) processor, a first CXL memory riser module, a second CXL memory riser module.
However, HuangFu teaches a Compute Express Link (CXL) processor (Fig 3 Processor 110; [0031] In FIG. 3A, processor 110 may be connected to switches 305-1 and 305-2. In FIG. 3A, switches 305-1 and 305-2 (which may be referred to collectively as switches 305) may be cache-coherent interconnect switches: for example, switches 305-1 and 305-2 may be Compute Express Link (CXL) switches), a first CXL memory riser module installed into the first plug-in connector interface, a second CXL memory riser module installed into the first plug-in connector interface ([0032] CXL memory modules 310-1 through 310-6 (which may be referred to collectively as memory modules 310): CXL switch 305-1 may be connected to CXL memory modules 310-1 through 310-3, and CXL switch 305-2 may be connected to CXL memory modules 310-4 through 310-6. CXL memory modules 310 may be any desired type of memory modules: for example, CXL memory modules 310 may be Dual In-Line Memory Modules (DIMMs), and may be used as DRAM; [0147] the first CXL memory module includes a first CXL interface; [0148] the second CXL memory module includes a second CXL interface; and [0149] the CXL switch connects the first CXL memory module using the first CXL interface and the second CXL memory module using the second CXL interface).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined HuangFu’s CXL processor and memory modules with the existing system of Vijayaraghavan. A person of ordinary skill in the art would have been motivated to make this combination to provide the resulting system with the advantage of of high bandwidth transfers of data to-from memory (see HuangFu’s [0023] Using the Compute Express Link (CXL) protocol or some other cache-coherent interconnect protocol, data may be accessed from a memory module. The CXL or other cache-coherent interconnect protocol may provide data at a higher bandwidth than might be used to transfer data to the host processor. The processing element may be designed to perform specific near data processing tasks, and may therefore do so more efficiently than a generic processor executing commands).
Vijayaraghavan and HuangFu do not explicitly teach wherein machine learning code is configured to determine a first processing capability of the first memory riser module and a second processing capability of the second memory riser module
However, Ramesh teaches wherein code is configured to determine a first processing capability of the first memory module and a second processing capability of the second memory module and to allocate a first processing resource of the first accelerator module to the first workload based upon an evaluation of the first processing need, the first processing capability, and the second processing capability ([0017] The hardware circuitry can, based on the monitored or determined characteristics of the workloads, write at least a portion of the workload to a different type of memory device. For example, if the workload is executed while the data corresponding to the workload is stored in a volatile memory device and the hardware circuitry determines that execution of the workload can be optimized if the data corresponding to the workload is stored in a non-volatile memory device, the hardware circuitry can cause at least a portion of the data corresponding to the workload to be written to the non-volatile memory device; [0018] the workload can be optimized can include optimizing battery consumption of the computing system, bandwidth associated with the computing system, computing resource consumption associated with the computing system, and/or speed of execution of the workload by the computing system, among others … high power consumption memory devices … a memory device that is characterized by a lower power consumption; [0019] workload can be optimized can include optimizing execution of the workload by utilizing memory devices and/or media types that exhibit different memory capacities versus bandwidth capabilities … a memory device that exhibits high capacity but low bandwidth (e.g., a NAND memory device … a memory device that exhibits high bandwidth but low capacity (e.g., a 3D stacked SDRAM memory device));
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined Ramesh’s allocation of workloads to optimal memories with the machine learning resource allocation system of Vijayaraghavan and HuangFu. A person of ordinary skill in the art would have been motivated to make this combination to provide Vijayaraghavan and HuangFu’s system with the advantage of providing the optimal memory resources for processing the received workloads (see at least Ramesh [0002] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory … ; [0010] data corresponding to execution of workloads executed within a memory system can be selectively written to different types of memory within the memory system).
Conclusion
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/H.L./
Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195