DETAILED ACTION
Claims 1-40 are currently pending in the application. Claims 1-20 are original claims to patent US 10,761,775 B2 and claims 21-40 are newly added claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 has been entered.
Reissue
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,761,775 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Information Disclosure Statement
In order to have information considered by the Office during the pendency of a patent application, an information disclosure statement (IDS) must be: (1) in compliance with the content requirements of 37 CFR 1.98; (2) filed in accordance with the procedural requirements of 37 CFR 1.97; and (3) signed in compliance with 37 CFR 1.33(b). See MPEP 609.
This application contains several documents provided by Patent Owner which have not been cited in an IDS, including at least: “NVME_IDENTIFY_CONTROLLER_DATA structure (nvme.h)”; “smartctl NVMe SSD: what is ‘Maximum Data Transfer Size’?”; “NVM Express 1.2”, 11/03/2014; “NVM Express 1.2b”, 06/01/2016; and “NVM Express 1.2.1”, 06/05/2016.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-25, and 27-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0212759 A1, published 07/30/2015 (herein Jo) in view of US 2015/0095554 A1, published 04/02/2015 (herein Asnaashari) in further view of “NVM Express, Revision 1.2”, published 11/30/2014 (herein NVM Express).
Claim 21
Jo, Asnaashari, and NVM Express
A storage device, comprising: a controller connected to a memory device, wherein the controller is configured to:
Jo discloses a storage device (Jo: figure 1, element 100) with a memory device (Jo: figure 1, element 124, flash memory) connected to a controller (Jo: figure 1, the storage device elements other than the flash memory).
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obtain a command from a host device, wherein data associated with the command exceeds a maximum data transfer size (MDTS) associated with the storage device;
Jo discloses obtaining a command (Jo: figures 3-5; paragraphs 0044-0055; a program command 300) from a host device (Jo: figure 1, element 200).
Jo does not explicitly state “wherein data associated with the command exceeds a maximum data transfer size (MDTS) associated with the storage device”.
Asnaashari demonstrates that it was known before the effective filing date of the claimed invention to operate memory access in an SSD environment using a NVMe protocol with PCIe (Asnaashari: paragraphs 0005-0006, 0029-0030). Jo demonstrates it was known to operate its memory access devices and transfer command teachings in an SSD environment with PCIe (Jo: paragraphs 0031-0033). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the SSD memory transfer commands and devices of Jo as part of an NVMe protocol as suggested by Asnaashari’s teachings. This implementation would have been obvious because one of ordinary skill in the art would have found: the implementation of is an application of a known element/technique yielding a predictable result using an acceptable piece of prior art; and both references are directed toward SSD and various memory access protocols including NVMe’s related PCIe (Jo: paragraphs 0031-0033; Asnaashari: paragraphs 0005-0006, 0029-0030).
Further, NVM Express demonstrates it was known before the effective filing date of the claimed invention for the NVMe protocol of Asnaashari to include a maximum data transfer size (MDTS) (NVM Express: page 98, Maximum Data Transfer Size, MDTS; page 8, section 1.1) in an SSD environment using PCIe (NVM Express: page 8, section 1.4). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the memory transfer commands and devices of Jo as part of an NVMe protocol such that data associated with a command exceeds a maximum data transfer size (MDTS) associated with the storage device as suggested by the teachings of Asnaashari and NVM Express. This implementation would have been obvious because one of ordinary skill in the art would have found: the implementation of is an application of a known element/technique yielding a predictable result using an acceptable piece of prior art; and all the references are directed toward SSD memory access.
Therefore, Jo shows a command is obtained from a host, and in view of Asnaashari and NVM Express, the data associated with the command exceeds a maximum data transfer size (MDTS) associated with the storage device.
generate first commands based on the data associated with the command exceeding the MDTS associated with the storage device and process the first commands; and
Jo discloses generating sub-commands when a command’s associated data exceed a maximum (Jo: figures 5 and 12; paragraphs 0044-0055, and 0069).
Jo shows a command is obtained from a host, and in view of Asnaashari and NVM Express, the data associated with the command exceeds a maximum data transfer size (MDTS) associated with the storage device.
However, to the extent Jo does not explicitly state “generate first commands based on the data associated with the command exceeding the MDTS”. Jo demonstrates that it was known before the effective filing date of the claimed invention to generate commands when data exceeds a memory device’s maximum capability (Jo: paragraphs 0048, 0051-0052) and that it is desirable to send commands efficiently as a single command (Jo: paragraph 0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the memory transfer commands and devices of Jo with generating sub-commands based on the data associated with the command exceeding the MDTS associated with the storage device (a device’s maximum capability) as suggested by the teachings of Jo. This implementation would have been obvious because one of ordinary skill in the art would have found: the implementation of is an application of a known element/technique yielding a predictable result using an acceptable piece of prior art; Jo dividing a command is obvious in an SSD environment with MTDS, in view of Asnaashari and NVM Express; and Jo teaches the desirability/efficiency of a single command that is divided (Jo: paragraph 0051), which if exceeding a maximum capability (such as MTDS shown by Asnaashari and NVM Express) must be divided (Jo: paragraph 0051; figures 3-5; paragraphs 0044-0055, for example a program command 300 with a data size portion of 12KB being larger than what can be transferred into the memory block maximum of 4KB).
“Referring to FIGS. 1, 2 and 12, the data processing method comprises receiving a command from the host 200 in the storage device 100, and verifying the validity of the command (S901). Next, the received and verified command is divided into multiple unit commands (S903). Resulting first DMA requests are generated according to certain unit commands, while resulting second DMA requests are generated by other unit commands (S905). Thereafter, the first DMA operations and the second DMA operations respectively associated with the first DMA requests and second DMA requests are initiated using a multi-processing unit including the first processing unit 110 and the second processing unit 112 (S907).” (Jo: paragraph 0069)
“… For example, the data size information 304 portion of the command 300 may include a value of ‘12 KB’ indicating that each block of write data provided in associated with the command 300 has a size of 12 KB. Thus, assuming that each of the memory blocks 150, 152, 154, 156, 158, 160, 162 and 164 provided by the flash memory 124 of the storage device 100 has a size of 4 KB, each memory block of write
data (e.g., 314) processed by the storage device 100 in response to the command 300 will require three (3) memory blocks (e.g., 152, 154 and 156) of the flash memory 124.” (Jo: paragraph 0048)
“Assuming the efficient use of a single program command 300 to program all three (3) 4KB sets of write data to the flash memory 124, the program command 300 may be divided by operation of the command division unit 140 into a plurality of unit commands (e.g., 320, 322 and 324). This "division" of a single program command may result in the re-definition of logical address(es), corresponding physical address(es), and/or data size(s) associated with the three (3) sets of write data in relation to one or more of the unit commands 320, 322 and 324. For example, in certain embodiments of the inventive concept, the command division unit 104 of the storage device 100 may define data set size(s) for each one of the respective unit commands 320, 322 and 324 in view of (e.g.,) various data storage characteristics of the flash memory 124, such as minimum program data size (e.g., 4KB or 8 KB), minimum data block size (e.g., 4KB or 8KB), etc.” (Jo: paragraph 0051, emphasis added)
“In FIG. 4, assuming that each one of the sets of write data 320, 322 and 324 has a size of 4KB and further assuming program data size constraints allowing 4KB to be stored in each memory block BLK1, BLK2 and BLK3, execution of three (3) corresponding unit commands 320, 322 and 324 for each set of write data will result in programming of the respective write data sets to BLK 1, BLK 2, and BLK 3 in the flash memory 124. Thereafter, read data having a size of 4 KB may be readily retrieved from each one of memory block 152 (BLK1), 154 (BLK2) and/or 156 (BLK3) in response to one or more read commands received from host 200 and corresponding unit commands provided by the command division unit 104. Consistent with the foregoing, a plurality of unit commands (e.g., unit program commands 320, 322 and 324) may be respectively distributed to the first processing unit 106 and/or the second processing unit 116 by the command division unit 104.” (Jo: paragraph 0052, emphasis added)
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transmit a notification, based on the processing the first commands, to the host device.
Jo discloses transmitting a notification to the host based on completion of the first commands (Jo: figure 13; paragraphs 0070 and 0043).
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Claim 22
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller tracks the number of first commands.
Jo discloses tracking the first commands by tracking the corresponding requests (Jo: figure 13; paragraphs 0070 and 0043).
Claim 23
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller generates the first commands in an order based on addresses provided by the host device.
Jo discloses generating the first commands in an order based on addresses provided by the host command (Jo: figures 3-4, note the initial block being divided into 3 consecutive blocks; paragraphs 0051-0052).
Claim 24
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller generates the first commands in an order based on a command size.
Jo does not explicitly state “the controller generates the first commands in an order based on a command size”. Asnaashari demonstrates that it was known before the effective filing date of the claimed invention to generate commands and order based on command size (Asnaashari: paragraph 0081, the commands are ordered or structured such that an attempt is made to fill the entire memory size with NVMe commands). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the ordered generation of commands in Jo with generating in an order based on command size as suggested by Asnaashari’s teachings. This implementation would have been obvious because one of ordinary skill in the art would have found: Jo would also desire efficient use of the entire memory size; the implementation of is a substitution and application of one known element and technique for another yielding a predictable result using an acceptable piece of prior art; and both references are directed to memory access of host commands using sub-commands.
Claim 25
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller operates in connection with a non-volatile memory express (NVMe) protocol.
Jo does not explicitly state “the controller operates in connection with a non-volatile memory express (NVMe) protocol”. Asnaashari demonstrates that it was known before the effective filing date of the claimed invention to operate memory access in an SSD environment using a NVMe protocol with PCIe (Asnaashari: paragraphs 0005-0006, 0029-0030). Jo demonstrates it was known to operate its memory access devices and transfer command teachings in an SSD environment with PCIe (Jo: paragraphs 0031-0033). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the SSD memory transfer commands and devices of Jo as part of an NVMe protocol as suggested by Asnaashari’s teachings. This implementation would have been obvious because one of ordinary skill in the art would have found: the implementation of is an application of a known element/technique yielding a predictable result using an acceptable piece of prior art; and both references are directed toward SSD and various memory access protocols including NVMe’s related PCIe (Jo: paragraphs 0031-0033; Asnaashari: paragraphs 0005-0006, 0029-0030).
Claim 27
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller obtains metadata associated with the command.
Jo discloses host command metadata (Jo: paragraphs 0045-0047) for the controller (Jo: paragraph 0048-0052).
Claim 28
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the generating the first commands or the processing the first commands is based on a quality of service.
Jo discloses the broadest reasonable interpretation of generating based on a quality of service (Jo: paragraph 0051, “assuming the efficient use”, that is a measure of quality).
Claim 29
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller further generates second commands based on the notification.
Jo is capable of processing additional commands, that may be sub-divided (generating second sub-commands) after completion of the first command operation.
Claim 30
Jo, Asnaashari, and NVM Express
The storage device of claim 21, wherein the controller
obtains a second command from the host device and transmits the second command to a second device.
Asnaashari shows a controller (Asnaashari: figure 1, the storage device elements other than the plurality of SSD NVMes) sending other commands to other devices (Asnaashari: figure 1, the plurality of SSD NVMes; see also paragraphs 0029-0030).
Claims 31-32, 34, 37, and 39
Jo, Asnaashari, and NVM Express
The limitations of claims 31-32, 34, 37, and 39 correspond to the limitations of claims 21-23 and 27-28.
The limitations of claims 31-32, 34, 37, and 39 are rejected in a corresponding manner to the limitations of claims 21-23 and 27-28.
Claim 33
Jo, Asnaashari, and NVM Express
The limitations of claim 33 correspond to the limitations of claim 24.
The limitations of claim 33 are rejected in a corresponding manner to the limitations of claim 24.
Claims 35-36, and 40
Jo, Asnaashari, and NVM Express
The limitations of claims 35-36, and 40 correspond to the limitations of claims 29-30.
The limitations of claims 35-36, and 40 are rejected in a corresponding manner to the limitations of claims 29-30.
Claim 38
Jo, Asnaashari, and NVM Express
The limitations of claim 38 correspond to the limitations of claims 23 and 24.
The limitations of claim 38 are rejected in a corresponding manner to the limitations of claims 23 and 24.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0212759 A1, published 07/30/2015 (herein Jo) in view of US 2015/0095554 A1, published 04/02/2015 (herein Asnaashari) in view of “NVM Express, Revision 1.2”, published 11/30/2014 (herein NVM Express) in further view of US 2015/0255130 A1, published 09/10/2015 (herein Lee).
Claim 26
Jo, Asnaashari, NVM Express and Lee
The storage device of claim 21, wherein the controller operates in connection with a flash translation layer (FTL) of the storage device to process at least a portion of the first commands.
Jo does not explicitly state “the controller operates in connection with a flash translation layer (FTL) of the storage device to process at least a portion of the first commands”. Lee demonstrates that it was known before the effective filing date of the claimed invention to operate memory access in connection with a flash translation layer (Lee: paragraphs 0006 and 0034). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the system and processes of commands in Jo with using a flash translation layer as suggested by Lee’s teachings. This implementation would have been obvious because one of ordinary skill in the art would have found: the implementation of is a substitution and application of one known element and technique for another yielding a predictable result using an acceptable piece of prior art.
Response to Arguments
Patent Owner’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: (A) claims 1-20 are allowable as a search of the claimed subject matter did not result in any additional prior art than that which had already been applied in the preceding prosecution 16/107,969.
Correspondence Information
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/William H. Wood/
Reexamination Specialist, CRU 3992
Conferees:
/RACHNA S DESAI/Reexamination Specialist, Art Unit 3992
/ALEXANDER J KOSOWSKI/Supervisory Patent Examiner, Art Unit 3992