DETAILED ACTION
1. Claims 1-25 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 1, 6-7, 11, 13-14, 16, 17, 19, 20, 22, and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boesch et al (hereafter Boesch)(US Pub. 2018/0189642) in view of Nicol (US Pub. 2020/0167309).
Boesch was cited in the IDS filed 04/05/2023.
5. As to claim 1, Boesch discloses a convolutional accelerator ([0075] convolution accelerator), comprising:
a feature line buffer ([0075] feature line buffer);
a kernel buffer ([0075 kernel buffer);
a multiply-accumulate cluster coupled to the feature line buffer and the kernel buffer ([0075] a multiply-accumulate (MAC) unit module having a plurality of MAC units arranged to multiply data passed from the kernel buffer with data passed from and the feature line buffer.).
6. Boesch does not teach or suggest at least iteration control circuitry, which, in operation, defines a plurality of sub-tensors of a streamed feature data tensor, wherein the convolutional accelerator, in operation, decomposes a kernel into a plurality of sub-kernels and iteratively convolves the sub-kernels with respective sub-tensors of the defined plurality of sub-tensors of the streamed feature data tensor.
However, Nicol discloses at least iteration control circuitry ([0042] iterative techniques), which, in operation, defines a plurality of sub-tensors of a streamed feature data tensor ([0089]-[0091]), wherein the convolutional accelerator, in operation, decomposes a kernel into a plurality of sub-kernels ([0031] and[0058] kernels decomposed/partitioned into sub-kernels) and iteratively convolves the sub-kernels with respective sub-tensors of the defined plurality of sub-tensors of the streamed feature data tensor ([0113] convolution operations).
7. Therefore, it would have been obvious to one of ordinary skill in the prior to the effective filing date of the claimed invention to modify the teachings of Boesch by implementing the iteration control circuitry as in Nicol, for the benefit of more efficient data analysis and tensor computations (Nicol [0005]-[0007]).
8. As to claims 6, 13, 16, 19, and 24, the combination of Boesch and Nicol discloses wherein the streamed feature data tensor is organized into a number of batches, each batch having a same height, a same width and a same depth, and an iteration for a sub-kernel has an iteration length equal to the number of batches (Boesch [0152] and Nicol [0069]).
9. As to claims 7, 14, and 20, the combination of Boesch and Nicol discloses wherein the streamed feature data tensor is repeatedly streamed to the convolutional accelerator during the iterative convolving of the sub- kernels with the respective sub-tensors (Nicol [0089]-[0091]).
10. As to claims 11, 17, 22 and 25, the claims are rejected for similar reasons as to claim 1 above.
11. Claim(s) 2-3, 12, 18, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Boesch and Nicol and further in view of Ovsiannikov (US Pub. 20200336155).
12. As to claims 2, 12, and 18, the combination of Boesch and Nicol does not disclose wherein the iteration control circuitry, in operation, generates sets of pointers to define windows of the streamed feature data tensor, the windows corresponding to respective sub-tensors of the plurality of sub-tensors.
However, Ovsiannikov discloses wherein the iteration control circuitry, in operation, generates sets of pointers to define windows of the streamed feature data tensor, the windows corresponding to respective sub-tensors of the plurality of sub-tensors ([0124]-[0128] pointers, windows).
13. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Boesch and Nicol with the set of pointers generated as in Ovsiannikov for the benefit of of compressing and decompressing multichannel bit streams in parallel (Ovsiannikov [0002]).
14. As to claims 3 and 23, the combination of Boesch, Nicol, and Ovsiannikov discloses wherein a set of pointers defining a respective window comprises a first line pointer, a last line pointer, a first column pointer, and a last column pointer (Ovsiannikov [0128]).
Allowable Subject Matter
15. Claims 4-5, 8-10, 15, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites at least generates the first line pointer based on a vertical position of the sub-kernel in the kernel, and a vertical iteration offset parameter defined for the kernel decomposition; generates the last line pointer based on the vertical position of the sub-kernel in the kernel, a number of vertical iterations parameter defined for the kernel decomposition, the vertical iteration offset parameter, and a height of the streamed feature data tensor; generates the first column pointer based on the horizontal position of the sub-kernel in the kernel, and a horizontal iteration offset parameter defined for the kernel decomposition.
Claims 8, 15, and 21 recite at least wherein the convolutional accelerator, in operation, defines decomposition control parameters including: an iteration period, ITER_PERIOD, defining a length of an iteration of the convolving of a sub-kernel with a respective sub-tensor; a horizontal offset, ITER_OFFSET_H, defining an offset between adjacent sub-kernels in the horizontal direction; a vertical offset, ITER_OFFSET_V, defining an offset between adjacent sub-kernels in the vertical direction; a number of horizontal operations, ITERNRH, defining a number of horizontal operations performed during an iteration associated with a sub-kernel; and a number of vertical operations, ITERNRV, defining a number of vertical operations performed during an iteration associated with a sub-kernel.
The closest prior art of record US Pub. 2018/0189642 teaches a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch. However, the prior art of record does not teach the limitations above as claimed.
Conclusion
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151